FR2482800A1 - PROTECTION DEVICE OF A POWER AMPLIFIER, AND TRANSMITTER COMPRISING SUCH A DEVICE - Google Patents

Abstract

The device consists of an inverter which takes in the signal input and provides the input to the power amplifier and a logic circuit. The circuit contains an anomaly detector connected to the signal input and the power amplifier output and a switched shunt across the power amplifier input. The power amplifier is an MOS transistor with input to its gate, and output from its drain with its source taken to ground. The anomaly detector consists of an inverter with a rise time greater than that of the first inverter and the power amplifier, connected to one input of an AND gate, the other gate input being connected to the drain of the power amplifier. The gate output is connected to the gate of an MOS transistor which shunts the power amplifier input, and to a latched input of an alarm circuit. The power amplifier and alarm and protection may be integrated on the same substrate.

Description

 The invention relates to a device for protecting a power amplifier and more particularly to a device for protecting against overcurrents.

 One solution to protect an amplifier is to size it to withstand overcurrents. However, this first solution has the drawback of considerably increasing the cost and the size of the equipment and, moreover, it cannot be used if it is desired to obtain a protection device that can be easily integrated.

 Another solution is to use discrete components such as fuses, resistors with a positive or negative temperature coefficient, which cannot be integrated.

 The invention provides an easily integrated protection device which protects the amplifier in the presence of an anomaly, before deterioration occurs, and which returns to the initial state as soon as the anomaly disappears.

 According to a characteristic of the invention, the protection device of a power amplifier, comprises a first inverter whose input is connected to the output of the circuit which supplies the signal to be amplified, and whose output is connected to the terminal input of the amplifier, and a logic protection circuit which includes means for detecting an anomaly which are connected on the one hand to the output terminal of the amplifier and on the other hand to the input of the first inverter, and amplifier blocking means connected on the one hand to the output of the previous means and on the other hand to the input terminal of the amplifier.

 According to another characteristic of the invention, the protection device relates to the protection of a MOS type transistor used as an amplifier having a response time 0, the gate of which, constituting the input terminal, is connected to the output of the first inverter having a response time 91, the source of which is connected to ground, and the drain of which, constituting the output is connected via a load resistor to the supply voltage source, the means for detecting anomalies include a second inverter, with a response time e2 greater than O + 61, the input of which is connected to the input of the first inverter, and a logic "AND" gate of which one of the inputs is connected to the output of the second inverter, and the other input of which is connected to the drain of the amplifier transistor, and the blocking means comprise an MOS type transistor whose gate is connected to the output of the "AND" gate of the anomaly detection means, the source is connected to ground and whose the drain is connected to the gate of the amplifier transistor.

 According to another characteristic of the invention, the protection device comprises an alarm circuit.

 According to another characteristic of the invention, the protection device can be integrated and can be integrated on the same substrate as the amplifier transistor.

Other characteristics of the present invention will appear more clearly on reading the following description of an exemplary embodiment, this description being made in relation to the appended figures in which - FIG. 1 schematically represents a transmitter classic
comprising a MOS type transistor as an amplifier
power to transmit information on a line to
pulse transformer; - Figure 2 gives the time diagrams relating to the function
emitter of FIG. 1, on the one hand in function-
otherwise normal, on the other hand in the event of anomalies - Figure 3 represents an emitter identical to that of the
Figure 1, but equipped with an amplifier protection device
power ficator according to the invention - Figure 4 gives the time diagrams relating to the function
Figure 3 transmitter operation
FIG. I represents, diagrammatically, a conventional transmitter which comprises a power amplifier constituted by a MOS type transistor 1 whose gate G constitutes the input terminal, whose source S is connected to ground, and whose drain D constitutes the output terminal.

 In our example, this transmitter is intended to transmit on a line with pulse transformer 2 of ratio n ..

 The transmission line is connected to the terminals L and L 'of the secondary winding of the transformer 2, and the primary winding is connected on the one hand to the output terminal D of the transistor 1 and on the other hand to the source of supply voltage VDD.

 In our example, the digital information F received at the input of the transmitter must be transmitted on the line in code RZ ("return to zero"). This is why, this transmitter comprises as input a logic gate "AND" 3 of which one of the inputs receives the signal F to be amplified and transmitted, whose other input receives a clock signal H which gives the template of the pulses to be transmitted and the output of which is connected to the input terminal G of amplifier 1.

 Figure 2 gives diagrams of the times relating to the operation of the transmitter shown in Figure 1.

 Line 1 represents the information signal F.

 Lines 2 to 5, grouped by a vertical brace, are.

relating to normal operation N of the transmitter.

 Line 2 represents the clock signal H, and line 3 represents the signal C coming from the "AND" logic gate 3, which supplies the information F coded in code RZ ("return to zero").

 Line 4 represents the signal D from amplifier 1.

When the signal H is in the logic state "1" at the same time as the signal F, the signal C, and therefore the gate G of the transistor, is in the logic state "I"; which results in transistor 1 being on and therefore signal D goes to logic level "O".

The transistor has a low impedance and generates a current through the primary of the transformer 2; the value of the current is given by the transformation ratio n of the transformer 2.

In pulse mode, the series load resistance seen by R2 the amplifier is equal to R1 + nz, R1 being the resistance of the primary winding and R2 the resistance of the secondary winding.

 When the signal C returns to the state "O", the gate G of the transistor 1 is, therefore, in the state "0" and the transistor 1 is again blocked; it presents an infinite impedance and cuts the primary current, and consequently the secondary current. Signal D returns to state "1".

 Line 5 shows diagrammatically the value of the current I which flows in the primary winding of the transformer 2 and in the transistor 1, and which takes the value Io when the signal C is at logic level "1".

 Lines 6 to 9, grouped together by a vertical brace, relate to DC operation in the event of an online short circuit, that is to say on the transformer secondary.

 Lines 6 and 7 are identical to lines 2 and 3 respectively.

 Since there is a short circuit in the secondary, the secondary resistance reduced to the primary is zero and the load resistance of the amplifier becomes Ri which is very low (less than 1 Q). When the signal C is at level "1", the, transistor I must support the supply voltage VDD between its drain D and source S terminals. The signal D shown in FIG. 8 is at logic level "1". A large current IM, shown on line 9, flows through transistor 1, and the high power dissipated in transistor 1 deteriorates it.

 Lines 10 to 13, grouped by a vertical brace, relate to DC operation in the event of a clock signal permanently blocked at level "1".

 Line 10 represents the clock signal H which passes from level "O" to level and remains blocked at "1".

 Line 11 represents the signal C which is permanently at level "1", when the information signal F is at level "1". Its gate being at level "1", the MOS type transistor 1 is on and a continuous level appears across the terminals of the pulse transformer 2; consequently, amplifier 1 no longer has any resistance or load except the very low resistance of primary Ri (less than 1 Q).

The signal D represented on line 12 is permanently at "1" and a strong current IM represented on line 13 passes through the transistor 1, which dissipates a very large power as long as
signal C remains at level "1", which deteriorates it and risks
destroy it.

Figure 3 shows an example of an available
protective sitive, in accordance with the invention, and relating to
the transmitter that has just been described.

 In Figures 1 and 3, identical elements have the same references.

The transmitter shown in Figure 3, includes an amplifier
power cator constituted by a MOS type transistor 1,
having a response time 6, the source S of which is connected to the
ground, a pulse transformer 2 of ratio n whose winding
elementary is connected on one side to the drain D of transistor 1
and on the other side to the supply voltage source VDD, and
whose secondary winding has its terminals L and L 'connected
to the transmission line.

The transmitter also includes a "NAND" logic gate 4
one of whose inputs receives the information signal F, of which
the other input receives the clock signal H and the output of which
provides signal A.

The transmitter finally includes a protection device 5
which includes a first inverter 6, having a response time 61,
whose input is connected to the output of the "NAND" gate 4 and
whose output supplies the signal C to the input G of transistor 1,
a protection logic circuit 7 and an alarm circuit 8.

The protection logic circuit 7 comprises means for
detection of operating anomalies consisting of a second
inverter 9, having a response time 62, the input of which is
connected to the output of the "NAND" door 4 from which it receives
signal A, by an "AND" logic gate 10, one of the inputs
is connected to the drain D of transistor 1, and the other input of which
is connected to the output of the inverter 9 which provides it with a
signal B.

In addition, the protection logic circuit 7 includes
means for blocking the amplifier constituted by a MOS type transistor 11 of which the source S 'is connected to ground,
whose gate G 'is connected to the output of the "AND" circuit 10 which supplies it with a signal E, and whose drain D' is connected to the gate
G of the amplifier transistor 1.

 The alarm circuit 8 consists of a flip-flop 12 for storing the alarm, the input of which is connected to the output of the "AND" circuit 10 from which it receives the signal E, and the output of which is connected to the input of triggering of a device 13 capable of providing an alarm which can be, for example, a visual alarm, or a supervisory member.

 The operation of the transmitter fitted with the protection device 5 is described below using the time diagrams represented in FIG. 4.

 Line 1 represents the information signal F.

Line 2 represents the clock signal H and
line 3 represents signal A, which comes from logic gate "NAND" 4 and which is equal to FH

 Line 4 represents the signal B which comes from the inverter 9 and which is the inverse of the signal A.

 Line 5 represents the signal C from the inverter 6.

 In the initial conditions given at time to the information signal is at logic level "1", the clock signal H is at level "O"; therefore signal A is at level "1" and signals B and C are at level "O".

The signal C being at level "O", the gate G of the amplifier transistor 1 is at level "O" and consequently, the transistor
I is blocked, its drain D is at the supply voltage VDD, and the signal D, coming from the drain D of transistor 1 and shown in line 6, is at logic level "1".

 I1 there is no current I, shown on line 8, in the primary winding of transformer 2.

 The signal B being at level "O", the signal D being at level "1" and the signal E coming from the gate "AND" 10 being equal to B.D, the signal E is at level "O"; it is shown on line 7. Consequently, the protection transistor Il is blocked.

 Still in normal operation, at time tl, the clock signal H goes to level "1"; signal F still being at "1", signal A goes to "O" and signals B and C go to "1".

 The signal C being at level "1", the gate G of transistor i is at level "1" and consequently, the transistor is on; a current of value Io passes through this transistor 1 and the primary winding of the transformer 2.

 Since no anomaly has occurred, the voltage at the drain D of transistor 1 is low (for example, less than 0.5V for an Io current of 20mA), and the signal D is considered to be in the logic state " O ". The signal E, equal to B.D, is still at level "0" and the protection transistor 11 is always blocked.

 In normal operation, the protection transistor 11 is blocked, and the operation of the emitter must be identical to that shown in the brace N in FIG. 2.

 For this, it is necessary that the signal E is at level "0", and it is necessary that, in the case represented at time tl, the validation of the protection circuit by the signal B (signal B at "1") does not does not occur before signal D has reached its normal level "0". This is why, the response time 62 of the inverter 9 from which the signal B is derived must be greater than the sum of the response times 61 of the inverter and 6 of the amplifier transistor 1.

 When an anomaly occurs, such as at time t2. The current I increases and the voltage at the drain D of the transistor 1 also, until it reaches the threshold corresponding to a signal D at logic level "1".

The signal D having passed to level "1", and the signal B already being at level "1", the signal E equal to BD goes to "1", and the gate G 'of the protection transistor It goes to logic level sw1 "
Consequently, the transistor is turned on, its drain D 'goes to ground, and the signal C goes to logic level "0".

 The drain D 'of the transistor being connected to the gate G of the transistor 1, the transistor 1 is blocked, which cancels the current I which had just started.

 The transistor 1 only had to support a current of reduced value for a very short time, which is not likely to deteriorate it.

 If at time t3, the clock signal H goes to logic level "0", signal B goes to level "O" and signal E goes to "O" and the protection transistor is again blocked; the device has returned to the initial state defined by time to.

 The device is ready to operate again, as shown at time t4 in FIG. 4.

 We have seen above that any anomaly observed results in the passage to logic level "1" of the signal E. The alarm circuit 8 records this condition by means of the flip-flop IZ, which is connected to a device 13 capable of report the anomaly and which can be a visual alarm or a supervisory device, the latter being external to the circuit.

 Such a protection device allows conventional integration of the elements used: MOS type transistors, and logic gates achievable by MOS type transistors.

 In addition, the delay of the inverter 9 relative to the inverter 6 and to the transistor 1 is very easily achievable and controllable by playing on the geometry of the integrated transistors.

 Finally, the emitter transistor 1 does not dissipate any more than a very low power, it can also be integrated, and an emitter provided with its protection device can be produced on a monolithic integrated circuit.

Claims (5)

 1. Protection device (5) of a power amplifier (1), characterized in that it comprises a first inverter (6) whose input is connected to the output of the circuit which supplies the signal (A) to amplifier, and the output of which is connected to the input terminal (G) of the amplifier (1), and a protection logic circuit (7) which comprises means for detecting an anomaly which are connected to a part at the output terminal (D) of the amplifier (1) and on the other hand at the input of the first inverter (6), and means for blocking the amplifier connected on the one hand to the output of the previous means and on the other hand to the input terminal (G) of the amplifier (1).  2. Protection device (5) of a power amplifier (1) according to claim 1, characterized in that the power amplifier is a transistor (1) of MOS type, having a response time 6, the gate (G), constituting the input terminal, is connected to the output of the first inverter having a response time 61, whose source (S) is connected to ground, and whose drain (D), constituting the terminal output, is connected via a load resistor to the supply voltage source (VDD), in that the anomaly detection means comprise a second inverter (9), having a response time 62 greater than 6 + 61, the input of which is connected to the input of the first inverter (6), and a logic "AND" gate (10) of which one of the inputs is connected to the output of the second inverter (9), other input is connected to the drain (D) of the amplifier transistor (1), and in that the blocking means comprise a MOS type transistor (11) whose gate (G ') is connected to the output of the "AND" gate of the anomaly detection means, the source (S ') of which is connected to ground, and the drain (D') of which is connected to the gate (G) - of the amplifier transistor (1 ).  3. Protection device according to claim 2, characterized in that it comprises an alarm circuit (8) constituted by a flip-flop (12) for alarm storage, the input of which is connected to the output of the logic gate. "AND" (10) means for detecting anomalies, and the output of which is connected to the triggering input of an alarm system (13) of a supervisory member.  4. Transmitter comprising a power amplifier, characterized in that it includes a protection device according to any one of claims 1 to 3.  5. Transmitter, characterized in that it comprises a power amplifier constituted by a MOS-type transistor (1) integrated on a monolithic integrated circuit, and in that it comprises a protection device according to any one of claims 2 and 3, which is integrated on the same substrate.