FR2480473A1 - Speed control system for magnetic tape signal correction - uses frequency reference recorded on tape to correct speed Variations in tape drive motor - Google Patents

Abstract

A reference frequency recorded on magnetic tape is applied to a read circuit and then corrected for amplitude. This signal is digitised and applied via a blocking register to a memory from which the data is extracted and managed by an addressing and control circuit. The addressing and control circuit receives an input from the read head via a phase locked loop to provide an output for the capstan motor speed control circuit. In this circuit a counter and D/A converter provide the input for a voltage to frequency converter which controls the water speed. The sampling rate is pre-programmed to a frequency which corresponds to the mean value of sample pulses.

Description

The present invention relates to the restitution of data from recorded signals, on a moving medium, in particular on a magnetic type medium.

We know that one of the main conditions for a good use of a magnetic recording obtained by displacement of a support compared to a writing head is that the reading speed of the support is, in each place of it , strictly equal to that which existed at the time of the registration of the said place or by differing from a known quantity
If the recording speed fluctuates, it is imperative, under pain of revealing when reading frequency distortions, that the speed fluctuations are reproduced during reading.

@Or, variations in the speed of the medium compared to the recording organ are frequent in magnetic bard recorders. Some of these variations are @@@ im @ sees by careful realization of the mechanical elements of such recorders. But other variations are unpredictable, especially those caused by the environment in which the recording is made. Thus, on-board recorders, for example, on vehicles, planes or other vehicles are subjected to vibrations of high frequency which are communicated to the recording equipment and to the tape itself, causing variations in speed. very fast instantaneous ones which affect the quality of the recording. The distortions of the signals recorded on a magnetic suppori which result from the variation of relative speed of the tape and of the recording head (s) cause on playback the phenomenon of "weeping""in the case of low frequency distortions such as those caused by slight defects in the uniformity of rotation of the capstan driving the strip and the phenomenon known as" fluctuations "in the case of distortions of relatively high frequency like those which can result from the vibration of the band itself or of the other movable members responsible for guiding this band along the recording head strement or reading
When a high fidelity of reproduction frequency of the recorded signals is necessary, provision has been made not only for recording and playback apparatuses with minimal wobbling and fluctuation characteristics, but also for recording , simultaneously with the generally analog significant signals of which it is desired to obtain a faithful reproduction later, a reference signal such as a clock signal having a perfectly stable frequency. This then makes it possible to carry out certain compensations when reading the recording to improve the restitution of significant signals.

 It is notably known to determine on reading the frequency of the reference signal recorded and to control the capstan for driving the strip of the reading device at this frequency. Thus, the reading speed of the magnetic tape is varied so as to follow as closely as possible the speed vsntions to which said tape has been assigned i. 'recording under the influence of disruptive influences. In this way, with elaborate servo chairs, we try to compensate for the effects of wow and fluctuations in the reproduction of the signal so as to obtain a faithful restitution of the frequencies.

 However, in particular due to the inertia of the capstan, this compensation cannot be perfect and becomes more and more bad as the frequency of the fluctuations to be compensated increases.

 In this way, even with high performance playback devices, it is difficult to faithfully reproduce recorded signals in a particularly disturbed environment by vibrations of removed frequency such as, for example, those that can be encountered at aboard jet planes.

In addition, even if an acceptable quality of playback can sometimes be achieved when the tape is read at the speed at which it was recorded, defects due to recording irregularities become unacceptable when the tape is played back during playback. tape at a speed much greater than its recording speed.

However, it is often advantageous to use relatively high reading speeds to quickly strip the information recorded on a tape running at a relatively low speed. This is the case, for example, of recordings made for surveillance purposes, for example, when trying to collect the maximum amount of information on a given tape length using the lowest possible frame rate. carried by the band before, during reading, be stripped in the minimum of time.

 It is therefore very desirable to be able to obtain a faithful reproduction of the main characteristics of the frequency spectrum of a recorded signal even when the tape is scrolled at a much higher speed than when recorded. An increase in the speed of reproduction, however, leads to an increase in frequency of the undesirable variations and their compensation by variation of the reading speed becomes quite problematic. Thus far, we have been inconveniently limited in the reading speed of recorded magnetic tapes.

 The present invention, on the contrary, allows faithful reproduction in frequency of signals recorded on a support by relative displacement of this support and of a recording means, even if the recording has suffered from disturbances causing vibrations or the like.

To this end, the subject of the invention is a method of restoring a signal, in particular an analog signal recorded simultaneously with a frequency reference on a support animated by a relative movement with respect to a recording or recording member in which a simultaneous reading of the signal and this frequency reference is carried out, by relative scrolling of the support with respect to a reading means, to produce respectively a reading signal and a reading reference, characterized in that one samples the read signal in correspondence with pulses representative of the read reference and the sampled signal is transformed to correct the variations in frequency of the read signal caused by disturbances in the recording speed of the medium.

 The subject of the invention is also an apparatus for restoring a signal, in particular an analog signal, recorded simultaneously with a frequency reference, on a support animated by a movement relative to a writing member, comprising means for produce a read signal and a read reference, by scrolling of said support, characterized in that it. includes means for sampling the read signal in correspondence with pulses representative of the read reference. and means for transforming the sampled signal to correct the variations in frequency of the read signal caused by disturbances in the recording speed of the medium.

 A faithful signal can be reconstituted from samples corresponding to determined points of the reading reference which, themselves, correspond to determined values of the recording frequency reference and consequently of the analog signal recorded simultaneously. with it. It is indeed possible to use this correspondence relationship between the samples of the signal read from the recording and the corresponding values of the original analog signal to correct the frequency distortions resulting from the recording and playback operations and obtain a faithful frequency reproduction of the signal originally recorded.

According to a preferred embodiment of the invention, to carry out the transformation of the sampled signal, samples of the read signal are sequentially stored in memory in the order in which they are produced by the sampling and these samples are extracted. the memory, in the order in which they are entered, at a pre-programmed frequency corresponding substantially to the average value of the frequency of the sampling impulses.

 Thus, if samples are used which correspond to instants determined by a particular respective characteristic of the reading reference, for example the instants of zero crossing of the rising edges of this reference, the samples obtained correspond to values of the analog signal d separated by equal time intervals. By restoring these values to the output of the memory, at equal time intervals, it is thus possible to carry out the correction in time of the read signal itself, without it being essential to subject the magnetic tape during the reproduction process to fluctuations which fully reproduce those which it underwent at the time of registration.

On the contrary, the invention also makes it possible to overcome, at the level of the restitution of the signal, the fluctuations generated by the reading process itself.

Such fluctuations can in particular arise at relatively high frequencies when the read operation is carried out at high speeds.

In accordance with an advantageous embodiment, the sampling pulses of the read signal are produced at a frequency @ multiple of that of the read reference and in phase with this range. However, this gives a sampling rate el @@ é and good fidelity of the secopy of the ana @@ gic signal in a series of samples.

 Preferably, the sampling is carried out at a frequency @@ imale on au @@ i as high as possible, taking into account the characteristics @ of @ tronic used, whatever the reading vi @@ @@ the recording. the density or t @@ @ @ @ @ nt @ llo @@ ag of the reading signal is then as high a pulse as the @@ tesaa of movement of the reading apparatus @@@ less.

The emp @@@ ence to m @@ tré that one could, with a rate
to sample from a few hundred kHz, @@ teni @@@@ @@ extremely faithful productions of analegic signals @@@ recorded, even with higher read speeds @ ieu @ s times @ higher at the recording speed, for example ten to twenty times.

According to a characteristic of the invention, it is further provided to vary the reading speed of the medium as a function of the rate of completion of the memory. We make sure
as well as this retains an average degree of filling which makes it possible to take into account variations of great dynamics of the rate of entry of the samples in this memory, the rate of exit remaining constant. It thus succeeds in correcting fluctuations in the high frequency of the read signal, while the variations in read speed at low frequencies are compensated by the servo-control of the memory filling rate.

Preferably, the samples are digital samples produced by analog / digital conversion of the read signal. A digital to analog converter
is planned at the exit of the moire for the restitution of a
analog signal corresponding to the recorded signal.

The memory used can advantageously be an addressable RAM, the process of entering and
information output being controlled by logic in
which a prionity is assigned to the extraction orders
memory information.

In the description which follows, given by way of example,
reference is made to the accompanying drawings in which
Figure 1 is a block diagram of a dgan circuit of an apparatus according to the invention
Figure 2 is a block diagram of an element of
Figure 1;
Figure V is a block diagram of another element of Figure 11
FIG. Z is a diagram of the signals used in the circuit of FIG.

 There is shown, very diagrammatically in FIG. 1, a magnetic recording reader provided with a read head 13 whose output signals are applied to an input 16 l @ d @ of a read circuit 15. A magnetic tape - that 1.7 scrolls in front of the head 13 between two bottles 19 and 21, respectively debtor and receiver, under the action of a capstan d1entr'ment schematically represented at 23.

The capstan 23 is driven with slaving, in a known manner, by a motor 25, by means of a connection shown diagrammatically by the dashed line 27 at a speed which varies as a function of the voltage d power to said motor which is applied to it by its input 37.

Said voltage is dependent on a phase lock loop (BV) circuit 29 which receives on one of its inputs 31 a reference frequency signal Fref and on another input 33 a frequency signal from a tachometer 2 @ goes directly by the capstan shaft 23 and produces a train of pulses whose frequency is directly representative of the effective speed of rotation of the capstan. It is the output 35 of the loop 29 which controls the voltage supply of the motor to its input 37.

 The magnetic strip 17 carries a plurality of tracks, thirteen for example, suitable for collecting data which, in the present example, consist of analog signals which, on reading, seek to analyze the frequency spectrum with precision within a range up to several kilohertz. The magnetic strip 17 also includes a track for recording a reference signal, constituted by a clock signal, simultaneously with that of uxtue data signals. The other tracks of the magnetic strip are affected.

 If the recording of the tape was performed in a disturbed environment such as, for example, on board a vehicle, the resulting variations in tape speed with respect to the recording head similarly affect the recording of the clock signal. By registering this reference, the distortions caused by these variations can be corrected when the recorded signals are restored.

it is often advantageous to reproduce the recording of the tape 17 at speeds which can be significantly higher than the recording speed of the tape. Thus, for a recording speed of the tape of 5.1 centimeters per second, which makes it possible to record under good conditions the analog signals which one seeks to analyze later, it is possible to perform the reading at speeds adjustable by means mentioned below and up to sixteen times the original recording speed.

 The frequency spectrum of the read signal to be analyzed then extends to several tens of kilohertz.

 When recording, the clock frequency can typically be 13.5 kHz. If the tape is read at a speed sixteen times greater than the recording speed, the signal corresponding to the clock recording present at the output of the reading circuits 15, or reading reference, will have a frequency of approximately 216 kHz.

 A typical cry may be constituted by slow variations of the frequency of the reading reference of approximately 2% around the frequency of this clock, or of the multiple thereof corresponding to the multiplication of the reading speed. Variations, for example around 5% and up to 10% and even 20%, of the clock frequency or its multiple, due to fluc tuat, are superimposed on it. relatively high.

 The reading circuit 15 delivers on its output 41 the reading reference resulting from the reading of the recorded clock signal. On its other outputs 43a, 43b, 43c, etc., the reading circuit delivers the reading signals corresponding to the analog signals recorded on the tracks of the magnetic tape 17 assigned to the recording of the data. In what follows, we will only consider the output 43a assigned to the recording track a.

 The output 41 applies the read reference through a level detector 42 to an input 43 of a phase lock loop (BV) 45 suitable for transmitting on its output 47 a train of pulses whose frequency is a multiple of the frequency of the reading reference and which is in strict phase coincidence with this reference. In an exemplary embodiment, the frequency of this pulse train is 216 hKz, which corresponds to a multiplication by sixteen of the frequency of the recorded clock signal.

 The output 47 of the loop 45 controls a conversion control input 49 of an analog-digital converter 50, the other input 51 of which receives samples of the read signal present at the output of a blocking sampler 74 which receives the signal of reading from the output 43a of the reading circuit 15 via a level restoration circuit 73. This signal is sampled at the frequency of the blocking pulses it receives on its input 75 from an output 78 of the A / D converter 50 at the start of each conversion cycle, and this until the end of the period. conversion rate, that is, in the considered example 2.8 microseconds.

Each digital sample at the output of the converter 50 is intended to be recorded in an addressable random access memory 54. The samples reach this addressable random access memory 54. The samples reach this memory via a blocking register 64 and are there sequentially entered in the order of their appearance at the output of the analog-digital converter 50. they are read and extracted from memory 54 under the control of a crystal oscillator 56 producing at its output 57 a rigorously stable frequency whose value is equal to the average value of the frequency of the pulse train present at the output of the phase lock loop 45, i.e. in the example used 216 kilohertz. Address logic and priority control 8 @ manages l writing and reading the samples contained in the memory 54.

 At the output of memory 54, the stored samples are converted again into an analog signal by a digital / unalogical converter 59, to which they are transmitted through a blocking register 77, and which delivers on its output 61 a faithful reproduction, as for its frequency spectrum, of the signal originally recorded on track a of the magnetic tape. A liaizon 46 connects the level detector 42 to an en @@ ée 44 of the D / A converter 59 intended to @abiber the @@@@@ function thereof in the absence of a reading reference on the @ @tie 41 of circuit 15.

The samples extracted from memory 54 at a regular rate @@ correspond to sampling instants determined by the transition to zéxo a @ cendant of the rectangular signal i @ su of the phase lock plug 45. This signal was strictly phase with the reading reference (out @ 41). the sampling instants therefore correspond to regularly spaced values @ in time of the signal @@ clock recorded at the same time as the analog signal to be used. The extracted samples are therefore perfectly in phase with these values and provide a faithful reproduction of the frequency spectrum of the original analog signal.

 The phase vexronillage rod 45 is shown diagrammatically in FIG. 2. The output 47 of the loop 45 is at the output of a voltage-controlled oscillator (VCO) 103 by an input 105. This o @ cillatour delivers a rectangular signal of frequency fo at an input 107 of a frequency divider 109 comprising a plurality of inputs 111 for programming a division factor N to provide at its output 113 a signal whose frequency is equal to fO / N.

 The frequency fO / N is transmitted to an input 115 of a phase comparator 117, the other input of which is constituted by the input 43 of the phase loop 45. This comparator compares the phases of the signal fO / N and of the reading reference present a at the output 41 of the reading circuit 15, to produce on its output 121 a corresponding voltage signal intended to control the frequency of the oscillator 103, by the input 105 of the latter through a amplifier 123 and a filter 106. This filter essentially comprises a parallel connection of a capacitor C125 and a field effect transistor 127, connection at one end of which is connected in series one end of an adjustable resistor R129, l the other end of the parallel circuit being connected to ground. The other end of the resistor R129 is connected to the input 105 of the oscillator 103. The filter 106 makes it possible to attenuate the surface ripples of the output voltage of the comparator. 117. in order to provide the input of the oscillator 103 with a fairly stable control voltage while allowing extremely tight operation of the loop 45 capable of closely monitoring any phase variation at the acimis signal on the input 43, corresponding to fluctuations during the recording and the reproduction of the signal.

The divider N can be adjusted as shown diagrammatically at 131 as a function of the reading speed VL of the strip 17 from a display circuit 133 of the latter. It is possible to adjust this divider so that the frequency O always remains as high as possible, that is to say in the example N chosen 216 Ez, whatever the reading speed. in - I, the rating device capable of obtaining satisfactory restitution performance for a maximum reading speed corresponding to sixteen times the recording speed, its performance will be even better for a lower reproduction speed. Indeed, maintaining the output frequency f O of the phase loop 45 in the latter case results in a greater sampling density of the read signal 43a by the blocking sample-cell 74 and the analog / converter. digital 50.

 The circuit 133 for displaying the speed V also controls the field effect transistor 127 in order to vary the characteristics of the filter at the input 105 of the VCO oscillator 103 as a function of this reading speed.

The analog / digital converter 50 (FIG. 1) is controlled by the rising edge (passa, ge to zero) of each output pulse of the phase lock loop 45 to trigger each conversion cycle, It includes a multibit output 62, for example eight bits, connected to 3 the input 63 of the blocking register 64 which has a validation input 65 connected to an output 205 of the logic 80. The multibit output 66 of the blocking register is connected to the input 67 of memory 54. This is a random access memory (RAM) having, in the example described, a capacity of approximately sixteen kilometers commanded by a fourteen-bit addressing input designated by the reference 68 and connected to the output d address 209 of the logic 80. The output 55 of the memory 54 is connected to the input 69 of the digital analog converter 59 through a blocking register 77 which has an input 70 connected to an output 213 of the logic 80 to allow, for each digital sample sent to dan s a position of the memory, transfer out of it at the rate set by the oscillator 56.

 The logic 80 receives on one of its inputs, 201, the signals coming from the phase lock loop 45 and on another input, 203, the signals coming from the crystal oscillator 56. Its output 207 is connected to a input 71 of memory 54 intended to temporarily validate the data bus of the latter for writing samples to be stored.

Another output 211 is connected to an input 72 of the memory 54 validating the memory bus for reading the signals to be extracted.

A pulse from the phase lock loop 45 is applied to the input of a delay circuit 202 forming part of the logic 80 and which imposes on it a delay corresponding to the duration of the conversion cycle of the analog to digital converter 50 , or 2.8 microseconds in this example. The pulse thus delayed excites a monostable 250 whose output is connected, on the one hand to the control input 65 of the blocker 64 through the output 205, to control the admission into the blocker 64 of the information present at the output of the analog / digital converter 50 at the end of a conversion cycle. The monostable 250 is also connected to the input of a blocking register 265 having a reset reset input 266 and a connected output to an input 267 of an AND gate 260, the other input 268 of which is inverting and designed to receive an inhibition signal INH. The output 269 of the AND gate 260 is connected, to the input of RESET 266, as well as to a monostable 270 whose output is connected to the output 207 of the logic, also directly to an output 206 and finally, to the entry 271 of a registration register 272 with fourteen bits. The content of the registration register 272 is incremented by each pulse received on its input 271 to deliver on its multibit output 273 an address signal to an input 215 of an Mx multiplexer 217 whose output forms the output 209 of the logic 80 to address input 68 of memory 54.

The output of the crystal oscillator 56 connected to the input 203 of the logic 80 is connected to a delay circuit 235 whose output excites a monostable 236 connected to an input 237 of an OR gate 240, also at the input of a monostable 220 whose output 245 is connected to the other input 243 of the OR gate 240, finally to the input of a delay circuit 251 exciting at its output a monostable 230 whose output forms the output 213 of logic 80.

The output of gate 240 is connected to the inverting input 268 of gate ET 260.

 The output 245 of the monostable 220 is also connected to an input 253 for incrementing the content of a read register 255, the multibit output 257 of which is connected to a second input 218 of the multiplexer 217. This Mx multiplexer 217 is intended for alternately switching the signals present on its input 215 and on its input 218 towards the output 209 under the control of an input 219 also connected to the output 245 of the monostable 220. Finally, the output of the monostable 220 is directly connected to the output 211 of the logic 80.

(The duration of excitation of this monostable 220 is, in this example, of a microsecond).

The operation is as follows
A pulse from the phase loop 45 admitted on the input 201 (FIG. 3) - is first of all delayed by the circuit 202 to cause the excitation of the monostable 250 at the end of the conversion period of the analogi converter - / digital 50. In FIG. 4D, the blocking signal of the blocking sampler 74 from the A / D converter 50 is shown, which begins with the pulse coming from the phase locking loop 45 and is ends at the end of conversion, at the same time as the monostable 250 is energized (pulses E1 and E2 in FIG. 4E). In its excited state, the monostable 250 produces a pulse for registration request (FIG. 4E) on output 205 which validates the opening of the blocking register 64 (FIG. 1) to enable it to receive the digital sample present at the end of the analog / digital converter 50 and which is transmitted to the input of the blocking register 265.

 If the registration request pulse is similar to the pulse E2 of FIG. 4E, that is to say occurs in the absence of an inhibition signal IN @ on the gate ET 260, the blocker register 265, as soon as it has tilted, produces an impulse $ figure 4F) on the output 269 of the gate ET 260, which allows to perform, at the same time as the reset of the regis @@@ 265, l 'in @ rementation of the @ogister of registration 272 and @@ @ise en route of the monostable 270. This last validates the bus @@ in mem @ ire 54 for the inscription (figure 4G) by the area 71.

The registration register 272 (FIG. 3) is incremented by the impulse present on input 271 indicating the memory address into which a digital sample present in the register 64 is to be transferred. When the multiplexer 217 connects its multi-bit input 215 to the output 209, the memory position 54 at the corresponding address is effectively requested and the writing of the sample blocked in the register 64 is carried out there under the control '' a brief validation impaisance produced by the monostable 270 and
transferred to entry 271 of the memory (FIG. 4G).

 When a pulse from the crystal oscillator 56 is present at the input 203, it causes the excitation of the monostable 220 and the increment of the reading register 255 to determine the address of the memory position 54 which must be read for the extraction of a sample to register 77. At the same time, the pulse produced by the monostable 220, or reading pulse, (fig. 4A) acts on the control input 219 of the multiplexer 217 so to switch the latter so that the input 218 is now connected to the output 209 to interrogate the new address in the memory 54. The duration of the pulse is sufficient to cover the whole process of reading from the memory at the address indicated (one microsecond in the example chosen). At the end of this pulse, the multiplexer 217 returns to its initial state and connects the address input 215 2 to the output 209. During the duration of this pulse, a pulse of data bus validation is transmitted (output 213) to the input 72 of the memory 54 to control the transport of the sample recorded therein. This sample is admitted to register 77 lfig. I) during the opening time thereof by an unblocking pulse (fig. 4B) produced at output 213 and which begins after the start of the reading pulse (fig.4A) and ends before the end of this by the combined play of the monostable 230 and the delay circuit 251.

 Priority logic is provided to resolve cases of conflict caused by the simultaneous or almost simultaneous reception of an impulse at the entry of the registration register and at the entry of the reading register. It is imperative that, from this situation; the read impulse benefits from the priority so as to read the sample stored in the memory at a strictly stable frequency. 5 On the other hand, there is no disadvantage in delaying the writing of a sample present at the output of the analog / digital converter 50. To this end, an inhibition signal of the writing INH is produced in response to each pulse from the crystal oscillator 56.

the write ban must extend, not only from the moment of reception of a clock or crystal pulse 56, but also during a time preceding this pulse equal to the time necessary to realize - register.

 Referring to FIG. 4C, an inhibition pulse INH has been represented, which begins approximately one microsecond before the start of the reading pulse of FIG. 4A, and ends approximately one microsecond after this, (in the assumption that it is desired to leave a time of one microsecond for each operation of reading or writing data into memory).

To produce a pulse of FIG. 4C, the monostable 236 is excited in response to the previous pulse of the oscillator 56 with a delay Q which corresponds to the time elapsed between the rising edge of the previous read pulse (fig. 3A) and the start of the desired inhibition time. The output pulse from the monostable 236 is applied to the OR gate 240 at the output of which there is therefore present a logic level 1 having the effect of prohibiting the operation of the AND gate 260 in the description circuit. Before the monostable 236 goes out, the read signal from the monostable 220 (fig. 3A) maintains the inhibition signal at the output of the OR gate 240 and the correlative prohibition of operation of the AND gate 260, until S the impact of the monostable 220.

 If a registration request, constituted by the pulse El of FIG. 4E (output from the monostable 250), reaches the blocking register 265 while the inhibition signal INH is present on the gate ET 260 (as shown on the FIG. 4C), the blocking register 265 switches and the signal present on the output (FIG. 4F) cannot pass through the AND gate 260, neither excite the registration validation monostable 270, nor advance the registration register 272.

 No risk of loss of data to be entered is to be feared insofar as these remain stored in the blocking register 64 while waiting for the conflict with the read pulse to be resolved. Indeed, in the hypothesis envisaged for the pulse El of FIG. 4E, as soon as the signal INH ceases (fig. 40), the gate ET 260 becomes conductive (fig. 4F), which causes the incrementation process of the registration register 272, of excitation of the monostable 270 and of resetting of the blocking register 265, as illustrated in FIGS. 4F and 4G.

 For the correct functioning of the inhibition signal INH must leave between two successive inhibition slots a time interval sufficient to be able to carry out two successive registrations if the rate of variation of the frequency of the phase loop requires it. Thus, in the example used, the interval between two read pulses being 4.3 microseconds (at the frequency of 216 HZ) and the inhibition slot corresponding to 2 microseconds, there is still enough time to make two registrations each requiring 1 microsecond.

 The invention provides for controlling the reading speed so that the filling level of the memory 54 is maintained in the vicinity of half of its capacity while allowing rapid variations in the number of samples contained in this memory, in addition or less compared to this average value, in order to absorb brief fluctuations, but of high absolute value more or less in the instantaneous frequency of arrival of the samples.

 To this end, the output 206 of the logic 80 (FIG. 1) is also connected to the counting input C81 of an up-down counter 82 of which the other input D83 is connected to the output 211 of the logic 80. The eight most significant stages of the up-down counter 82 are connected by a multi-bit link 84 to the inputs of an eight-bit digital-analog converter 85 whose output 86 is connected to a low-pass filter 87. The voltage at the output of the converter 85 varies more or less depending on the filling level of the counter 82. The latter is fed in the increasing direction by pulses corresponding to inscriptions of digital samples in the memory 54 while its content is decremented by the pulses corresponding to extractions of samples out of this memory.

The filter 87 supplies an input 90 of an amplifier 88, itself connected to a voltage-frequency converter 89. The output 91 of the voltage-frequency converter 89 is, during normal operation, connected through an electronic switch 92, at the input 31 of the phase loop 29 which controls the reading speed of the magnetic recording using a reference frequency Fref present on the output 91. This frequency is proportional to the voltage applied to the converter 89 , which is directly representative of the filling level of the counter 82 and, consequently, of the memory 54. The gain of the amplifier 88 is adjusted so that the voltage present at the input of the converter 89 corresponds to the frequency nominal Capstan control fref 23 for the reading speed chosen when the account level present on the link 84 at the output of the counter 82 indicates that. memory 54 is filled to half its capacity.

 The filter 87 includes a system for compensating for the late phase inherent in the filtering. this filter is provided to eliminate the high frequency fluctuations of this test and provide a relatively stable control signal to the drive system of the capstan motor, the possible slow fluctuations of which are compatible with the response speed of the capstan to @ variations phase.

 When the apparatus is started up, it is necessary to allow time for the content of the memory 54 to reach half of its capacity before bringing into play the regulation means which has just been defined. To this end, an electronic switch 93 is interposed on the link between the output 211 of the logic 80 and the down counting input D83. The switch 93 is controlled by a differential amplifier 94 which receives on one of its inputs 95 the analog signal present at the output of the filter 87 and compares it to @@ voltage reference signal V (1/2 cap) present in par @@ ence on the other input 96 of the amplifier 94. The level of the time V (1/2 cap @ represents the value of the output voltage of the filter 87 which corresponds to a filling of @@ memo @re 54 at half of @a capacity. The output of l @@ mpli @ l @@ teur 94 is connected, on the one hand, to the input of command 100 of switch 93, and on the other hand , at the input d @ command 97 of the electronic switch 92. The latter is @ e @@ è a crystal oscillator 98 which is capable of supplying @ a signal Fref at the input of the phase locking loop 29, to control the reading speed at the start of operation.

 At start-up, the switch 92 connects the output 99 of this oscillator directly to the loop 29, while the voltage-frequency convertor 39 is isolated from the latter. The bidirectional counter 82 receives only counting pulses. When the output voltage of the filter 37, which represents the level of count in the counter 82, reaches a level higher than the voltage V (1/2 cap), a signal appears at the output of the amplifier 94; the switch 92 switches under the command applied to its input 97, thus disconnecting the oscillator 98 from the loop 29 and Y connecting the voltage-frequency converter 89. At the same time, the switch 93, which was open so as to let act the only pulses coming from the output 206 to increment the counter 82, closes under the control of the amplifier 94 to start applying countdown pulses coming from the output 211 of the logic 80. The oscillator 98 and the converter 89 have their nominal output frequency adjusted as a function of the reading speed VL displayed.

A device such as that which has just been described makes it possible to eliminate the high frequency fluctuations affecting the recording of signals when this recording takes place under highly disturbed conditions and which it was impossible to correct correctly before. This is the case, in particular, when the signals are frequency fluctuations of very large amplitude and / or very fast, for example when the recorder is subjected to shocks.

 The device which live from being described also makes it possible to obtain a faithful reproduction in frequency of a signal whose replay speed can be much higher than its recording speed, which was difficult to achieve before. 1 results therefrom that it is possible to obtain a much quicker processing of the tapes recorded under difficult conditions.

The apparatus which has just been described makes it possible to eliminate not only the frequency faults which arise when the signals are recorded, but also the distortions which could occur during reading, in particular at great speed.

One can advantageously keep a certain compensation for the low frequency fluctuations (wow) by a servo-control of the capstan, as it has been described, which makes it possible to keep a reasonable memory capacity.

 The device --- also allows the faithful reproduction of the spectra of signals recorded not only under eyebrow conditions, but with devices whose inherent characteristics of immunity to wailing and to relatively poor fluctuations. Thus, one frees oneself from the obligation to use extremely sophisticated and often heavy recording apparatuses for the recording in difficult conditions where the weight is often a significant handicap, as is the case for the on-board devices.

The restitution apparatus according to the invention makes it possible to correct the defects which may result from the use of relatively poorly developed recording media, by providing very good fidelity of restitution,
Such a device can be used in a reading station and assigned to the high-speed processing of a very large number of recordings from different sources, that is to say from various recorders. this assignment justifies the use of advanced equipment at the breeding station. centralized.

Claims (17)

REVESICATI ONS 1. Method for restoring a signal, in particular analog signal, recorded simultaneously at a frequency reference on a support animated by a relative movement with respect to a recording or recording device in which a simultaneous reading of the signal is carried out and of this frequency reference, by scrolling of the support with respect to a reading means, to produce respectively a reading signal and a reading reference, characterized in that the reading signal is sampled in correspondence of pulses representative of the read reference and the sampled signal is transformed to correct the variations in frequency of the read signal caused by disturbances in the recording speed of the medium. 2. Method according to claim 1, characterized in that to carry out said transformation, samples of said read signal are sequentially stored in memory in the order in which they are produced by sampling and these samples are extracted from memory, in the order in which they entered it, at a preprogrammed frequency corresponding substantially to the average value of the frequency of the sampling pulses.  3, Method according to claim 1 or 2, characterized in that one carries out the reading of the support at a scrolling speed several times greater than the speed of recording the signal and the frequency reference on the support. 4. Apparatus for restoring a signal, in particular analog signal, recorded simultaneously with a frequency reference on a support (17) movable relative to a recording or recording device, comprising means for producing a read signal and a reading reference in response to the simultaneous reading, respectively of the signal and of the reference recorded, by relative scrolling of said support (17) and of a reading means (13) characterized in that it comprises sampling means (74) of the read signal in response to pulses representative of the read reference and means (54, 80) of transformation of the sampled signal to correct the variations in frequency of the read signal caused by disturbances in the speed of support recording (17). 5. Apparatus according to claim 4, characterized in that the transformation means comprise a memory (54) for sequentially recording samples of the read signal in 7 "order in which they are produced by said sampling means (74) and means (70) for extracting said samples from said memory in their order of entry, at a pre-programmed frequency corresponding substantially to the average value of the frequency of said representative pulses.  6. Apparatus according to claim 4 or 5, characterized in that it comprises multiplier means (47) for producing said sampling pulses in phase with, but at a frequency multiple of that of the reading reference  7. Apparatus according to claim 6, wherein the reading means (13, 23) are adapted to operate at different speeds @ s, @ nra @ terized in c @ that the multiplier means (47) are programmable so that the average value the frequency of the sampling pulses remains substantially the same for different read speeds.  8. Apparatus according to one of claims 6 or 7, characterized in that the @ said multiplier means comprise a phase locking loop (47) comprising a frequency divider (109) connected to the output of this loop, means (117) for comparing the phase of the divider output signal and the read reference, and an oscillator (103) whose frequency is controlled by the output of said phase comparator.  9. Apparatus according to claim 5 and one of claims 6 to 8, characterized in that it comprises, in cut, operating means (82, 88) in response to the degree of filling of the nrè'moire pour ajue- -ter the speed of the relative scrolling of the reading means and the support  10.Apparatus according to one of claims 5 to 9, characterized in that the sampling means (74, 50) comprise: an analog / digital converter (50) for recording in said memory samples in digital form, and in that it comprises a digital / analog converter (59) at the output of said memory (54) to produce an analog signal from said samples. 11. Apparatus according to claim 10, characterized in that the memory (54) is an addressable random access memory. 12. Apparatus according to claim ll in which the memory extraction means comprise means suitable for producing clock pulses at the preprogrammed frequency, characterized in that it further comprises address means <-217 ) of memory locations (54) for writing said samples to memory in response to each of said representative pulses and reading them out of this memory in response to each of said clock pulses. 13. Apparel 1 according to claim 12, characterized in that it comprises means (260, 265) for deferring the wise address of the memory in writing for the benefit of addressing the reading memory when one of said pulses representative conflicts with one of said clock pulses.  14. Apparatus according to claim 13, characterized in that the means (240) for differing comprise means suitable for generating a signal to inhibit the addressing of the memory in registration during the time necessary for reading the memory in response to said clock pulse and during a time interval preceding the reception of a clock pulse corresponding to the duration necessary for a registration operation.  15. Apparatus according to claim 14, characterized in that the time interval separating two successive inhibition signals is sufficient to allow the successive registrations of at least two samples.  16. Apparatus according to one of claims 14 or 15, characterized in that it further comprises means (265) for temporary storage of the sample to be memorized during the duration of the inhibition signal  17. Apparatus according to one of claims 12 to 16, characterized in that it comprises a registration address register (272) and a read address register (255) coupled to the address input memory through a multi plexer (217) controlled in correspondence with the clock signal.