FR2468185B1 - - Google Patents
Info
- Publication number
- FR2468185B1 FR2468185B1 FR8022291A FR8022291A FR2468185B1 FR 2468185 B1 FR2468185 B1 FR 2468185B1 FR 8022291 A FR8022291 A FR 8022291A FR 8022291 A FR8022291 A FR 8022291A FR 2468185 B1 FR2468185 B1 FR 2468185B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8022291A FR2468185A1 (fr) | 1980-10-17 | 1980-10-17 | Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8022291A FR2468185A1 (fr) | 1980-10-17 | 1980-10-17 | Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2468185A1 FR2468185A1 (fr) | 1981-04-30 |
| FR2468185B1 true FR2468185B1 (xx) | 1984-12-14 |
Family
ID=9247046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8022291A Granted FR2468185A1 (fr) | 1980-10-17 | 1980-10-17 | Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2468185A1 (xx) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1218344B (it) * | 1983-03-31 | 1990-04-12 | Ates Componenti Elettron | Processo per l'autoallineamento di un doppio strato di silicio policristallino,in un dispositivo a circuito integrato,mediante un' operazione di ossidazione |
| JPS60134478A (ja) * | 1983-11-28 | 1985-07-17 | ローム・コーポレーション | 電気的プログラム式記憶装置を製造する方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3984822A (en) * | 1974-12-30 | 1976-10-05 | Intel Corporation | Double polycrystalline silicon gate memory device |
| GB1540450A (en) * | 1975-10-29 | 1979-02-14 | Intel Corp | Self-aligning double polycrystalline silicon etching process |
| JPS53108247A (en) * | 1976-12-27 | 1978-09-20 | Texas Instruments Inc | Electrically programmable floating gate semiconductor memory |
| US4151021A (en) * | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
| US4173766A (en) * | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory cell |
| US4173791A (en) * | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory array |
-
1980
- 1980-10-17 FR FR8022291A patent/FR2468185A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2468185A1 (fr) | 1981-04-30 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |