FR2465273A1 - Interactive processor for real time images - uses digitised image signal input to multiprocessor system - Google Patents

Abstract

In a number of activities such as quality control of metals and analysis of radiological images a TV camera obtains a moving image which is processed by computer. The spaced and image quality is increased by a multiprocessor system. The output from a TV camera (1) is applied to a monitor (3) and tape recorder (4) and also to an A/D converter (2). The digitised signal is routed via a megabus (18) to a D/A converter(s) for application to a screen (6) for inspection. The digital signal is also applied to microprocessor units (7-14) controlled by a microprocessor control unit (15) with a mass memory system (16). This ensures control and processing taks are performed and also allows interactive operation via a teletype writer (17).

Description

 The invention relates to computerized capture devices with digitization and image processing, the processing aiming to improve the result of the capture and to extract from it the most commonly used and most directly exploitable information. It relates more particularly to devices using a television camera, associated with an analog-to-digital converter, to carry out the input, using microprocessors and in which it is preferably provided that a human operator has a display results in order to interactively control the execution of the various treatments.

 Such devices allow to provide a relatively high speed of capture allowing in particular the capture of images of moving objects, a high resolution power and a relatively inexpensive and efficient processing of the digitized images.

 The applications of these devices are very numerous and as varied as: cell counting, quality control of metals, analysis of radiological images, control of automatisms. and industrial processes, traffic control, and others.

 The present invention aims to increase the universality of use of these devices and to increase the speed of capture and the quality of the image without significantly increasing costs.

 The device according to the invention is mainly characterized, in combination, by several operating units connected together by a megabus and comprising I an image capture unit comprising a television camera and an analog-to-digital converter agencies for capturing in time real a full video image; a plurality of micro-processing units each comprising a microprocessor, a memory, first and second logic circuits controlled by the corresponding microprocessor and respectively authorizing access to the memory, to said microprocessor and to the megabus, said memory being able to store the information corresponding to a predetermined number of lines of the video image and means for deciding whether said micro-unit is concerned or not by an operation in progress; and a control unit, comprising a microprocessor, a mass memory, a generator of interrupt signals connected to the other units and means for sending specific control words to said other units.

 As will be explained below, this original architecture of the device, which makes it a hierarchically controlled computer system, with common memory dispersed in banks connectable to the master processor (belonging to the control unit) and to a determined slave processor arbitrary (belonging to one of the micro-processing units), the master processor being specialized while the slave processors are trivialized and each process a determined part of the video image, makes it possible to speed up processing, conflicts of access to the megabus therefore the use of a complex synchronization mechanism, being avoided.

Other particularities, as well as the advantages of the invention will become clear in the light of the description below.

In the accompanying drawing:
Figure 1 is a general block diagram of a device according to a preferred embodiment of the invention;
Figure 2 shows schematically the input unit that includes such a device;
FIG. 3 represents a micro-processing unit and,
Figure 4 shows the control unit.

In Figure 1, a machine is shown composed of the following four logical units:
- An input unit, composed of a television camera 1, a set of circuits comprising an analog digital converter and symbolized by a rectangle 2, a television monitor 3 and a video recorder 4 and intended digitizing the television signal and storing the scanned image in memory.

- A display unit, used for the interactive development of the treatments and composed of a set of circuits comprising a digital-analog converter and symbolized by a rectangle 5, and intended to convert the digitized and processed image into a signal television applied to a control screen 6,
- A processing unit, composed of eight micro-units (7 to 14), each of which comprises, as will be explained in detail below
- A memory having a part called image memory, containing sixty four consecutive lines of the image and a part called "processing memory" containing the code necessary for the processing of work areas.

- A processing microprocessor,
- A system of doors, which will be described below and makes it possible to isolate each micro-unit from the rest of the machine and to recognize from the information circulating on the megabus, that which is intended for this micro-unit.

- A control unit (microprocessor 15 - mass memory 16) which ensures, on the one hand the control and scheduling of the tasks entrusted to the three other units and allows, on the other hand, via a teletype 17, the interactive dialogue with
the user.

A megabus 18 interconnects these different units. It includes, in addition to power supply lines
- an interruption line
- a "Reset" line used to start the machine
- thirty two bidirectional lines of data,
- eighteen address lines
- six control lines for access to microphone memory
processing units, namely
A line of reading and writing, a line of beginning
memory cycle, and four lines (OCTO - OCT3) indicating,
as will be explained below, on which byte (s) of the
word addressed the read or write operation must be ef
carried out.

In Figure 2, the unit is shown in more detail
input. The video signal supplied by the camera (cable 101) is
applied to converter 200 through an adaptation circuit
102 arranged to supply a signal to a control circuit 103
even start of frame (wire 1020), a start of frame signal
odd (wire 1021) and a line start signal (wire 1022).

The circuit 103 is arranged to receive, from the processor
15, a control word (link 151) which indicates the type of sai
to perform and an interrupt signal (link 251). The
circuit 103 compares the most significant bits of the addresses circulating
in the mejabus with a name assigned to the input unit and, in the event of coincidence, at the time of an interrupt signal, it triggers the following operations: :( in the described execution mode, we have assuming that the captured image contains 512 points of 512 lines and that each point is digitized on eight bits)
a - waiting for the even frame start signal
b - for each line of the video signal and for five hundred and twelve measurement points per line, sending to the converter 200 (link 2000) an order for sampling the video signal and converting it into an integer digital value expressed by eight bits for each points.

c - all the four points of the video image, emission, on the megabus, according to the process which will be described later, of the four bytes of corresponding data on (A0. ..A31), of eighteen address bits ( on Bo - B17) and appropriate signals on the six control lines (via 183).

d - after acquisition of two hundred and fifty six lines of the even frame, waiting for the odd frame start signal and execution of the operations b - c
e - after acquisition of two hundred and fifty six lines of the odd frame, -stop of the capture and transmission, on the wire 1030, of an end of capture signal directly transmitted to the microprocessor 15 (FIGS. 2 and 4).

 The generation of address bits Bo and B17 is carried out by a binary counter 104 and by a line connection and power amplification circuit 105.

 The counter 104 receives a reset signal (line 1040) from the circuit 103 at the time of the interruption and, by the same line, clock pulses which it counts until its maximum capacity of 512 x 512 and each of which therefore corresponds to a point. At each point, the order to store a byte from converter 2 is sent, by a link 2010, to a circuit 201 which is intended to cite lines Ao to A31 and, for each word (four bytes), a signal of end of word is transmitted by the counter (link 1041) to the control circuit 103, which then gives circuit 201 the order to load the megabus (link 2011).

At the end of each line, the counter 104 sends to circuit 103 an end of line signal (link 1042) and, at the end of each frame, it sends an end of frame signal (link 1043).

 Let CO to C17 be the eighteen bits of the count of counter 104. We can consider that the two least significant bits CO - C1 express the number between 0 and 31, of the measurement point in a word; the next seven bits C2 to C8 express the number, between 0 and 127, of the word in a line of the image; the next five bits, Cg to C13, express the numbers, between 0 and 31, of the line in an eighth of a frame; the next three bits, C14 to C16, express the number, between 0 and 7, of the eighth frame in the frame and the last bit C17 expresses the number, equal to O or 1, of the frame in the image .

 At the end of each word, the circuit 105, as a function of the information received from the counter (link 1050), sends an address on the lines Bo ... B17. The lines Bo to B6 are respectively excited by the information corresponding to C2 - C8, that is to say indicate what is the word of the line; 37 is excited by C17, ie indicates which frame it is; B8 to B12 are excited by Cg - C13, that is to say indicate the number of the line in an eighth of frame; B13 receives the binary value 1, which indicates that addressing is carried out, during entry, on the "image memory" part of the memories of the micro-processing units; B14 to B16 are excited by C14 to C16, which indicate the number of the eight micro-units that is addressed; and B17 receives the binary value 1, which indicates that the addressing takes place on the memories of the micro-processing units.

 Furthermore, a signal generator 106, also controlled by the circuit 03, puts the four lines OCTO - OCT3 mentioned above in the active state, which indicates that, during the entry, the memories work on four bytes at a time.

In addition, the generator 106 puts the read-write line in write mode and controls the cycle start line in accordance with the requirements of the memories of the micro-processing units.

 It will be noted that, as far as the generation of addresses is concerned, the operation which we have just described is equivalent to the addressing of a single and continuous memory of 256 K bytes (K = 1024).

 The manner of generating these addresses described above makes it possible to simply solve the problem of the temporal separation of the two frames and the image is traversed using a natural numbering of the addresses by increment of one unit between the successive points.

Seizure involving a large number of points
(512 x 512) in a video image, and taking place in # real time scanning of the two frames of this image by a television camera (1/25 sec.), The converter 2 must be fast enough for this work in real time, the data transfer by words of four bytes contributing however to facilitate the seizure. No slowdown of the camera scanning is necessary.

The speed of the capture (1 point every 100 ns) practically requires, to stay in simple solutions, to wait for the end of the capture to start processing the image.

This solution departs from previous solutions and contributes to simplifying the problem of synchronization.

 The display unit (5, Figure 1) has a structure of the same type as the input unit and will therefore not be described in detail.

 Figure 3 shows in more detail a micro-processing unit. It includes a memory 70 having for example a capacity of 32 K bytes for the "image" part and 8 K bytes for the "processing" part. This memory is of a type, known per se, having a selection mechanism which allows, when the four words OCTO to OCTO 3 are validated (which is the case during the data entry operation) to consider the memory of the micro-unit as a memory addressable by words of 32 bits, while allowing access by byte.

 The memory of the micro-processing unit can be linked with units other than the input unit (in particular with the processor 15) and each of the four lines OCTO to OT03 can then be validated or not: this will make it possible to whether or not to participate in the byte corresponding to each of said lines in the operation in progress.

 Returning to FIG. 3, it can be seen that the micro-processing unit described comprises a micro-processor 71 responsible for executing the programs located in the "processing" part of the memory 70. The micro-processor is connected to the control unit by the interruption line 181 and the "Reset" line 182 which allows the initialization of the micro-processing unit and by two lines (710 and 711), # allows the control of the two doors 72 and 73 of the micro-processing unit.

 When the microprocessor has ordered the opening of door 72, door 73 is closed and access to memory 70 is exclusively reserved for the microprocessor. When the microprocessor has ordered the opening of door 73, door 72 is closed and access to memory 70 is then exclusively reserved, via the megabus 18, to units other than the microprocessor. Gate 73 includes a selection mechanism capable of deciding, by comparison of bits B14 to B17 of the addresses received on the megabus 18 and of a name assigned to each micro-unit (received by the link 701, if the memory of the micro-unit considered is concerned or not by the operation in progress.

The operation of the micro-processing unit which has just been described is as follows
After resetting (line 182 active); the door 73 is open and the microprocessor 71 is in the "halt" state. The control unit (15 - 16) then performs its work (which will be described later and which comprises, in particular, the loading, into the memory of the micro-processing unit, of the programs necessary for the execution of an order), then sends an interrupt to each micro-processing unit.

At this time, the microprocessor of each processing unit becomes active, closes the door 73, opens the door 72 and performs the requested processing (by means of the commands deposited in its memory). During the time when the door 73 is closed, the memory 70 is protected, that is to say that any attempt to read this memory (for example, made by the processor 15, to know if the micro-processing unit considerme has finished its work) has the effect of delivering an agreed value meaning that the memory is not accessible and this, without interrupting the work of the microprocessor 71.

 When the requested work is completed, the microprocessor 71 closes the door 72, opens the door 73 and goes into the halo state.

 The practical realization of doors 72 and 73 is within the reach of the skilled person. Thanks to doors 72 and 73, the processing microuni ty can be isolated from the rest of the machine and, among the information circulating on the megabus, the micro-unit recognizes those intended for it.

We will now describe, with reference to FIG. 4, the control unit 15-16 of FIG. 1. The processor 15 comprises a microprocessor 150; its own memory 151 containing programs and data; a certain number of interfaces (152: interface of the mass memory; 153: interface of the terminal 17 of communication with the user; entry doors, specialized exit 154, through which pass on the one hand the
names assigned to the different micro-processing units and input and display units of the machine, on the other hand, the control words of the input and display units); a signal generator 155, to which the various interrupt lines are connected to the micro-processing units and the input and display units; a member 156 for accessing the megabus 18, projecting the local bus 157 into the megabus and generating the appropriate OCTO - OCT3 addresses and signals; an interrupt line 158 (input) receiving the end of input signal sent by the input unit on the link 1030; and a "Reset" line 159 which allows the initialization of the control unit.

In operation, in the initial state, all the units or micro-units of the machine are in the high state. The microprocessor 150 of the control unit begins to execute a program pre-recorded in a part of the own memory 151.

This program will
a) assign names, via doors 154, to the units
and micro-units,
b) indicate to the user of the machine that he is
ready,
c) read a command issued by the user
d) execute this command
e) return to (b)
There are four main types of commands
a) capture an image; b) display an image; c) perform processing on an image; d) save or restore an image to / from the mass memory. Commands (a) - (c) and (d) end leaving the participating units in the "halt" state, while command (b) is held until the user issues another ordered. The control unit must therefore memorize the display state to, if necessary, interrupt the display at the start of each of the other commands.

Ultimately, at the start of each command, the processing units and micro-units are in the halo state, the doors 73 are open and the entry and display are stopped. For the command of an input, the control unit analyzes the command and, using its parameters, generates a command word which it sends to the input unit, then an interrupt - address set
of the input unit that starts it. The entry is then executed in the manner described above and ends with the emission of an end of entry signal.

 The process for the display control and its interruption is the same. For the control of a treatment, the control unit analyzes the command and loads, if they are not already there, the programs necessary for its execution in the program zones of the memories of the various micro-processing units. This operation is done by direct access (member 156) between the mass memory (16) and the memory of each processing microuni ty. The control unit then loads, into the appropriate working areas of said memories, parameters allowing the execution of the programs and sends an interrupt to each of the micro-processing units. After a predetermined time, which depends on the nature of the processing, the control unit tries to perform a reading in said working areas. If, after several reading attempts, the memory of at least one processing micro-unit is not accessible the control unit decides that an error has occurred. Otherwise, the results are read in order to compose the final result of the processing and to communicate it to the terminal (17).

The operation of saving or restoring an image is carried out by direct access between the mass memory (16) and the "image memory" of the micro-processing units.

From the above description, it appears that the functional architecture of the machine is such that it behaves like an association of four different logical machines, obtained by a dynamic reconfiguration of the whole and a reallocation of the memory in progress d 'use.

 In the control machine, the general processor 15 has control and accesses the common memory (constituted by the memories of the micro-processing units) in its entirety. It interprets the commands issued by the operator or a user program and organizes the tasks to be executed: choice of the unit, which in turn will take control and access the memory.

In the input machine, circuit 103 assumes control and allows access to all of the common memory, addressed as if it were unique and continuous. The display machine operates in an analogous manner, the control circuit associated with the digital-analog converter (5) then having control, and the general processor (15) awaiting from the user an order to interrupt the display. In the processing machine, the eight local microprocessors, each connected to the memory of the corresponding processing micro-unit, have control and work in parallel, while the general processor (15) waits for the end of the processing. .

 In other words, the common memory is in a way dispersed in eight connectable banks, to one of the four logic machines.

These connections are established for a long time in relation to the memory cycle and are easily modifiable. Each processor also has visible local memory. The master processor is specialized, while the slaves are trivialized. Such a computer system, of the known general type with hierarchical control, does not fall into any category belonging to the prior art.

It will be noted that the local microprocessors (such as 71) and the converters (2 and 5) are interruptable only by the general processor (15) and therefore cannot communicate with each other. The general processor (15) is interruptible only by the analog-digital converter (2), and this, at the end of input; the rest of the time, he is the master of the situation.

However, each processing microprocessor remains in control of its own memory and decides whether or not to allocate it by controlling the corresponding doors.

 Thanks to this specific architecture, the particular structure of the processing unit and the particular organization of its links with the control unit, no conflict of access to the megabus, to the memory and to the different processors occurs and no complex synchronization mechanism is required in this machine. The important time required for such synchronization is therefore saved.

 The architecture specific to the machine described is suitable for carrying out the processing of the digitized image which contributes to highlighting the forms which it contains, without however using semantic information on the nature of these forms. For example, in hematology, these treatments will highlight more or less dark spots on a light background, without distinguishing between white blood cells and red blood cells. The algorithms used in such processing can all be executed in one or more sequential scans of the image and this is what makes it possible to have the same processing # performed simultaneously by several non-special microprocessors, on different parts. of the image. In practice, this condition imposed on the nature of the processing does not constitute an unacceptable limitation, it being understood that the processing of the semantic content of the image must be carried out by implementing other techniques, by means of a large computer. power associated with the machine.

It goes without saying that various modifications may be made to the diagrams described and shown, without departing from the spirit of the invention.

Claims (6)

1- Computerized input and processing device  of images, characterized by several operative units connected tees between them by a megabus and comprising: a unit of capturing images comprising a television camera and an analog-to-digital converter arranged for capturing in time real a full video image; a plurality of micro-units  each comprising a microprocessor, a memory, first and second logic circuits controlled by  the corresponding microprocessor and authorizing respectively  access to the memory, to said microprocessor and to the megabus, said memory being capable of storing information corresponding to a predetermined number of lines of the video image, means  to decide whether said micro-entity is concerned or not by an operation in progress; and a control unit, comprising a microprocessor, a mass memory, an interrupt signal generator connected to the other units and means for sending specific control words to said other units. 2- Device according to claim 1, characterized by  the fact that, the useful video image having 512 lines of 512 points, said plurality comprises eight micro-processing units whose memory comprises an "image" part of 32 K bytes.  3- Device according to claim 2, characterized in that the input unit comprises: means for generating, from the video signal, signals of even start of frame, start of odd frame and start of line; first means of comparing the most significant bits of an address circulating in the megabus with an affective name Input unit and, in the event of coincidence, to trigger, upon reception of an interrupt signal also emitted by the control unit, the successive acquisition of the lines of the even frame, then of those of the odd frame, followed by the transmission, to the microprocessor of the control unit, of an end of input signal, said acquisition comprising the emission on the megabus, every four points of the video image, of four bytes of corresponding data, of the second means controlled by the first means, of transmitting eighteen address bits (Bo a B17) on the megabus for each word of four bytes, of which the first seven (Bo a B6) define the word of the line, the eighth (B7) defines the frame, the next five (B8 to B12) define the number of the line in an eighth of frame, the following (B13) indicates that addressing is done on the di your "image" parts, the following three (B14 to B16) indicate the number of that of the eight micro-processing units which is addressed and the last (B17) means that the addressing is carried out or not on the memories of the micro -processing units.  4. Device according to one of claims 1 to 3, characterized by means of transmitting on the megabus four binary signals which may be individually valid or not, while each micro-processing unit comprises means, controlled by said signals binary, to selectively determine memory access for one, two, three or four bytes of each word.  5. Device according to one of claims 1 to 4, ca characterized in that each micro-processing unit includes means for delivering to any reading attempt made while said second logic circuit interrupts the connection between the corresponding memory and the megabus, information signifying that said memory is not accessible to other units.  start of each order. send an interrupt signal to said display unit to  includes means for memorizing the state of the display unit and  6. Device according to one of claims 1 to 5, wherein said operating units further comprise a display unit comprising a digital-analog converter and a control screen, characterized in that the control unit