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FR2450544A1 - SYSTEM AND METHOD FOR REAL-TIME AND DISTRIBUTED VIDEO IMAGE PROCESSING - Google Patents

SYSTEM AND METHOD FOR REAL-TIME AND DISTRIBUTED VIDEO IMAGE PROCESSING

Info

Publication number
FR2450544A1
FR2450544A1 FR8004192A FR8004192A FR2450544A1 FR 2450544 A1 FR2450544 A1 FR 2450544A1 FR 8004192 A FR8004192 A FR 8004192A FR 8004192 A FR8004192 A FR 8004192A FR 2450544 A1 FR2450544 A1 FR 2450544A1
Authority
FR
France
Prior art keywords
data
parallel
series
memory
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8004192A
Other languages
French (fr)
Other versions
FR2450544B3 (en
Inventor
Peter Colin Michael
Richard John Taylor
Martin Richard Trump
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micro Consultants Ltd
Original Assignee
Micro Consultants Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micro Consultants Ltd filed Critical Micro Consultants Ltd
Publication of FR2450544A1 publication Critical patent/FR2450544A1/en
Application granted granted Critical
Publication of FR2450544B3 publication Critical patent/FR2450544B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
    • H04N7/0137—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes dependent on presence/absence of motion, e.g. of motion zones
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Image Analysis (AREA)
  • Television Signal Processing For Recording (AREA)
  • Image Processing (AREA)

Abstract

MEMOIRE ET PROCESSEUR A REPARTITION, COMPRENANT UN SYSTEME DE REPERE DE MOUVEMENT. LE SYSTEME COMPREND UNE MEMOIRE D'IMAGE SUBDIVISEE EN UNE SERIE DE SECTEURS311 EN PARALLELE ET UN PROCESSEUR D'ENTREE COMPRENANT UNE SERIE D'UNITES ARITHMETIQUES 340, 341, 343 EN PARALLELE POUR TRAITER SIMULTANEMENT UNE DONNEE D'ENTREE AVEC LES DONNEES DES SECTEURS EN FONCTION D'UN MOUVEMENT. UN GENERATEUR 350 FOURNIT UN REPERE QUI INDIQUE LE MOUVEMENT DE L'IMAGE ENTRE LA DONNEE D'ENTREE ET LA DONNEE EN MEMOIRE ET ACCOMPAGNE LA DONNEE TRAITEE ET IL EST EGALEMENT PREVU UN PROCESSEUR DE SORTIE COMPRENANT UNE SERIE D'UNITES ARITHMETIQUES EN PARALLELE POUR TRAITER SIMULTANEMENT LES DONNEES DE SORTIE PROVENANT D'AU MOINS DEUX EMPLACEMENTS A L'INTERIEUR DE CHAQUE SECTEUR DE LA MEMOIRE. UN DETECTEUR349 EST PREVU POUR DETECTER LE REPERE DE MOUVEMENT ET DETERMINER SI LA DONNEE DE SORTIE DESTINEE AU TRAITEMENT PROVIENT D'UNE MEME TRAME OU D'AUTRES TRAMES. APPLICATION: EFFECTUER DIVERSES FONCTIONS DE TRAITEMENTS VIDEO TELS QUE LA REDUCTION DU BRUIT, LA CONVERSION D'UNITES DE MESURE ET LE CHANGEMENT DE DIMENSION DE L'IMAGE.MEMORY AND DISTRIBUTION PROCESSOR, INCLUDING A MOTION CUE SYSTEM. THE SYSTEM INCLUDES AN IMAGE MEMORY SUBDIVIDED INTO A SERIES OF PARALLEL SECTORS311 AND AN INPUT PROCESSOR INCLUDING A SERIES OF ARITHMETIC UNITS 340, 341, 343 IN PARALLEL TO SIMULTANEOUSLY PROCESS AN INPUT DATA WITH THE DATA FROM THE SECTORS IN PARALLEL. FUNCTION OF A MOVEMENT. A 350 GENERATOR PROVIDES A MARK WHICH INDICATES THE MOVEMENT OF THE IMAGE BETWEEN THE INPUT DATA AND THE DATA IN STORAGE AND ACCOMPANIES THE PROCESSED DATA AND AN OUTPUT PROCESSOR INCLUDING A SERIES OF ARITHMETIC UNITS IN PARALLEL IS ALSO PROVIDED. SIMULTANEOUSLY THE OUTPUT DATA FROM AT LEAST TWO LOCATIONS WITHIN EACH SECTOR OF THE MEMORY. A DETECTOR349 IS PROVIDED TO DETECT THE MOTION MARK AND DETERMINE IF THE OUTPUT DATA FOR PROCESSING IS COMING FROM THE SAME FRAME OR FROM OTHER FRAMES. APPLICATION: PERFORM VARIOUS VIDEO PROCESSING FUNCTIONS SUCH AS NOISE REDUCTION, UNITS OF MEASUREMENT CONVERSION AND IMAGE SIZE CHANGE.

FR8004192A 1979-02-27 1980-02-26 SYSTEM AND METHOD FOR REAL-TIME AND DISTRIBUTED VIDEO IMAGE PROCESSING Granted FR2450544A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1567879A 1979-02-27 1979-02-27

Publications (2)

Publication Number Publication Date
FR2450544A1 true FR2450544A1 (en) 1980-09-26
FR2450544B3 FR2450544B3 (en) 1981-11-20

Family

ID=21772892

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8004192A Granted FR2450544A1 (en) 1979-02-27 1980-02-26 SYSTEM AND METHOD FOR REAL-TIME AND DISTRIBUTED VIDEO IMAGE PROCESSING

Country Status (3)

Country Link
DE (1) DE3007381A1 (en)
FR (1) FR2450544A1 (en)
GB (1) GB2044580B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393621A2 (en) * 1989-04-18 1990-10-24 Kabushiki Kaisha Toshiba Recursive filter and image display apparatus including the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8410597D0 (en) * 1984-04-25 1984-05-31 Quantel Ltd Video signal processing
EP0408810B1 (en) * 1989-07-20 1996-03-20 Kabushiki Kaisha Toshiba Multi processor computer system
GB2245795A (en) * 1990-07-05 1992-01-08 Rank Cintel Ltd Generating convoluted digital video signals

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240911A (en) * 1975-09-27 1977-03-30 Kokusai Denshin Denwa Co Ltd <Kdd> Line number conversion system of tv signal
DE2617884C2 (en) * 1976-04-23 1985-03-21 Robert Bosch Gmbh, 7000 Stuttgart Standard converter for television signals
GB1594341A (en) * 1976-10-14 1981-07-30 Micro Consultants Ltd Picture information processing system for television

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393621A2 (en) * 1989-04-18 1990-10-24 Kabushiki Kaisha Toshiba Recursive filter and image display apparatus including the same
EP0393621A3 (en) * 1989-04-18 1991-04-17 Kabushiki Kaisha Toshiba Recursive filter and image display apparatus including the same

Also Published As

Publication number Publication date
GB2044580A (en) 1980-10-15
FR2450544B3 (en) 1981-11-20
DE3007381A1 (en) 1980-09-18
GB2044580B (en) 1983-03-23

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