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FR2435753A1 - Additionneur parallele de codes p de fibonacci - Google Patents

Additionneur parallele de codes p de fibonacci

Info

Publication number
FR2435753A1
FR2435753A1 FR7912192A FR7912192A FR2435753A1 FR 2435753 A1 FR2435753 A1 FR 2435753A1 FR 7912192 A FR7912192 A FR 7912192A FR 7912192 A FR7912192 A FR 7912192A FR 2435753 A1 FR2435753 A1 FR 2435753A1
Authority
FR
France
Prior art keywords
fibonacci
register
inverting output
podes
additioner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7912192A
Other languages
English (en)
Other versions
FR2435753B1 (fr
Inventor
A P Stakhov
N A Solyanichenko
V A Luzhetsky
A V Ovodenko
A A Kozak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VINNITSKY POLITEKHN INST
Original Assignee
VINNITSKY POLITEKHN INST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VINNITSKY POLITEKHN INST filed Critical VINNITSKY POLITEKHN INST
Publication of FR2435753A1 publication Critical patent/FR2435753A1/fr
Application granted granted Critical
Publication of FR2435753B1 publication Critical patent/FR2435753B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

L'invention concerne les techniques de calcul L'additionneur faisant l'objet de l'invention est caractérisé notamment en ce que la sortie non inverseuse du registre de nombre à augmenter 1 et la sortie non inverseuse du registre de nombre à ajouter 2 sont raccordées aux entrées du bloc de contrôle 12 et du détecteur de fin d'addition 13, que le registre de nombre à ajouter 2 a sa sortie inverseuse reliée à l'une des entrées du bloc 6 de réduction des codes p de Fibonacci à la forme minimale, dont l'autre entrée et l'autre sortie sont raccordées respecivement à la sortie non inverseuse du registre de nombre à augmenter 1 et à son entrée de normalisation. L'additionneur en question peut être utilisé dans les ordinateurs en vue d'additionner des nombres à chiffres multiples représentés en codes de Fibonacci.
FR7912192A 1978-05-15 1979-05-14 Additionneur parallele de codes p de fibonacci Granted FR2435753A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU782617011A SU840891A1 (ru) 1978-05-15 1978-05-15 Параллельный сумматор кодов фибоначчи

Publications (2)

Publication Number Publication Date
FR2435753A1 true FR2435753A1 (fr) 1980-04-04
FR2435753B1 FR2435753B1 (fr) 1982-05-07

Family

ID=20765179

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7912192A Granted FR2435753A1 (fr) 1978-05-15 1979-05-14 Additionneur parallele de codes p de fibonacci

Country Status (6)

Country Link
US (1) US4276608A (fr)
JP (1) JPS5538490A (fr)
DE (1) DE2919573A1 (fr)
FR (1) FR2435753A1 (fr)
GB (1) GB2025095B (fr)
SU (1) SU840891A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471454A (en) * 1981-10-27 1984-09-11 Ibm Corporation Fast, efficient, small adder
JPS59203897A (ja) * 1983-05-06 1984-11-19 Seibu Denki Kogyo Kk 二段翼軸流フアンの可変翼ピツチ装置
US4818969A (en) * 1984-08-09 1989-04-04 Kronos, Inc. Method of fixed-length binary encoding and decoding and apparatus for same
US6934733B1 (en) * 2001-12-12 2005-08-23 Lsi Logic Corporation Optimization of adder based circuit architecture
CN112787658B (zh) * 2020-12-31 2022-12-13 卓尔智联(武汉)研究院有限公司 基于斐波那契进制的逻辑运算电路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2375655A1 (fr) * 1976-12-22 1978-07-21 Taganrogskij Radiotech Inst Additionneur de codes de fibonacci

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU577528A1 (ru) * 1976-02-13 1977-10-25 Таганрогский радиотехнический институт им. В.Д.Калмыкова Накапливающий сумматор

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2375655A1 (fr) * 1976-12-22 1978-07-21 Taganrogskij Radiotech Inst Additionneur de codes de fibonacci

Also Published As

Publication number Publication date
JPS5735496B2 (fr) 1982-07-29
US4276608A (en) 1981-06-30
FR2435753B1 (fr) 1982-05-07
DE2919573A1 (de) 1979-11-29
GB2025095B (en) 1982-03-10
SU840891A1 (ru) 1981-06-23
JPS5538490A (en) 1980-03-17
GB2025095A (en) 1980-01-16

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Legal Events

Date Code Title Description
ST Notification of lapse