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FR2408175A1 - Appareil de traitement de donnees comprenant une memoire pour micro-instructions - Google Patents

Appareil de traitement de donnees comprenant une memoire pour micro-instructions

Info

Publication number
FR2408175A1
FR2408175A1 FR7831414A FR7831414A FR2408175A1 FR 2408175 A1 FR2408175 A1 FR 2408175A1 FR 7831414 A FR7831414 A FR 7831414A FR 7831414 A FR7831414 A FR 7831414A FR 2408175 A1 FR2408175 A1 FR 2408175A1
Authority
FR
France
Prior art keywords
memory
instructions
micro
processing apparatus
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7831414A
Other languages
English (en)
Other versions
FR2408175B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of FR2408175A1 publication Critical patent/FR2408175A1/fr
Application granted granted Critical
Publication of FR2408175B1 publication Critical patent/FR2408175B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

UN APPAREIL DE TRAITEMENT DE DONNEES COMPREND UNE MEMOIRE POUR MICRO-INSTRUCTIONS 11 ADAPTEE POUR FOURNIR DES MICRO-INSTRUCTIONS CONTENANT UNE PREMIERE ET UNE SECONDE ADRESSES QUI SONT PRESENTEES A UNE MEMOIRE DESCRIPTEURS A DOUBLE ACCES 13 POUR FOURNIR UN PREMIER ET UN SECOND MOTS DESCRIPTEURS COMPRENANT CHACUN LES POSITIONS DES BITS DE DELIMITATION ET DES INFORMATIONS SUR LA LONGUEUR DES OPERANDES DE LONGUEUR VARIABLE RESPECTIFS STOCKES DANS UNE MEMOIRE DE TRAVAIL A DOUBLE ACCES 15. LES OPERANDES LUS SONT ALIGNES AUTOMATIQUEMENT SUR LES ENTREES D'UNE UNITE ARITHMETIQUE ET LOGIQUE 17 EN FONCTION DES INFORMATIONS CONTENUES DANS LES MOTS DESCRIPTEURS RESPECTIFS. LA MEMOIRE DE TRAVAIL 15 EST COUPLEE A UNE MEMOIRE PRINCIPALE DONT ELLE PEUT RECEVOIR DES INSTRUCTIONS VIRTUELLES ET DES DONNEES.
FR7831414A 1977-11-07 1978-11-07 Appareil de traitement de donnees comprenant une memoire pour micro-instructions Expired FR2408175B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/849,048 US4135242A (en) 1977-11-07 1977-11-07 Method and processor having bit-addressable scratch pad memory

Publications (2)

Publication Number Publication Date
FR2408175A1 true FR2408175A1 (fr) 1979-06-01
FR2408175B1 FR2408175B1 (fr) 1986-04-11

Family

ID=25304934

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7831414A Expired FR2408175B1 (fr) 1977-11-07 1978-11-07 Appareil de traitement de donnees comprenant une memoire pour micro-instructions

Country Status (5)

Country Link
US (1) US4135242A (fr)
JP (1) JPS5474645A (fr)
DE (1) DE2847934A1 (fr)
FR (1) FR2408175B1 (fr)
GB (1) GB2008822B (fr)

Families Citing this family (50)

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US4276596A (en) * 1979-01-02 1981-06-30 Honeywell Information Systems Inc. Short operand alignment and merge operation
US4305124A (en) * 1978-06-09 1981-12-08 Ncr Corporation Pipelined computer
US4268909A (en) * 1979-01-02 1981-05-19 Honeywell Information Systems Inc. Numeric data fetch - alignment of data including scale factor difference
US4246644A (en) * 1979-01-02 1981-01-20 Honeywell Information Systems Inc. Vector branch indicators to control firmware
US4467443A (en) * 1979-07-30 1984-08-21 Burroughs Corporation Bit addressable variable length memory system
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
JPS5847053B2 (ja) * 1979-11-19 1983-10-20 株式会社日立製作所 デ−タ処理装置
CA1174370A (fr) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Unite de traitement de donnees avec operandes a traitement "pipeline"
USRE32493E (en) * 1980-05-19 1987-09-01 Hitachi, Ltd. Data processing unit with pipelined operands
JPS5743239A (en) * 1980-08-27 1982-03-11 Hitachi Ltd Data processor
US4445172A (en) * 1980-12-31 1984-04-24 Honeywell Information Systems Inc. Data steering logic for the output of a cache memory having an odd/even bank structure
US4520439A (en) * 1981-01-05 1985-05-28 Sperry Corporation Variable field partial write data merge
US4429372A (en) 1981-06-16 1984-01-31 International Business Machines Corporation Method for integrating structured data and string data on a text processing system
US4467416A (en) * 1981-09-16 1984-08-21 Honeywell Information Systems Inc. Logic transfer and decoding system
US4460959A (en) * 1981-09-16 1984-07-17 Honeywell Information Systems Inc. Logic control system including cache memory for CPU-memory transfers
US4575583A (en) * 1981-10-01 1986-03-11 At&T Bell Laboratories Programmable digital controller for generating instructions
US4654781A (en) * 1981-10-02 1987-03-31 Raytheon Company Byte addressable memory for variable length instructions and data
US4491908A (en) * 1981-12-01 1985-01-01 Honeywell Information Systems Inc. Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit
JPS58182754A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd 演算処理装置
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
US4597044A (en) * 1982-10-14 1986-06-24 Honeywell Information Systems, Inc. Apparatus and method for providing a composite descriptor in a data processing system
JPS61502566A (ja) * 1984-06-27 1986-11-06 モトロ−ラ・インコ−ポレ−テツド ビツト・フイ−ルド命令の方法と装置
US5034900A (en) * 1984-10-05 1991-07-23 Hitachi, Ltd. Method and apparatus for bit operational process
US6552730B1 (en) 1984-10-05 2003-04-22 Hitachi, Ltd. Method and apparatus for bit operational process
US5265204A (en) * 1984-10-05 1993-11-23 Hitachi, Ltd. Method and apparatus for bit operational process
US4847759A (en) * 1985-03-18 1989-07-11 International Business Machines Corp. Register selection mechanism and organization of an instruction prefetch buffer
US4907148A (en) * 1985-11-13 1990-03-06 Alcatel U.S.A. Corp. Cellular array processor with individual cell-level data-dependent cell control and multiport input memory
US5155820A (en) * 1989-02-21 1992-10-13 Gibson Glenn A Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits
JPH0395629A (ja) * 1989-09-08 1991-04-22 Fujitsu Ltd データ処理装置
US5471628A (en) * 1992-06-30 1995-11-28 International Business Machines Corporation Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode
US6034674A (en) * 1992-06-30 2000-03-07 Discovision Associates Buffer manager
US5861894A (en) * 1993-06-24 1999-01-19 Discovision Associates Buffer manager
EP0674266A3 (fr) * 1994-03-24 1997-12-03 Discovision Associates Procédé et dispositif d'interface de mémoire à accès aléatoire
CA2145365C (fr) * 1994-03-24 1999-04-27 Anthony M. Jones Methode d'acces a des batteries de memoires vives dynamiques
CA2145363C (fr) * 1994-03-24 1999-07-13 Anthony Mark Jones Interface pour memoire vive
US5963154A (en) * 1994-07-29 1999-10-05 Discovision Associates Technique for decoding variable and fixed length codes
US6119213A (en) * 1995-06-07 2000-09-12 Discovision Associates Method for addressing data having variable data width using a fixed number of bits for address and width defining fields
US5911152A (en) * 1995-09-05 1999-06-08 Compaq Computer Corporation Computer system and method for storing data in a buffer which crosses page boundaries utilizing beginning and ending buffer pointers
US5860138A (en) * 1995-10-02 1999-01-12 International Business Machines Corporation Processor with compiler-allocated, variable length intermediate storage
US6173247B1 (en) * 1997-06-18 2001-01-09 Dsp Software Engineering, Inc. Method and apparatus for accurately modeling digital signal processors
US6820195B1 (en) * 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6418489B1 (en) * 1999-10-25 2002-07-09 Motorola, Inc. Direct memory access controller and method therefor
JP3719897B2 (ja) * 2000-02-29 2005-11-24 富士通株式会社 データ転送装置、データ転送方法及び記録媒体
US6912173B2 (en) * 2001-06-29 2005-06-28 Broadcom Corporation Method and system for fast memory access
US7370184B2 (en) * 2001-08-20 2008-05-06 The United States Of America As Represented By The Secretary Of The Navy Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit
US7685405B1 (en) * 2005-10-14 2010-03-23 Marvell International Ltd. Programmable architecture for digital communication systems that support vector processing and the associated methodology
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
KR101700405B1 (ko) * 2010-03-22 2017-01-26 삼성전자주식회사 레지스터, 프로세서 및 프로세서 제어 방법
US9600194B1 (en) 2015-11-25 2017-03-21 International Business Machines Corporation Integrating sign extensions for loads
CN107688466B (zh) * 2016-08-05 2020-11-03 中科寒武纪科技股份有限公司 一种运算装置及其操作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3401375A (en) * 1965-10-01 1968-09-10 Digital Equipment Corp Apparatus for performing character operations
US3440615A (en) * 1966-08-22 1969-04-22 Ibm Overlapping boundary storage
US3654621A (en) * 1969-11-28 1972-04-04 Burroughs Corp Information processing system having means for dynamic memory address preparation
FR2156445A1 (fr) * 1971-10-20 1973-06-01 Cii

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
BE758811A (fr) * 1969-11-28 1971-04-16 Burroughs Corp Systeme de traitement d'information ayant un emmagasinage sans structure pour traitements emboites
US3739352A (en) * 1971-06-28 1973-06-12 Burroughs Corp Variable word width processor control
FR111574A (fr) * 1973-12-13 1900-01-01
IT1016854B (it) * 1974-08-21 1977-06-20 Olivetti & Co Spa Calcolatore elettronico di elabora zione dati

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3401375A (en) * 1965-10-01 1968-09-10 Digital Equipment Corp Apparatus for performing character operations
US3440615A (en) * 1966-08-22 1969-04-22 Ibm Overlapping boundary storage
US3654621A (en) * 1969-11-28 1972-04-04 Burroughs Corp Information processing system having means for dynamic memory address preparation
FR2156445A1 (fr) * 1971-10-20 1973-06-01 Cii

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/71 *

Also Published As

Publication number Publication date
FR2408175B1 (fr) 1986-04-11
GB2008822B (en) 1982-05-12
GB2008822A (en) 1979-06-06
US4135242A (en) 1979-01-16
JPS5474645A (en) 1979-06-14
DE2847934A1 (de) 1979-05-10

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Legal Events

Date Code Title Description
ST Notification of lapse