FR2382093A2 - PROCESS FOR THE MANUFACTURING OF COLLECTIVELY PASSIVE SEMICONDUCTOR DEVICES, AND DEVICES THUS OBTAINED - Google Patents
PROCESS FOR THE MANUFACTURING OF COLLECTIVELY PASSIVE SEMICONDUCTOR DEVICES, AND DEVICES THUS OBTAINEDInfo
- Publication number
- FR2382093A2 FR2382093A2 FR7705255A FR7705255A FR2382093A2 FR 2382093 A2 FR2382093 A2 FR 2382093A2 FR 7705255 A FR7705255 A FR 7705255A FR 7705255 A FR7705255 A FR 7705255A FR 2382093 A2 FR2382093 A2 FR 2382093A2
- Authority
- FR
- France
- Prior art keywords
- devices
- collectively
- grooves
- diodes
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 2
- 238000002161 passivation Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/50—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Sensors (AREA)
Abstract
L'addition porte sur des perfectionnements concernant notamment la fabrication de diodes << P-I-N >> passivées collectivement. Un premier perfectionnement concerne l'utilisation d'une couche épitaxiale épaisse et fortement dopée servant de substrat pendant le creusement des sillons 21, ledit substrat 3 étant ensuite rodé jusqu'au niveau des sillons pour séparer les diodes. Un deuxième perfectionnement concerne un tracé hexagonal des sillons donnant des arêtes moins aiguës favorisant la passivation. Application aux diodes à couche << I >> relativement épaisse.The addition relates to improvements relating in particular to the manufacture of collectively passivated "P-I-N" diodes. A first improvement relates to the use of a thick and heavily doped epitaxial layer serving as a substrate during the digging of the grooves 21, said substrate 3 then being lapped up to the level of the grooves to separate the diodes. A second improvement relates to a hexagonal outline of the grooves giving less sharp edges favoring passivation. Application to relatively thick "I" film diodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7705255A FR2382093A2 (en) | 1973-03-09 | 1977-02-23 | PROCESS FOR THE MANUFACTURING OF COLLECTIVELY PASSIVE SEMICONDUCTOR DEVICES, AND DEVICES THUS OBTAINED |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7308561A FR2220877A1 (en) | 1973-03-09 | 1973-03-09 | PIN diodes collectively made from PIN chip - are formed between electrodes by etching parallel trenches in two stages followed by separation |
FR7705255A FR2382093A2 (en) | 1973-03-09 | 1977-02-23 | PROCESS FOR THE MANUFACTURING OF COLLECTIVELY PASSIVE SEMICONDUCTOR DEVICES, AND DEVICES THUS OBTAINED |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2382093A2 true FR2382093A2 (en) | 1978-09-22 |
FR2382093B2 FR2382093B2 (en) | 1980-10-24 |
Family
ID=34227829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7705255A Granted FR2382093A2 (en) | 1973-03-09 | 1977-02-23 | PROCESS FOR THE MANUFACTURING OF COLLECTIVELY PASSIVE SEMICONDUCTOR DEVICES, AND DEVICES THUS OBTAINED |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2382093A2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0537306A4 (en) * | 1990-11-05 | 1994-05-18 | Harris Corp | Process for forming extremely thin integrated circuit dice |
EP0583625A3 (en) * | 1992-07-17 | 1994-08-24 | Lsi Logic Corp | Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of i/o area to active area per die |
WO2002049076A3 (en) * | 2000-12-15 | 2002-11-14 | Koninkl Philips Electronics Nv | Semiconductor device layout |
-
1977
- 1977-02-23 FR FR7705255A patent/FR2382093A2/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0537306A4 (en) * | 1990-11-05 | 1994-05-18 | Harris Corp | Process for forming extremely thin integrated circuit dice |
EP0583625A3 (en) * | 1992-07-17 | 1994-08-24 | Lsi Logic Corp | Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of i/o area to active area per die |
WO2002049076A3 (en) * | 2000-12-15 | 2002-11-14 | Koninkl Philips Electronics Nv | Semiconductor device layout |
Also Published As
Publication number | Publication date |
---|---|
FR2382093B2 (en) | 1980-10-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CL | Concession to grant licences |