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FR2371733A1 - Systeme d'acces aux memoires - Google Patents

Systeme d'acces aux memoires

Info

Publication number
FR2371733A1
FR2371733A1 FR7734658A FR7734658A FR2371733A1 FR 2371733 A1 FR2371733 A1 FR 2371733A1 FR 7734658 A FR7734658 A FR 7734658A FR 7734658 A FR7734658 A FR 7734658A FR 2371733 A1 FR2371733 A1 FR 2371733A1
Authority
FR
France
Prior art keywords
memory
memories
accesses
input
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7734658A
Other languages
English (en)
Other versions
FR2371733B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2371733A1 publication Critical patent/FR2371733A1/fr
Application granted granted Critical
Publication of FR2371733B1 publication Critical patent/FR2371733B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un système qui valide des accès à un certain nombre de mémoires avec l'assurance que les accès à une mémoire impropre sont détectés. Le système d'entrée/sortie comporte une unité de traitement d'entrée/sortie et au moins des unités de première et de seconde mémoires. La première mémoire est une mémoire morte (ROM) codée de façon à stocker des instructions de routines de commande. La seconde mémoire est une mémoire lisible/inscriptible dans laquelle sont stockées des instructions et des données nécessaires au fonctionnement du système de commande. L'unité de traitement contient plusieurs registres de stockage, un registre de commande et un registre de direction. Application: accès aux mémoires d'un système de traitement de données.
FR7734658A 1976-11-18 1977-11-17 Systeme d'acces aux memoires Granted FR2371733A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/742,814 US4124891A (en) 1976-11-18 1976-11-18 Memory access system

Publications (2)

Publication Number Publication Date
FR2371733A1 true FR2371733A1 (fr) 1978-06-16
FR2371733B1 FR2371733B1 (fr) 1984-05-04

Family

ID=24986338

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7734658A Granted FR2371733A1 (fr) 1976-11-18 1977-11-17 Systeme d'acces aux memoires

Country Status (7)

Country Link
US (1) US4124891A (fr)
JP (1) JPS5391538A (fr)
AU (1) AU509302B2 (fr)
CA (1) CA1098217A (fr)
DE (1) DE2750721A1 (fr)
FR (1) FR2371733A1 (fr)
GB (1) GB1595438A (fr)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4261033A (en) * 1977-01-19 1981-04-07 Honeywell Information Systems Inc. Communications processor employing line-dedicated memory tables for supervising data transfers
US4296466A (en) * 1978-01-23 1981-10-20 Data General Corporation Data processing system including a separate input/output processor with micro-interrupt request apparatus
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4459666A (en) * 1979-09-24 1984-07-10 Control Data Corporation Plural microcode control memory
US4521858A (en) * 1980-05-20 1985-06-04 Technology Marketing, Inc. Flexible addressing and sequencing system for operand memory and control store using dedicated micro-address registers loaded solely from alu
US4370712A (en) * 1980-10-31 1983-01-25 Honeywell Information Systems Inc. Memory controller with address independent burst mode capability
DE3176878D1 (en) * 1980-11-10 1988-10-20 Wang Laboratories Data transmitting link
US4509140A (en) * 1980-11-10 1985-04-02 Wang Laboratories, Inc. Data transmitting link
JPS57117027A (en) * 1981-01-13 1982-07-21 Nec Corp Signal sending and receiving circuit
US4646236A (en) * 1981-04-17 1987-02-24 International Business Machines Corp. Pipelined control apparatus with multi-process address storage
US4484263A (en) * 1981-09-25 1984-11-20 Data General Corporation Communications controller
US4803655A (en) * 1981-12-04 1989-02-07 Unisys Corp. Data processing system employing a plurality of rapidly switchable pages for providing data transfer between modules
JPS6145272B2 (fr) * 1981-12-04 1986-10-07 Burroughs Corp
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4538223A (en) * 1982-09-29 1985-08-27 Microdata Corporation Computer operand address computation
US4524415A (en) * 1982-12-07 1985-06-18 Motorola, Inc. Virtual machine data processor
US4823308A (en) * 1984-02-02 1989-04-18 Knight Technology Ltd. Microcomputer with software protection
JPS6140650A (ja) * 1984-08-02 1986-02-26 Nec Corp マイクロコンピユ−タ
US4918586A (en) * 1985-07-31 1990-04-17 Ricoh Company, Ltd. Extended memory device with instruction read from first control store containing information for accessing second control store
US4858138A (en) * 1986-09-02 1989-08-15 Pitney Bowes, Inc. Secure vault having electronic indicia for a value printing system
JPS6381554A (ja) * 1986-09-25 1988-04-12 Canon Inc 交換可能な周辺装置を取り扱う電子機器
US5193154A (en) * 1987-07-10 1993-03-09 Hitachi, Ltd. Buffered peripheral system and method for backing up and retrieving data to and from backup memory device
US5134700A (en) * 1987-09-18 1992-07-28 General Instrument Corporation Microcomputer with internal ram security during external program mode
US4964033A (en) * 1989-01-03 1990-10-16 Honeywell Inc. Microprocessor controlled interconnection apparatus for very high speed integrated circuits
US5598569A (en) * 1994-10-17 1997-01-28 Motorola Inc. Data processor having operating modes selected by at least one mask option bit and method therefor
US5666508A (en) * 1995-06-07 1997-09-09 Texas Instruments Incorporated Four state two bit recoded alignment fault state circuit for microprocessor address misalignment fault generation
US6883171B1 (en) * 1999-06-02 2005-04-19 Microsoft Corporation Dynamic address windowing on a PCI bus
USD427323S (en) * 1999-07-13 2000-06-27 John Lihan Oil spill barricade
US7149842B2 (en) * 2003-07-17 2006-12-12 Sun Microsystems, Inc. Efficient utilization of shared buffer memory and method for operating the same
US8332598B2 (en) * 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US7587521B2 (en) * 2005-06-23 2009-09-08 Intel Corporation Mechanism for assembling memory access requests while speculatively returning data
US7765366B2 (en) * 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US8253751B2 (en) 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US7558941B2 (en) * 2005-06-30 2009-07-07 Intel Corporation Automatic detection of micro-tile enabled memory
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3806880A (en) * 1971-12-02 1974-04-23 North American Rockwell Multiplexing system for address decode logic
US3821715A (en) * 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer
FR2305792A1 (fr) * 1975-03-26 1976-10-22 Honeywell Inf Systems Systeme generateur de code de direction pour un systeme de traitement d'entree/sortie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3806880A (en) * 1971-12-02 1974-04-23 North American Rockwell Multiplexing system for address decode logic
US3821715A (en) * 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer
FR2305792A1 (fr) * 1975-03-26 1976-10-22 Honeywell Inf Systems Systeme generateur de code de direction pour un systeme de traitement d'entree/sortie

Also Published As

Publication number Publication date
AU2919077A (en) 1979-04-05
JPS5391538A (en) 1978-08-11
CA1098217A (fr) 1981-03-24
GB1595438A (en) 1981-08-12
FR2371733B1 (fr) 1984-05-04
AU509302B2 (en) 1980-05-01
DE2750721A1 (de) 1978-05-24
US4124891A (en) 1978-11-07

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Legal Events

Date Code Title Description
ST Notification of lapse