[go: up one dir, main page]

FR2296967A1 - LARGE DENSITY LOGICAL NETWORK - Google Patents

LARGE DENSITY LOGICAL NETWORK

Info

Publication number
FR2296967A1
FR2296967A1 FR7534722A FR7534722A FR2296967A1 FR 2296967 A1 FR2296967 A1 FR 2296967A1 FR 7534722 A FR7534722 A FR 7534722A FR 7534722 A FR7534722 A FR 7534722A FR 2296967 A1 FR2296967 A1 FR 2296967A1
Authority
FR
France
Prior art keywords
circuits
input wires
logical network
interrogation signals
large density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7534722A
Other languages
French (fr)
Other versions
FR2296967B1 (en
Inventor
Dennis T Cox
William T Devine
Gilbert J Kelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/537,219 external-priority patent/US3987287A/en
Priority claimed from US05/537,218 external-priority patent/US3936812A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2296967A1 publication Critical patent/FR2296967A1/en
Application granted granted Critical
Publication of FR2296967B1 publication Critical patent/FR2296967B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Electronic Switches (AREA)

Abstract

Logic switching circuits are provided at least at some crosspoints. They carry out ogic operations in accordance with interrogation signals applied to input wires. Interrogation circuits are provided at both ends of at least some of the input wires, so that two different interrogation signals can be applied to the same wire. Some of these input wires are divided in sections in orer to form two groups of mutually independent logic circuits so that two interrogation signals applied to the same inpu wire control only one group of logic switching circuits.
FR7534722A 1974-12-30 1975-11-05 LARGE DENSITY LOGICAL NETWORK Granted FR2296967A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/537,219 US3987287A (en) 1974-12-30 1974-12-30 High density logic array
US05/537,218 US3936812A (en) 1974-12-30 1974-12-30 Segmented parallel rail paths for input/output signals

Publications (2)

Publication Number Publication Date
FR2296967A1 true FR2296967A1 (en) 1976-07-30
FR2296967B1 FR2296967B1 (en) 1978-05-12

Family

ID=27065418

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7534722A Granted FR2296967A1 (en) 1974-12-30 1975-11-05 LARGE DENSITY LOGICAL NETWORK

Country Status (1)

Country Link
FR (1) FR2296967A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2331209A1 (en) * 1975-11-06 1977-06-03 Ibm STRUCTURE OF A MODIFIABLE DECODER FOR A LOGIC NETWORK
FR2365883A1 (en) * 1976-09-27 1978-04-21 Siemens Ag SEMI-CONDUCTIVE PLATE FOR THE MANUFACTURE OF MODULES WITH HIGH INTEGRATION DENSITY
FR2471023A1 (en) * 1979-12-07 1981-06-12 Ibm France MATRIX NETWORK OF SEMICONDUCTOR ELEMENTS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1300301A (en) * 1970-04-20 1972-12-20 Gen Instr Microelect Read-only memories

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1300301A (en) * 1970-04-20 1972-12-20 Gen Instr Microelect Read-only memories

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ARTICLE "APPLICATION OF A HIGH SPEED PROGRAMMABLE LOGIC ARRAY" PRIEL ET HOLLAND *
PAGES 94-96) *
REVUE US "COMPUTER DESIGN", VOLUME 12, NO. 12, DECEMBRE 1973 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2331209A1 (en) * 1975-11-06 1977-06-03 Ibm STRUCTURE OF A MODIFIABLE DECODER FOR A LOGIC NETWORK
FR2365883A1 (en) * 1976-09-27 1978-04-21 Siemens Ag SEMI-CONDUCTIVE PLATE FOR THE MANUFACTURE OF MODULES WITH HIGH INTEGRATION DENSITY
FR2471023A1 (en) * 1979-12-07 1981-06-12 Ibm France MATRIX NETWORK OF SEMICONDUCTOR ELEMENTS
EP0030280A1 (en) * 1979-12-07 1981-06-17 International Business Machines Corporation Matrix array of semiconductor elements

Also Published As

Publication number Publication date
FR2296967B1 (en) 1978-05-12

Similar Documents

Publication Publication Date Title
CH489623A (en) Technical wire made of thermoplastic material
SE409061B (en) PRIORITY LINK IN WHICH INPUT GROUPS ARE TREATED IN A CYCLIC ORDER WITH MAINTAINING A FIXED PRIORITY WITH AN INPUT GROUP
CH469406A (en) Control mixing console with changeable operating circuit, especially for sound studio technology
FR2296967A1 (en) LARGE DENSITY LOGICAL NETWORK
CH554113A (en) MULTI-LEVEL SWITCHING NETWORK FOR SELECTIVE CONNECTION OF AT LEAST ONE OF SEVERAL INPUT TRANSMISSION LINES TO ONE OF SEVERAL OUTPUT TRANSMISSION LINES.
ES147750U (en) Network structure (Machine-translation by Google Translate, not legally binding)
DK127528B (en) Engine control circuit.
CH526241A (en) Switching system with coupling points having four-layer semiconductors
CH410483A (en) Passage wheel with moving contacts, especially for permutation switches
AT299324B (en) Telecommunication switching system with central control
CH505522A (en) Multi-stage switching network with electronic crosspoint contacts
DK127490B (en) Self-seeking multi-stage electronic switching network.
AT309540B (en) Circuit arrangement for centrally controlled telecommunications switching systems, in particular telephone switching systems, with two-way connections
CH495242A (en) Automatic coupling that establishes electrical connections for heating and control circuits of mainline railways
CH536586A (en) Circuit arrangement for telecommunication, in particular telephone switching systems, with time division multiple operation
FR1375400A (en) Synthetic branch grid, in particular for main electrical circuits
AT308205B (en) Circuit arrangement for centrally controlled telecommunications switching systems, in particular telephone switching systems, with two-way connections
AT266227B (en) Circuit arrangement for centrally controlled telecommunication systems, in particular telephone systems, with two-way connections
AT282688B (en) Switching arrangement for the transmission of information, in particular for the control of signals
CH521667A (en) Circuit arrangement for telecommunications systems, in particular telephone exchanges, with cross-field control devices
CH534991A (en) Selection circuit, especially for telecommunications switching systems
NL152145B (en) TELECOMMUNICATIONS TRANSMISSION SYSTEM WITH PILOT CONTROL.
CH530745A (en) Telecommunication, in particular telephone switching system with program-controlled control units
AT288495B (en) Circuit arrangement for centrally controlled switching systems, in particular telephone switching systems
CH509659A (en) Coordinate switch with self-retaining crosspoints

Legal Events

Date Code Title Description
ST Notification of lapse