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FR2178007B1 - - Google Patents

Info

Publication number
FR2178007B1
FR2178007B1 FR7310813A FR7310813A FR2178007B1 FR 2178007 B1 FR2178007 B1 FR 2178007B1 FR 7310813 A FR7310813 A FR 7310813A FR 7310813 A FR7310813 A FR 7310813A FR 2178007 B1 FR2178007 B1 FR 2178007B1
Authority
FR
France
Prior art keywords
layer
photoresist
pads
leads
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7310813A
Other languages
English (en)
Other versions
FR2178007A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of FR2178007A1 publication Critical patent/FR2178007A1/fr
Application granted granted Critical
Publication of FR2178007B1 publication Critical patent/FR2178007B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/1147—Manufacturing methods using a lift-off mask
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2924/00013—Fully indexed content
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01024—Chromium [Cr]
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    • H01L2924/01039—Yttrium [Y]
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    • H01L2924/01084—Polonium [Po]
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    • H01L2924/013—Alloys
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    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/014—Solder alloys
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR7310813A 1972-03-27 1973-03-26 Expired FR2178007B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00238116A US3821785A (en) 1972-03-27 1972-03-27 Semiconductor structure with bumps

Publications (2)

Publication Number Publication Date
FR2178007A1 FR2178007A1 (fr) 1973-11-09
FR2178007B1 true FR2178007B1 (fr) 1978-08-04

Family

ID=22896575

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7310813A Expired FR2178007B1 (fr) 1972-03-27 1973-03-26

Country Status (8)

Country Link
US (1) US3821785A (fr)
JP (1) JPS52670B2 (fr)
CA (1) CA984060A (fr)
DE (1) DE2314731C3 (fr)
FR (1) FR2178007B1 (fr)
GB (1) GB1377601A (fr)
IT (1) IT981659B (fr)
NL (1) NL7304183A (fr)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906541A (en) * 1974-03-29 1975-09-16 Gen Electric Field effect transistor devices and methods of making same
JPS5130673U (fr) * 1974-08-26 1976-03-05
US3959522A (en) * 1975-04-30 1976-05-25 Rca Corporation Method for forming an ohmic contact
JPS51147253A (en) * 1975-06-13 1976-12-17 Nec Corp Structure of electrode terminal
US4293637A (en) * 1977-05-31 1981-10-06 Matsushita Electric Industrial Co., Ltd. Method of making metal electrode of semiconductor device
US4438181A (en) 1981-01-13 1984-03-20 Jon M. Schroeder Electronic component bonding tape
DE3135007A1 (de) * 1981-09-04 1983-03-24 Licentia Gmbh Mehrschichtenkontakt fuer eine halbleiteranordnung
JPS59193036A (ja) * 1983-04-16 1984-11-01 Toshiba Corp 半導体装置の製造方法
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US4937006A (en) * 1988-07-29 1990-06-26 International Business Machines Corporation Method and apparatus for fluxless solder bonding
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
KR960016007B1 (ko) * 1993-02-08 1996-11-25 삼성전자 주식회사 반도체 칩 범프의 제조방법
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
US6428942B1 (en) * 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
US6214646B1 (en) * 2000-02-29 2001-04-10 Lucent Technologies Inc. Soldering optical subassemblies
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20040140219A1 (en) * 2003-01-21 2004-07-22 Texas Instruments Incorporated System and method for pulse current plating
DE102004024644A1 (de) * 2004-05-18 2005-12-22 Infineon Technologies Ag Verfahren zum Aufbringen metallischer Strukturen auf Substrate und Halbleiterbauelement
EP1779086A2 (fr) * 2004-08-10 2007-05-02 Dage precision Industries Ltd. Dispositif d'essai de cisaillement
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
TWI298204B (en) * 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same
JP5060494B2 (ja) * 2006-02-17 2012-10-31 デイジ プレシジョン インダストリーズ リミテッド せん断試験装置
DE102008042107A1 (de) * 2008-09-15 2010-03-18 Robert Bosch Gmbh Elektronisches Bauteil sowie Verfahren zu seiner Herstellung
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
KR102430984B1 (ko) * 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1196834A (en) * 1967-03-29 1970-07-01 Hitachi Ltd Improvement of Electrode Structure in a Semiconductor Device.
FR1569479A (fr) * 1967-07-13 1969-05-30

Also Published As

Publication number Publication date
DE2314731B2 (de) 1980-06-04
DE2314731C3 (de) 1982-10-14
JPS52670B2 (fr) 1977-01-10
IT981659B (it) 1974-10-10
CA984060A (en) 1976-02-17
DE2314731A1 (de) 1973-10-11
JPS499187A (fr) 1974-01-26
FR2178007A1 (fr) 1973-11-09
US3821785A (en) 1974-06-28
GB1377601A (en) 1974-12-18
NL7304183A (fr) 1973-10-01

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