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FR1517770A - Procédé pour la formation des contacts en série de composants semi-conducteurs - Google Patents

Procédé pour la formation des contacts en série de composants semi-conducteurs

Info

Publication number
FR1517770A
FR1517770A FR78008A FR78008A FR1517770A FR 1517770 A FR1517770 A FR 1517770A FR 78008 A FR78008 A FR 78008A FR 78008 A FR78008 A FR 78008A FR 1517770 A FR1517770 A FR 1517770A
Authority
FR
France
Prior art keywords
semiconductor components
serial contacts
forming serial
contacts
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR78008A
Other languages
English (en)
Inventor
Norbert Bock
Walter Klossika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Patentverwertungs GmbH
Original Assignee
Telefunken Patentverwertungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Patentverwertungs GmbH filed Critical Telefunken Patentverwertungs GmbH
Application granted granted Critical
Publication of FR1517770A publication Critical patent/FR1517770A/fr
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Lead Frames For Integrated Circuits (AREA)
FR78008A 1965-10-19 1966-09-28 Procédé pour la formation des contacts en série de composants semi-conducteurs Expired FR1517770A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DET0029608 1965-10-19

Publications (1)

Publication Number Publication Date
FR1517770A true FR1517770A (fr) 1968-03-22

Family

ID=7555010

Family Applications (1)

Application Number Title Priority Date Filing Date
FR78008A Expired FR1517770A (fr) 1965-10-19 1966-09-28 Procédé pour la formation des contacts en série de composants semi-conducteurs

Country Status (4)

Country Link
US (1) US3494024A (fr)
DE (1) DE1514883C3 (fr)
FR (1) FR1517770A (fr)
GB (1) GB1152735A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (fr) * 1979-12-28 1981-10-07 Fujitsu Limited Empaquetage du type à broches multiples pour élément de circuit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444619A (en) * 1966-05-16 1969-05-20 Robert B Lomerson Method of assembling leads in an apertured support
US3849880A (en) * 1969-12-12 1974-11-26 Communications Satellite Corp Solar cell array
US3698073A (en) * 1970-10-13 1972-10-17 Motorola Inc Contact bonding and packaging of integrated circuits
GB1559361A (en) * 1978-02-10 1980-01-16 Philips Electronic Associated Methods for manufacturing microminiature solid state devices devices manufactured by such methods and apparatus for use in such methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2804581A (en) * 1953-10-05 1957-08-27 Sarkes Tarzian Semiconductor device and method of manufacture thereof
US3021461A (en) * 1958-09-10 1962-02-13 Gen Electric Semiconductor device
US3159775A (en) * 1960-11-30 1964-12-01 Sylvania Electric Prod Semiconductor device and method of manufacture
US3030562A (en) * 1960-12-27 1962-04-17 Pacific Semiconductors Inc Micro-miniaturized transistor
US3264712A (en) * 1962-06-04 1966-08-09 Nippon Electric Co Semiconductor devices
US3256465A (en) * 1962-06-08 1966-06-14 Signetics Corp Semiconductor device assembly with true metallurgical bonds
US3360852A (en) * 1964-05-08 1968-01-02 Frenchtown Porcelain Company Manufacture of ceramic bases

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (fr) * 1979-12-28 1981-10-07 Fujitsu Limited Empaquetage du type à broches multiples pour élément de circuit

Also Published As

Publication number Publication date
US3494024A (en) 1970-02-10
DE1514883B2 (de) 1974-07-11
DE1514883A1 (de) 1970-01-08
DE1514883C3 (de) 1975-02-27
GB1152735A (en) 1969-05-21

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