FI84954C - Device for receiving digital data - Google Patents

Description

1 84954

Arrangement for receiving digital data

The present invention is directed to a digital data receiving arrangement that adapts to channel variations in a transmission system, comprising an adaptive receiver stage comprising an adaptive equalizer and at least one sampler, the adaptive receiver stage producing complex samples at a certain frequency from a signal x (t) to input the detected complex symbols, and to determine the optimal sampling time of the adaptive resuscitation circuit by minimizing the quadratic function J representing the difference between y and ak, and to produce a primary clock signal of the oscillator.

The performance of high speed digital transmission systems that use an adaptive equalizer at the receiving end with coefficient taps spaced one symbol apart to compensate for linear distortions in the channel depends very much on the sampling time. Poor sampling moment selection can lead to a zero spectrum near the edge of the spectral band of the sampled signal, in which case channel equalization becomes difficult.

Adaptive equalizers typically use the criterion of least squares error for channel adaptation. The sampling moment is selected in the equalizer output while minimizing the square function J, which can preferably also be the root mean square error.

An adaptive uniform structure for high-speed transmission systems is presented in H. Kobayashi,

Simultaneous Adaptive Estimation and Decision Algorithm for Carrier Modulated Data Transmission Systems ", IEEE Transactions on Communication Technology, Vol. COM'19, No. 3, pages 268-280, June 1971.

35 The article presents a receiver structure in which the 'Ai 2 84954 frequency and carrier setting, and also the digital equalizer adjustment, is implemented using the criterion of the least squares error. In this structure, the signal is first demodulated, then sampled, and finally processed by an adaptive equalizer. However, in order to implement the frequency setting guaranteeing the optimal sampling phase in the receiver structure presented by H. Kobayashi, the sampling signal x (t) is first derived and then processed in parallel with the main path according to the same principles using a second sampler and a second adaptive equalizer with identical adaptive characteristics. with the features of the main leveler. The output of the frequency setting loop therefore uses a correlation circuit to minimize the function of the selected root mean square error and to intervene in the phase of 15 sampling times.

In the real situation, it has been found difficult to utilize this structure because in practice it means doubling the complexity of the receiver.

U.S. Patent No. 3,868,603 discloses an adaptive equalizer that uses timing resuscitation to minimize standard deviation error. This patent mentions the characteristic features set forth in H. Kobayashi's article and discloses a modification aimed at reducing the hardware used. As a result, one equal equalizer is used instead of two, and this single equalizer is made to operate at a rate twice the symbol rate.

It is an object of the present invention to implement the frequency setting without doubling the complexity of the circuit, and without performing the calculation of the derivative signal of x (t) and the subsequent processing.

The invention as defined in the introduction is thus characterized in that the adaptive receiving arrangement comprises an adaptive frequency setting circuit comprising: 35 means for modulating a primary clock signal according to a secondary clock, the period being twice the primary clock period and having successive rising edges separated in time by TA. and T2, said secondary clock alternately producing two sampling times τ and 5 τ + Δτ, where r is the sampling time of the primary clock and At is constant, to approximate the quadratic function J of the device and the sign of its variations between times r and Δτ, and 10 according to the sign of the variations of the quadratic function J.

The receiving arrangement of the data transmission system comprises a demodulator producing a baseband signal x (t). Once the sampler and adaptive equalizer have processed the receiver stage, this signal is obtained from samples yk, which are usually complex. These samples yk are then fed to a decision circuit which inputs the expressed symbols ak. But depending on the time of sampling, the error 20 in determining the indicated symbols ak may be significant. To reduce this error, the function J is chosen, which represents the difference between the samples yk and the symbols ak. The gradient of this function J with respect to the sampling moment τ is determined, i.e. dJ / dr, and this gradient is minimized by influencing the sampling moment.

25 The first quadratic function J is, for example, the root mean square error (1) J = E {| ej2} 30 such that ek = yk - ak, where the symbol | . | represents an absolute value (modulus) and the symbol E {.} represents the mean.

To minimize J, a stochastic version of the gradient algorithm is used.

The gradient of J 35 4 84954 θΕ {| ej2} (2) g = - 3τ 5 is not available, but its non-directed estimate is | ej (rk + Ar) | 2 - 1 ^ (7 ^) | 2 ( 3) §k = -

At 10 where At represents a small difference, and where Tk and when | Tk-rk_11 «At, are two corresponding successive sampling times of the primary clock, the former being derived from the latter by the ratio (7) described below.

15 From this gradient estimate we obtain a continuous function g (t), which is defined by the expression: (4) g (t) = Sgn (§k) if t E | kT, (k + l) T | 20 where T is the symbol of the transfer duration and Sgn (.) Denotes the sign function.

In reality, the function Sgn (.) Is presented to simplify the implementation and does not constitute any limitation on the invention. The signal g (t), after being filtered by a low-pass filter, controls the oscillator producing the primary clock.

The output of the low-pass filter is E (t) = f (t) * g (t), where f (t) denotes the impulse response of the filter and the asterisk denotes the convolution operation. When no filtering is performed, the equation is simplified to the form: E (t) = g (t).

In practice, a bandpass filter is used to provide a better compromise between performance during the data collection period and sleep mode. This filter, referred to as a loop filter, belongs to a conventional class of filters used in phase-locked loops known to those skilled in the art.

The signal E (t) controls the oscillator producing the primary clock, the phase 0 (t) of which changes according to the following relationship: 5 (5) 0 (t) = -K.E (t) where K is the gain constant of the oscillator.

During the 10th symbol period of the primary clock produced by this oscillator, the phase variation is obtained as:

(K + l) T

(6) (¾ = -K E (t) .dt 15

kT

In practice, this change is to Ar.

Thus, two consecutive moments Tk + 1 and rk are connected by a ratio of 20

(K + l) T

(7) Tw + l * Tk "K e * dt

25 kT

The second quadratic function J is, for example, (8) J = E {fk2} 30 where fk = | yk | 2 - | \ | 2 with the same notations as above. In the same way as the relation (3) gives the ratio: f \ <Tk + Δτ) - f2k_l <rk-l> 35 (9) g m - Δτ

The ratio 6 84954 (7) connecting the successive moments rk + 1 and rk can be used by substituting the ratio (9) with respect to (4) for the term gk ·

According to the invention, the sampling operation is performed in two consecutive sampling moments, the purpose of which is to cause the occurrence of a substantially constant time difference + Δτ - Tj ^ αΔτ in successive sampling operations. Thus, at times rk-1 and rR + Δτ, successive errors e occur for their first squares as a function. and e4 or 10 fJt_1 and fk according to another quadratic function, which makes it possible to determine successive sampling times using ratio (7) and ratio (3) or (9), respectively. This is done by correcting the phase of the primary clock with a signal that depends on the character of the expressions (3) or (9). The primary clock thus corrected is then given the correct shape to produce a secondary clock that controls the operation of the sampler.

In the first embodiment of the adaptive receiver arrangement, the secondary clock controls a sampler followed by a digital adaptive equalizer 2o.

In another embodiment of the invention, the secondary clock of the device controls a sampler preceded by an analog adaptive equalizer.

In a third embodiment, the secondary clock signal is divided into two time-shifted clock signals that control two samplers preceded by an analog adaptive equalizer.

The present invention will become more fully apparent from the following exemplary description with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of an adaptive receiver arrangement according to the invention; Figure 2 shows a diagram of clock signal sequences; Fig. 3 shows a cocoa diagram of the secondary clock generating circuit loh-35; 7,84954 Fig. 4 is a block diagram of an embodiment of a primary clock phase correction device; Fig. 5 shows a block diagram of an embodiment of a device for determining the sign of variations of a quadratic function J, when only the real part e'k of ek is taken into account and when the real parts are positive during successive moments; Fig. 6 shows a block diagram of an embodiment of an adaptive receiver stage in the case of a digital adaptive equalizer; Fig. 7 shows a block diagram of an embodiment of an adaptive receiver stage in the case of an analog adaptive equalizer; Fig. 8 shows a block diagram of an adaptive receiver arrangement in the case of an analog adaptive equalizer 15 when the secondary clock is divided into two time-shifted signals.

Figure 1 shows an adaptive receiver arrangement according to a preferred embodiment of the invention in the case where digital processing is performed. The basic signal x (t), which may be a complex signal, is applied to an adaptive receiver stage 11 followed by a decision circuit 14. The adaptive frequency setting circuit 12 determines the operating frequency of the adaptive receiver stage 11 from the samples yR and the detected symbols ak. In this preferred embodiment, the adaptive receiver stage 11 consists, as shown in Figure 6, of a sampler 111, which is then an analog-to-digital converter followed by a digital adaptive equalizer 112. The adaptive receiver stage 11 (Figure 1) produces samples yk which may be complex. Using the decision circuit 14, these samples produce the expressed symbols ak. The decision operation results in errors between the sample strings yk and the ak strings of the expressed symbols. Then the difference between the strings yk and the strings afc is determined, and the ne-35 superficial function J of this difference is calculated, determining the sign of its successive subsequent variations e 84954 thereafter. The calculator 13 receives the queues yk and ak and determines the sign of the variations of the function J in the first calculator 131 and then the second calculator 132. Depending on the sign of these variations, the correction device 123 produces a correction signal which affects the oscillator 122. The latter via the interface 124 to the adaptive receiver stage 11 and also to the processing device 121 which produces the secondary coil.

Figure 2 shows clock signal sequences illustrating an example of a mechanism that generates a secondary clock from a primary clock. Figure 3 shows an example of a block diagram by which clock signals are generated. The primary clock (interface 124, clock-1010 H1) is delayed in the delay element 62 to produce a clock H2 for its output 66. The selection arrangement 63 alternately removes one of the two cycles of each clock to produce clock signals H3 and H4 to the respective outputs 67 and 68. These clock signals are combined 64 then to form 20 secondary clocks (clock H5, interface 125) having a period twice the primary clock period and having successively rising edges separated by time Τχ and T2, said secondary clock producing two sampling moments τ and τ + Δτ. This is the same as sa-25 would mean that with respect to the constant period T of the primary clock (clock H1), the period would exceed it by Δτ, and that the period T2 would be shorter by the same value.

In the case where the quadratic function J is defined by the ratios (1) or (8), the calculator 13 consists of a static memory stored in advance of the sign values of the variations of the quadratic function stored for all pairs of predictable complex values yk and ak, the memory being read by complex values of yfc and ak by indicating.

35 However, in the case where the function J is determined o

^ V

With ratio 9 (8), it is equally possible that the first calculator comprises a subtractor which performs the calculation ek = yk - afc and a squaring circuit, for example a multiplier. It is also possible to include only the real part of ek, denoted by e'k, for the function J when this part is positive. In this second case, the sign of the variations of the function J is determined in the second calculating device 132. This is, for example, the calculating device defined in Fig. 5. For this purpose, the information from the first calculation device 131 is input to the delay element 50 and input to the input of the comparator 51. The second input of comparator 51 directly receives the output of the first calculator 131. Thus, the inputs of the comparator 51 receive simultaneously the delayed information e'^ j and the subsequent delayed information e'k. The comparator has two outputs that enter the active state when e'k-1 <e'k or e'k> ek, respectively. The active or inactive states of these outputs are stored in two memory elements 52, 53, which are allowed by the clock signal H6 obtained only by validating the rising edges of the clock signal H3 when the respective characters of e'k and e / k_1 are both positive. This is performed in the eligibility element 57. The outputs 54 and 55 of these memory elements act on the primary clock correction device 123. This correction device, as shown in Figure 4, consists of, for example, an operational amplifier 60 followed by a low-pass filter 61. The operational amplifier 60 is of the type LFNET . The characteristics of the low-pass filter 61 are determined to define the pull-inM range and limit the phase noise of the oscillator 30. The correction affects the oscillator 122, which is, for example, an oscillator of type MC 1648, manufactured by MOTOROLA, which feeds its dose 124 to the primary clock H1 at a frequency of, for example, 35 MHz.

'Sv. In another embodiment, the adaptive receiver stage 11 consists, as shown in Figure 7, of an analog adaptive equalizer 115 followed by a sampler.

In the third embodiment, as shown in Figure 8, the adaptive receiver stage 11 consists of an analog adaptive equalizer 115 followed by a first sampler 116 in one channel and a second sampler 113 in the other channel. All elements identical to those shown in Figure 3 are given the same reference numbers. The device 121 for modifying the primary clock 10 has in this case been reduced to only one delay element 62 in Fig. 3. The sampling clock signals are then the clock signals H1 and H2 shown in Fig. 2, which appear at connections 124 and 66 in Fig. 3. These sampling signals each control respective samplers. 113 and 116. All other functional principles are similar to those described in connection with the first embodiment. The error eak (erk, respectively) is the difference between the sample in the output of sampler 113 (or 116, respectively) and the 20 symbols defined at time k.

l!

Claims (6)

11 84954 A digital data receiving arrangement adapted to channel variations of a transmission system, comprising an adaptive receiver stage (lii) comprising an adaptive equalizer (112,113) and at least one sampler (113,116), the adaptive receiver stage producing complex samples at a certain frequency from the yk sampling signal x (t), a decision circuit (14) for supplying the detected complex symbols ak, and an adaptive timing resuscitation circuit (12) for determining the optimal sampling time by minimizing the quadratic function J representing the difference between y and ak, and an oscillator (122) for generating a primary clock signal, characterized by that the adaptive frequency setting circuit (12) comprises: - means (121) for modifying the primary clock signal according to a secondary clock signal, the period of which is twice the period of the primary clock signal and whose successive rising edges are temporally separated by T1 and T2 , said secondary clock alternating between two sampling times τ and τ + Δτ, where τ is the sampling time of the primary clock signal and Δτ is constant, - a device which approximates (132) the quadratic function J and its sign of variations (131) between 25 moments τ and τ + Δτ , and - a device for correcting the phase of the primary clock signal (123) according to the sign of the variations of the quadratic function J. Adaptive receiver arrangement according to Claim 1, characterized in that the device (13) for calculating the sign of the square function J and its variations consists of a static memory in which the sign of the variations of the square function J is calculated in advance. The known values are stored for all pairs of complex values yk and ak seen above, the memory being readable by indicating the complex values determined by i2 84954 yk and ak. The adaptive receiver arrangement according to claim 1, in which the quadratic function J is the root mean square of the error ek = yk - ak J = E {jekj}, where | ekj denotes the absolute value of ek and the symbol E {.} Averages, and in the case wherein the changes in J are determined from the real part of ek and only at moments when the real part is positive for two consecutive moments, characterized in that the device (13) for calculating the quadratic function J and the sign of its variations comprises: - a subtractor receiving complex samples at its inputs and the detected symbols ak and outputs ek = - ak, - an error element e (50) for the real part e'k 15 of the delay element (50) to produce a delay of one cycle of the primary clock signal, - delayed path errors e'j ^ and straight path errors of the comparator (51) e'k to receive simultaneously, and two memory elements (52,53) for e'j ^ and e in the control of the eligibility element. 'k to store the result of the comparison, - a validity element (57) which only validates the clock signal derived from the primary clock signal by eliminating one period from the two periods when the values of e'j ^ rn 25 and e'k are both positive. Adaptive receiver arrangement according to one of Claims 1 to 3, characterized in that the secondary clock signal controls a sampler (111) consisting of an analog-to-digital converter followed by a digital adaptive equalizer (112). Adaptive receiver arrangement according to one of Claims 1 to 3, characterized in that the secondary clock signal controls a sampler (111) which is preceded by an analog adaptive equalizer (115). li i3 84954 Adaptive receiver arrangement according to one of Claims 1 to 3, characterized in that the secondary clock signal is divided into two time-shifted clock signals which control two samplers (113, 116) preceded by an analog adaptive equalizer (115). \ i4 84954