FI813266L - Minnesstyrenhet med parallellbehandlade koeer - Google Patents

Minnesstyrenhet med parallellbehandlade koeer

Info

Publication number: FI813266L
Authority: FI; Finland
Prior art keywords: parallellbehandlade; minnesstyrenhet; koeer; med; parallellbehandlade koeer
Prior art date: 1980-10-31

Application number

FI813266A

Other languages

English (en)

Other versions

FI77124C (fi

FI77124B (fi

Inventor

Robert B Johnson

Jr Chester M Nibby

Original Assignee

Honeywell Inf Systems

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1980-10-31

Filing date

1981-10-19

Publication date

1982-05-01

1981-10-19 Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems

1982-05-01 Publication of FI813266L publication Critical patent/FI813266L/fi

1988-09-30 Application granted granted Critical

1988-09-30 Publication of FI77124B publication Critical patent/FI77124B/fi

1989-01-10 Publication of FI77124C publication Critical patent/FI77124C/fi

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Computer Networks & Wireless Communication (AREA)
Spectroscopy & Molecular Physics (AREA)
Signal Processing (AREA)
Dram (AREA)
Bus Control (AREA)
Memory System (AREA)
Techniques For Improving Reliability Of Storages (AREA)
Multi Processors (AREA)

FI813266A 1980-10-31 1981-10-19 Minnesstyrenhet med parallellbehandlade koeer. FI77124C (fi)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US06/202,821 US4451880A (en)	1980-10-31	1980-10-31	Memory controller with interleaved queuing apparatus
US20282180		1980-10-31

Publications (3)

Publication Number	Publication Date
FI813266L true FI813266L (fi)	1982-05-01
FI77124B FI77124B (fi)	1988-09-30
FI77124C FI77124C (fi)	1989-01-10

Family

ID=22751401

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
FI813266A FI77124C (fi)	1980-10-31	1981-10-19	Minnesstyrenhet med parallellbehandlade koeer.

Country Status (12)

Country	Link
US (1)	US4451880A (fi)
EP (1)	EP0051426A1 (fi)
JP (1)	JPS57120164A (fi)
KR (1)	KR860000986B1 (fi)
AU (1)	AU551810B2 (fi)
BR (1)	BR8106954A (fi)
CA (1)	CA1172771A (fi)
ES (1)	ES8303746A1 (fi)
FI (1)	FI77124C (fi)
MX (1)	MX151385A (fi)
PH (1)	PH18137A (fi)
YU (1)	YU43047B (fi)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4558429A (en) *	1981-12-17	1985-12-10	Honeywell Information Systems Inc.	Pause apparatus for a memory controller with interleaved queuing apparatus
JPS6025853A (ja) *	1983-07-22	1985-02-08	Nippon Seiko Kk	電気式動力舵取装置
JPS6025854A (ja) *	1983-07-22	1985-02-08	Nippon Seiko Kk	電気式動力舵取装置
CA1221464A (en) *	1983-12-26	1987-05-05	Hidehiko Nishida	Data processor system having improved data throughput of multiprocessor system
JPH0331665Y2 (fi) *	1984-09-05	1991-07-04
CA1286412C (en) *	1986-01-29	1991-07-16	Digital Equipment Corporation	Apparatus and method for providing distributed control in a main memory unit of a data processing system
US4937770A (en) *	1986-02-07	1990-06-26	Teradyne, Inc.	Simulation system
US5327542A (en) *	1987-09-30	1994-07-05	Mitsubishi Denki Kabushiki Kaisha	Data processor implementing a two's complement addressing technique
US5471637A (en) *	1988-12-30	1995-11-28	Intel Corporation	Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
US5363486A (en) *	1989-11-13	1994-11-08	Zenith Data Systems Corporation	Variable size queue circuit for buffering data transfers from a processor to a memory
US6807609B1 (en) *	1989-12-04	2004-10-19	Hewlett-Packard Development Company, L.P.	Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
US5265229A (en) *	1990-07-02	1993-11-23	Digital Equipment Corporation	Single load, multiple issue queue with error recovery capability
CA2051222C (en) *	1990-11-30	1998-05-05	Pradeep S. Sindhu	Consistent packet switched memory bus for shared memory multiprocessors
GB2272315B (en) *	1991-07-02	1995-10-04	Intel Corp	Asynchronous modular bus architecture with burst capability
FR2695227B1 (fr) *	1992-09-02	1994-10-14	Aton Systemes	Procédé pour le transfert entrelacé des données entre la mémoire d'un ordinateur et un équipement périphérique constitué d'un système de gestion et de plusieurs unités de stockage.
DE19503022A1 (de) *	1994-04-08	1995-10-12	Hewlett Packard Co	Master/Slave-Buskonfiguration für schnelle erweiterbare Speichersysteme
US6295586B1 (en)	1998-12-04	2001-09-25	Advanced Micro Devices, Inc.	Queue based memory controller
US6557090B2 (en) *	2001-03-09	2003-04-29	Micron Technology, Inc.	Column address path circuit and method for memory devices having a burst access mode
US20040054864A1 (en) *	2002-09-13	2004-03-18	Jameson Neil Andrew	Memory controller
US7461218B2 (en) *	2005-06-29	2008-12-02	Intel Corporation	Size-based interleaving in a packet-based link
JP5507079B2 (ja)	2006-04-28	2014-05-28	旭化成ケミカルズ株式会社	気体分離膜
US9268720B2 (en)	2010-08-31	2016-02-23	Qualcomm Incorporated	Load balancing scheme in multiple channel DRAM systems
US20240212743A1 (en) *	2021-04-21	2024-06-27	Rambus, Inc.	Integrated circuit memory devices with unidirectional ports for concurrent interface operations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3735354A (en) *	1972-04-07	1973-05-22	Sperry Rand Corp	Multiplexed memory request interface
US3961312A (en) *	1974-07-15	1976-06-01	International Business Machines Corporation	Cycle interleaving during burst mode operation
US4000485A (en) *	1975-06-30	1976-12-28	Honeywell Information Systems, Inc.	Data processing system providing locked operation of shared resources
US4151598A (en) *	1978-03-27	1979-04-24	Honeywell Information Systems Inc.	Priority assignment apparatus for use in a memory controller
US4281381A (en) *	1979-05-14	1981-07-28	Bell Telephone Laboratories, Incorporated	Distributed first-come first-served bus allocation apparatus

1980
- 1980-10-31 US US06/202,821 patent/US4451880A/en not_active Expired - Lifetime
1981
- 1981-10-19 FI FI813266A patent/FI77124C/fi not_active IP Right Cessation
- 1981-10-19 PH PH26360A patent/PH18137A/en unknown
- 1981-10-26 ES ES506564A patent/ES8303746A1/es not_active Expired
- 1981-10-27 BR BR8106954A patent/BR8106954A/pt not_active IP Right Cessation
- 1981-10-27 EP EP81305073A patent/EP0051426A1/en not_active Withdrawn
- 1981-10-28 AU AU76903/81A patent/AU551810B2/en not_active Ceased
- 1981-10-30 JP JP56173176A patent/JPS57120164A/ja active Granted
- 1981-10-30 YU YU2580/81A patent/YU43047B/xx unknown
- 1981-10-30 MX MX189901A patent/MX151385A/es unknown
- 1981-10-30 CA CA000389098A patent/CA1172771A/en not_active Expired
- 1981-10-31 KR KR1019810004189A patent/KR860000986B1/ko active IP Right Grant

Also Published As

Publication number	Publication date
ES506564A0 (es)	1983-02-01
US4451880A (en)	1984-05-29
BR8106954A (pt)	1982-07-13
EP0051426A1 (en)	1982-05-12
FI77124C (fi)	1989-01-10
KR830008242A (ko)	1983-11-16
AU551810B2 (en)	1986-05-15
CA1172771A (en)	1984-08-14
YU43047B (en)	1989-02-28
JPH039495B2 (fi)	1991-02-08
FI77124B (fi)	1988-09-30
MX151385A (es)	1984-11-13
AU7690381A (en)	1982-05-06
ES8303746A1 (es)	1983-02-01
YU258081A (en)	1983-12-31
PH18137A (en)	1985-04-03
KR860000986B1 (ko)	1986-07-24
JPS57120164A (en)	1982-07-27

Publication	Publication Date	Title
FI811194L (fi)	1981-10-24	Kommunikationssystem med en informationssystem med en informationsbuss
FI810875L (fi)	1981-09-25	Torkvira med laog genomtraenglighet
FI813309L (fi)	1982-04-30	Med inline-elektronkanon foersett faergbildroer
FI812808L (fi)	1982-03-13	Fenylpiperazinderivat med antiagressiv aktivitet
FI812175L (fi)	1982-01-11	Softsteroider med antiinflammationsverkan
FI810151L (fi)	1981-07-22	Med upprivbar oeppningsanording foersedd foerpackningsbehaollare
FI810752L (fi)	1981-09-13	Sammalfoerpackning med foerpackningen omslutande handtag
FI813266L (fi)	1982-05-01	Minnesstyrenhet med parallellbehandlade koeer
FI812365L (fi)	1982-02-05	Foer televisionsmottagare avsedd mottakteffektkaella synkroniserad med horisontalavlaenkningen
FI810630L (fi)	1981-08-30	Stoedelement med boejlig huvuddel
FI804045L (fi)	1981-07-03	Elektrostatisk faergsprutpistol med rotationsspridare
FI811069L (fi)	1981-10-11	Med en lyftanordning foersedd toemningskorg foer en varmpress
FI813237L (fi)	1982-04-24	Lastvaexlare med stoedarm
FI812051L (fi)	1982-01-08	Avlaenkningskrets med korrigerad rasterdistorsion
FI811296L (fi)	1981-10-29	Vaetskebehaollare med sugroersoeppningsdon
FI810269L (fi)	1981-08-02	Blixtlaos med aendstoppare
FI812364L (fi)	1982-02-05	Avboejningskrets med linearitetskorrigering
FI812744L (fi)	1982-03-06	Etanolframstaellning med hoegeffektiv bakteriodling
FI812639L (fi)	1982-03-30	Kommunikationsmultiplexer med duppelmikroprocessor
FI803726L (fi)	1981-12-21	Vaog foersedd med en vibrerande straeng
FI812275L (fi)	1982-01-23	Oevervakningsanordning foer en pcm-regenerator med en felproevare foer kodregleringen
FI810740L (fi)	1981-09-18	Foerstaerkaranordning med laogpasskarakteristika
FI812154L (fi)	1982-01-16	Behaollare med saekerhetslaos
FI813990L (fi)	1982-06-18	Detergentblandningar med reglerbara skumningsegenskaper
FI811188L (fi)	1981-10-24	Foerstaerkningsreglerad foerstaerkare med variabel emitterdegeneration

Legal Events

Date	Code	Title	Description
1995-05-15	MM	Patent lapsed
2004-08-31	MM	Patent lapsed	Owner name: HONEYWELL INFORMATION SYSTEMS INC.