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ES8407606A1 - Transmitter-data receiver system between a computer and a telegraph line. (Machine-translation by Google Translate, not legally binding) - Google Patents

Transmitter-data receiver system between a computer and a telegraph line. (Machine-translation by Google Translate, not legally binding)

Info

Publication number
ES8407606A1
ES8407606A1 ES527267A ES527267A ES8407606A1 ES 8407606 A1 ES8407606 A1 ES 8407606A1 ES 527267 A ES527267 A ES 527267A ES 527267 A ES527267 A ES 527267A ES 8407606 A1 ES8407606 A1 ES 8407606A1
Authority
ES
Spain
Prior art keywords
translation
transmitter
computer
machine
legally binding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES527267A
Other languages
Spanish (es)
Other versions
ES527267A0 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to ES527267A priority Critical patent/ES527267A0/en
Publication of ES8407606A1 publication Critical patent/ES8407606A1/en
Publication of ES527267A0 publication Critical patent/ES527267A0/en
Granted legal-status Critical Current

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  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

Transmitter-data receiver system that allows to transmit data in the form of messages, prepared in a computer, a telegraph or telex network, as well as receiving and decoding adequately the messages received by this line.comprend a first and a second circuit conversion of parallel series information (uart), being the first circuit given of a serial entry that receives from the ordered binary-serial signals, which include information bits and line control bits. (Machine-translation by Google Translate, not legally binding)
ES527267A 1983-11-03 1983-11-03 DATA TRANSMITTER-RECEIVER SYSTEM BETWEEN A COMPUTER AND A TELEGRAPHIC LINES Granted ES527267A0 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES527267A ES527267A0 (en) 1983-11-03 1983-11-03 DATA TRANSMITTER-RECEIVER SYSTEM BETWEEN A COMPUTER AND A TELEGRAPHIC LINES

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES527267A ES527267A0 (en) 1983-11-03 1983-11-03 DATA TRANSMITTER-RECEIVER SYSTEM BETWEEN A COMPUTER AND A TELEGRAPHIC LINES

Publications (2)

Publication Number Publication Date
ES8407606A1 true ES8407606A1 (en) 1984-09-16
ES527267A0 ES527267A0 (en) 1984-09-16

Family

ID=8486455

Family Applications (1)

Application Number Title Priority Date Filing Date
ES527267A Granted ES527267A0 (en) 1983-11-03 1983-11-03 DATA TRANSMITTER-RECEIVER SYSTEM BETWEEN A COMPUTER AND A TELEGRAPHIC LINES

Country Status (1)

Country Link
ES (1) ES527267A0 (en)

Also Published As

Publication number Publication date
ES527267A0 (en) 1984-09-16

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