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ES487251A1 - Un metodo para reducir al minimo el tiempo asociado al ope- rar un dispositivo de memoria de acceso directo - Google Patents

Un metodo para reducir al minimo el tiempo asociado al ope- rar un dispositivo de memoria de acceso directo

Info

Publication number
ES487251A1
ES487251A1 ES487251A ES487251A ES487251A1 ES 487251 A1 ES487251 A1 ES 487251A1 ES 487251 A ES487251 A ES 487251A ES 487251 A ES487251 A ES 487251A ES 487251 A1 ES487251 A1 ES 487251A1
Authority
ES
Spain
Prior art keywords
memory device
operating
direct access
time associated
access memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES487251A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES487251A1 publication Critical patent/ES487251A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un método para reducir al mínimo el tiempo asociado al operar un dispositivo de memoria de acceso directo en modo de desconexión de un canal en respuesta a órdenes de canal que se aplican a un dispositivo de control que interconecta el canal con el dispositivo de memoria, implicando algunas de dichas órdenes el movimiento mecánico del dispositivo de memoria, que comprende las operaciones de almacenar dentro de dicho dispositivo de control una primera orden que implica movimiento mecánico de dicho dispositivo de memoria, y, en respuesta a la siguiente orden que implica movimiento mecánico de dicho dispositivo de memoria, ejecutar dicha primera orden almacenada esencialmente en paralelo con dicha orden siguiente.
ES487251A 1978-12-28 1979-12-26 Un metodo para reducir al minimo el tiempo asociado al ope- rar un dispositivo de memoria de acceso directo Expired ES487251A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/973,827 US4310882A (en) 1978-12-28 1978-12-28 DAS Device command execution sequence

Publications (1)

Publication Number Publication Date
ES487251A1 true ES487251A1 (es) 1980-08-01

Family

ID=25521265

Family Applications (1)

Application Number Title Priority Date Filing Date
ES487251A Expired ES487251A1 (es) 1978-12-28 1979-12-26 Un metodo para reducir al minimo el tiempo asociado al ope- rar un dispositivo de memoria de acceso directo

Country Status (8)

Country Link
US (1) US4310882A (es)
EP (1) EP0017666B1 (es)
JP (1) JPS593787B2 (es)
AU (1) AU539004B2 (es)
BR (1) BR7908436A (es)
CA (1) CA1119311A (es)
DE (1) DE2965411D1 (es)
ES (1) ES487251A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413317A (en) * 1980-11-14 1983-11-01 Sperry Corporation Multiprocessor system with cache/disk subsystem with status routing for plural disk drives
US4423480A (en) * 1981-03-06 1983-12-27 International Business Machines Corporation Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations
JPS5878247A (ja) * 1981-11-02 1983-05-11 Nec Corp 磁気デイスク制御装置
US4638424A (en) * 1984-01-12 1987-01-20 International Business Machines Corporation Managing data storage devices connected to a digital computer
US5060142A (en) * 1988-05-20 1991-10-22 Menon Moothedath J System which matches a received sequence of channel commands to sequence defining rules for predictively optimizing peripheral subsystem operations
US4935828A (en) * 1988-06-30 1990-06-19 Wang Laboratories, Inc. Seek multitasking disk controller
JP2772482B2 (ja) * 1989-03-28 1998-07-02 株式会社 エス・デー 透視材及び透視材製ドア又は窓等の装飾方法
US5157770A (en) * 1990-08-31 1992-10-20 International Business Machines Corporation Nonsynchronous dasd control
JP3474646B2 (ja) * 1994-09-01 2003-12-08 富士通株式会社 入出力制御装置及び入出力制御方法
US6658535B1 (en) 2000-01-19 2003-12-02 International Business Machines Corporation Non-interfering seek behavior modification for improved hard drive performance
US8154385B2 (en) * 2005-08-31 2012-04-10 Impinj, Inc. Local processing of received RFID tag responses

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1449580A1 (de) * 1963-09-30 1970-01-15 Bunker Ramo Ziffernrechenmaschine
US3369221A (en) * 1964-05-04 1968-02-13 Honeywell Inc Information handling apparatus
US3480917A (en) * 1967-06-01 1969-11-25 Bell Telephone Labor Inc Arrangement for transferring between program sequences in a data processor
US3537072A (en) * 1967-06-19 1970-10-27 Burroughs Corp Instruction conversion system and apparatus
US3573743A (en) * 1968-09-30 1971-04-06 Sperry Rand Corp Programmable timing controls for magnetic memories
GB1310489A (en) * 1971-09-22 1973-03-21 Ibm Data handling systems
US3898623A (en) * 1973-06-05 1975-08-05 Ibm Suspension and restart of input/output operations
IT993428B (it) * 1973-09-26 1975-09-30 Honeywell Inf Systems Unita di controllo di calcolatore microprogrammato con microprogram mi residenti in memoria e sovrap posizioni delle fasi interpretati ve di una microistruzione con la fase esecutiva della precedente microistruzione
FR111576A (es) * 1973-12-13 1900-01-01
US3956739A (en) * 1974-03-06 1976-05-11 Ontel Corporation Data transfer system
US4099231A (en) * 1975-10-01 1978-07-04 Digital Equipment Corporation Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
US4092732A (en) * 1977-05-31 1978-05-30 International Business Machines Corporation System for recovering data stored in failed memory unit

Also Published As

Publication number Publication date
JPS593787B2 (ja) 1984-01-26
DE2965411D1 (en) 1983-06-16
AU539004B2 (en) 1984-09-06
AU5353479A (en) 1980-07-03
BR7908436A (pt) 1980-09-23
EP0017666B1 (en) 1983-05-11
EP0017666A2 (en) 1980-10-29
JPS5591051A (en) 1980-07-10
EP0017666A3 (en) 1981-01-07
US4310882A (en) 1982-01-12
CA1119311A (en) 1982-03-02

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970203