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ES473212A1 - Procedimiento y dispositivo para el control de las etapas deentrada de una transmision de datos por modulacion de impul-sos codificados - Google Patents

Procedimiento y dispositivo para el control de las etapas deentrada de una transmision de datos por modulacion de impul-sos codificados

Info

Publication number
ES473212A1
ES473212A1 ES473212A ES473212A ES473212A1 ES 473212 A1 ES473212 A1 ES 473212A1 ES 473212 A ES473212 A ES 473212A ES 473212 A ES473212 A ES 473212A ES 473212 A1 ES473212 A1 ES 473212A1
Authority
ES
Spain
Prior art keywords
received
pulse
monitoring
time zone
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES473212A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Patelhold Patenverwertungs and Elektro-Holding AG
Original Assignee
Patelhold Patenverwertungs and Elektro-Holding AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Patelhold Patenverwertungs and Elektro-Holding AG filed Critical Patelhold Patenverwertungs and Elektro-Holding AG
Publication of ES473212A1 publication Critical patent/ES473212A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/248—Distortion measuring systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/493—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Nonlinear Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Numerical Control (AREA)

Abstract

Procedimiento y dispositivo para el control de las etapas de entrada de una transmisión de datos por modulación de impulsos codificados, en relación a un campo de tolerancia de distorsión de etapa predeterminable, procedimiento caracterizado porque el campo de distorsión de las etapas de recepción del mensaje por modulación de impulsos codificados, se subdivide en dos zonas sucesivas, porque en la primera zona de tiempo que se extiende alrededor del instante teórico del flanco de etapa esperado del telegrama de recepción se controla si como máximo entra en el flanco de etapa, porque al entrar mas de un flanco se establece una característica de reconocimiento de erros, y porque se establece las mismas características de reconocimiento de error cuando en la segunda zona de tiempo complementaria entra también solo un flanco de etapa.
ES473212A 1977-09-13 1978-09-08 Procedimiento y dispositivo para el control de las etapas deentrada de una transmision de datos por modulacion de impul-sos codificados Expired ES473212A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1114677A CH622392A5 (es) 1977-09-13 1977-09-13

Publications (1)

Publication Number Publication Date
ES473212A1 true ES473212A1 (es) 1979-03-16

Family

ID=4370530

Family Applications (1)

Application Number Title Priority Date Filing Date
ES473212A Expired ES473212A1 (es) 1977-09-13 1978-09-08 Procedimiento y dispositivo para el control de las etapas deentrada de una transmision de datos por modulacion de impul-sos codificados

Country Status (10)

Country Link
US (1) US4213007A (es)
AT (1) ATA436878A (es)
CH (1) CH622392A5 (es)
DE (1) DE2748782A1 (es)
DK (1) DK398378A (es)
ES (1) ES473212A1 (es)
FI (1) FI782761A (es)
IN (1) IN149464B (es)
NO (1) NO150620C (es)
SE (1) SE439866B (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2049958B (en) * 1979-03-15 1983-11-30 Nippon Electric Co Integrated logic circuit adapted to performance tests
DE2924922A1 (de) * 1979-06-20 1981-01-22 Siemens Ag Verfahren und schaltungsanordnung zur taktsynchronisierung bei der uebertragung von digitalen nachrichtensignalen
EP0236818B1 (de) * 1986-03-14 1992-04-29 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zum Überwachen von mit einer Datenvermittlungs- bzw. Datenübertragungseinrichtung verbundenen Anschlussleitungen
US5341403A (en) * 1992-01-27 1994-08-23 Analog Devices, Incorporated Means to avoid data distortion in clock-synchronized signal sampling
US5301207A (en) * 1992-04-03 1994-04-05 Integrated Network Corporation Test apparatus and process for digital data service system
DE19606909A1 (de) * 1996-02-19 1997-08-21 Hartmann & Braun Ag Verfahren zur empfangsseitigen Störsignalunterdrückung an offenen seriellen Lichtwellenleiterschnittstellen
US8260636B2 (en) * 2007-08-31 2012-09-04 Caterpillar Inc. Method and system for prioritizing communication of a health risk

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3562710A (en) * 1968-04-24 1971-02-09 Ball Brothers Res Corp Bit error detector for digital communication system
US3546588A (en) * 1968-09-17 1970-12-08 Bell Telephone Labor Inc Phase hit monitor-counter
US3771059A (en) * 1972-03-27 1973-11-06 Rca Corp Universal data quality monitor
US3851101A (en) * 1974-03-04 1974-11-26 Motorola Inc Adaptive phase synchronizer
DE2435621B2 (de) * 1974-07-24 1978-02-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erkennung von uebertragungsfehlern beim empfang von isochron binaer modulierten daten

Also Published As

Publication number Publication date
SE439866B (sv) 1985-07-01
SE7809489L (sv) 1979-03-14
ATA436878A (de) 1985-04-15
NO783059L (no) 1979-03-14
FI782761A (fi) 1979-03-14
DK398378A (da) 1979-03-14
US4213007A (en) 1980-07-15
DE2748782A1 (de) 1979-03-22
NO150620B (no) 1984-08-06
NO150620C (no) 1984-11-14
IN149464B (es) 1981-12-19
CH622392A5 (es) 1981-03-31

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19990503