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ES470190A1 - Un circuito para la extraccion de temporizacion - Google Patents

Un circuito para la extraccion de temporizacion

Info

Publication number
ES470190A1
ES470190A1 ES470190A ES470190A ES470190A1 ES 470190 A1 ES470190 A1 ES 470190A1 ES 470190 A ES470190 A ES 470190A ES 470190 A ES470190 A ES 470190A ES 470190 A1 ES470190 A1 ES 470190A1
Authority
ES
Spain
Prior art keywords
input
waveform
output
waveforms
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES470190A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES470190A1 publication Critical patent/ES470190A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/007—Circuits for comparing the phase or frequency of two mutually-independent oscillations by analog multiplication of the oscillations or by performing a similar analog operation on the oscillations
    • H03D13/008—Circuits for comparing the phase or frequency of two mutually-independent oscillations by analog multiplication of the oscillations or by performing a similar analog operation on the oscillations using transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0009—Emitter or source coupled transistor pairs or long tail pairs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)

Abstract

Un circuito para la extracción de temporización, para extraer una onda de impulsos de reloj de una onda de impulsos de entrada, incluyendo dicho circuito un bucle sincronizado en fase con un comparador de fase que tiene una primera entrada a la que se aplica dicha onda de impulsos de entrada, una segunda entrada y una salida que se acopla en cascada por lo menos con un oscilador controlado a tensión cuya salida se acopla a la segunda entrada mencionada de dicho comparador de fase, generándose dicha onda de impulsos de reloj a la salida del oscilador controlado a tensión, caracterizado porque dicho comparador de fase (43) incluye primeros elementos (47-58) controlados por dicha onda de impulsos de entrada (i) y por dicha onda de impulsos de reloj (CPW), teniendo transiciones que tienen lugar sustancialmente en el centro de los impulsos de dicha onda de impulsos de entrada (i) y pueden proporcionar ondas de salida primera (i+) y segunda (i-) que son iguales a los valores de amplitud media delas ondas de impulsos intermedias primera (i+) y segunda(i-), cuyos impulsos están constituidos por porciones diferentes de los impulsos de dicha onda de impulsos de entrada (i) respectivamente y que son ambas proporcionales a la densidad de impulso (d) de dicha onda de impulsos de entrada (i), y porque dicho comparador de fase (43) incluye además segundos elementos (44) acoplados a los primeros elementos (47-58) y que proporcionan una señal de salida del comparador (v+ - v-) que es una función de la relación de las ondas de salida primera (i+) y segunda (i-).
ES470190A 1977-05-27 1978-05-24 Un circuito para la extraccion de temporizacion Expired ES470190A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7705842A NL7705842A (nl) 1977-05-27 1977-05-27 Inrichting voor het onttrekken van een klokpuls- reeks aan een ingangspulsreeks.

Publications (1)

Publication Number Publication Date
ES470190A1 true ES470190A1 (es) 1979-09-16

Family

ID=19828628

Family Applications (1)

Application Number Title Priority Date Filing Date
ES470190A Expired ES470190A1 (es) 1977-05-27 1978-05-24 Un circuito para la extraccion de temporizacion

Country Status (8)

Country Link
US (1) US4201948A (es)
AU (1) AU519278B2 (es)
BE (1) BE867506A (es)
CH (1) CH638358A5 (es)
DE (1) DE2821064A1 (es)
ES (1) ES470190A1 (es)
GB (1) GB1588955A (es)
NL (1) NL7705842A (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675883A (en) * 1984-10-04 1987-06-23 Siemens Aktiengesellschaft Arrangement for Carrier Recovery from Two Received Phase Shift Keyed Signals
US4851995A (en) * 1987-06-19 1989-07-25 International Business Machines Corporation Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
CH687773A5 (de) * 1994-10-12 1997-02-14 Emil Peter Verbundkonstruktion, insbesondere Bruecke.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3821658A (en) * 1973-04-26 1974-06-28 Signetics Corp Phase locked loop with memory
US3944940A (en) * 1974-09-06 1976-03-16 Pertec Corporation Versatile phase-locked loop for read data recovery

Also Published As

Publication number Publication date
US4201948A (en) 1980-05-06
CH638358A5 (en) 1983-09-15
AU519278B2 (en) 1981-11-19
BE867506A (nl) 1978-11-27
AU3619178A (en) 1979-11-22
NL7705842A (nl) 1978-11-29
GB1588955A (en) 1981-05-07
DE2821064A1 (de) 1978-12-07

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19990201