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ES344566A1 - Un aparato para sumar una pluralidad de operandos de bitio binarios plurales. - Google Patents

Un aparato para sumar una pluralidad de operandos de bitio binarios plurales.

Info

Publication number
ES344566A1
ES344566A1 ES344566A ES344566A ES344566A1 ES 344566 A1 ES344566 A1 ES 344566A1 ES 344566 A ES344566 A ES 344566A ES 344566 A ES344566 A ES 344566A ES 344566 A1 ES344566 A1 ES 344566A1
Authority
ES
Spain
Prior art keywords
input
lines
summing
operands
signal lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES344566A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES344566A1 publication Critical patent/ES344566A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
ES344566A 1966-08-31 1967-08-29 Un aparato para sumar una pluralidad de operandos de bitio binarios plurales. Expired ES344566A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US57640166A 1966-08-31 1966-08-31

Publications (1)

Publication Number Publication Date
ES344566A1 true ES344566A1 (es) 1968-10-16

Family

ID=24304268

Family Applications (1)

Application Number Title Priority Date Filing Date
ES344566A Expired ES344566A1 (es) 1966-08-31 1967-08-29 Un aparato para sumar una pluralidad de operandos de bitio binarios plurales.

Country Status (9)

Country Link
US (1) US3515344A (es)
AT (1) AT268732B (es)
CH (1) CH457921A (es)
DE (1) DE1549477B1 (es)
DK (1) DK141182B (es)
ES (1) ES344566A1 (es)
FR (1) FR1529408A (es)
NL (1) NL6711951A (es)
SE (1) SE330277B (es)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
US3675001A (en) * 1970-12-10 1972-07-04 Ibm Fast adder for multi-number additions
PL106470B1 (pl) * 1977-02-01 1979-12-31 Inst Maszyn Matematycznych Uklad cyfrowy do obliczania wartosci zlozonych wyrazen arytmetycznych
US4110832A (en) * 1977-04-28 1978-08-29 International Business Machines Corporation Carry save adder
US4208722A (en) * 1978-01-23 1980-06-17 Data General Corporation Floating point data processing system
US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
US4228520A (en) * 1979-05-04 1980-10-14 International Business Machines Corporation High speed multiplier using carry-save/propagate pipeline with sparse carries
US4399517A (en) * 1981-03-19 1983-08-16 Texas Instruments Incorporated Multiple-input binary adder
US4556948A (en) * 1982-12-15 1985-12-03 International Business Machines Corporation Multiplier speed improvement by skipping carry save adders
US4616330A (en) * 1983-08-25 1986-10-07 Honeywell Inc. Pipelined multiply-accumulate unit
JPS6068432A (ja) * 1983-09-22 1985-04-19 Hitachi Ltd キヤリセ−ブアダ−の符号生成方式
JPH0640301B2 (ja) * 1983-09-22 1994-05-25 ソニー株式会社 並列乗算回路
DE3524981A1 (de) * 1985-07-12 1987-01-22 Siemens Ag Anordnung mit einem saettigbaren carry-save-addierer
US4901270A (en) * 1988-09-23 1990-02-13 Intel Corporation Four-to-two adder cell for parallel multiplication
US5150321A (en) * 1990-12-24 1992-09-22 Allied-Signal Inc. Apparatus for performing serial binary multiplication
US5625582A (en) * 1995-03-23 1997-04-29 Intel Corporation Apparatus and method for optimizing address calculations
US5818743A (en) * 1995-04-21 1998-10-06 Texas Instruments Incorporated Low power multiplier
US5612911A (en) * 1995-05-18 1997-03-18 Intel Corporation Circuit and method for correction of a linear address during 16-bit addressing
US5973705A (en) * 1997-04-24 1999-10-26 International Business Machines Corporation Geometry pipeline implemented on a SIMD machine
JP3529622B2 (ja) * 1998-05-08 2004-05-24 株式会社東芝 演算回路
US6484193B1 (en) * 1999-07-30 2002-11-19 Advanced Micro Devices, Inc. Fully pipelined parallel multiplier with a fast clock cycle
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US8073892B2 (en) * 2005-12-30 2011-12-06 Intel Corporation Cryptographic system, method and multiplier
CN105512724B (zh) * 2015-12-01 2017-05-10 中国科学院计算技术研究所 加法器装置、数据累加方法及数据处理装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3253131A (en) * 1961-06-30 1966-05-24 Ibm Adder
US3115574A (en) * 1961-11-29 1963-12-24 Ibm High-speed multiplier
US3311739A (en) * 1963-01-10 1967-03-28 Ibm Accumulative multiplier
US3278732A (en) * 1963-10-29 1966-10-11 Ibm High speed multiplier circuit
US3340388A (en) * 1965-07-12 1967-09-05 Ibm Latched carry save adder circuit for multipliers

Also Published As

Publication number Publication date
FR1529408A (fr) 1968-06-14
SE330277B (es) 1970-11-09
AT268732B (de) 1969-02-25
DK141182C (es) 1980-06-23
US3515344A (en) 1970-06-02
CH457921A (de) 1968-06-15
DE1549477B1 (de) 1971-03-25
NL6711951A (es) 1968-03-01
DK141182B (da) 1980-01-28

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