ES2540651A2 - Regulación de tensión de sub-dominio de procesador de gráficos - Google Patents
Regulación de tensión de sub-dominio de procesador de gráficos Download PDFInfo
- Publication number
- ES2540651A2 ES2540651A2 ES201431706A ES201431706A ES2540651A2 ES 2540651 A2 ES2540651 A2 ES 2540651A2 ES 201431706 A ES201431706 A ES 201431706A ES 201431706 A ES201431706 A ES 201431706A ES 2540651 A2 ES2540651 A2 ES 2540651A2
- Authority
- ES
- Spain
- Prior art keywords
- voltage
- domain
- sub
- power
- translation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001105 regulatory effect Effects 0.000 abstract 3
- 108020001568 subdomains Proteins 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Power Sources (AREA)
Abstract
Regulación de tensión de sub-dominios de procesador suministrados por un mismo carril de alimentación de dominio de tensión. La tensión a determinadas unidades lógicas en el interior del dominio de tensión puede reducirse en relación con otras unidades lógicas del dominio de tensión, reduciendo el tiempo de espera a alta potencia. En una realización, un primer sub-dominio de tensión regulada incluye por lo menos una unidad de ejecución (EU, execution unit) mientras que un segundo sub-dominio de tensión regulada incluye por lo menos un muestreador de texturas para proporcionar flexibilidad en el establecimiento del punto de potencia - rendimiento del núcleo de gráficos más allá de la modulación del recuento de EU activas a través de un control (de control por puerta) de dominio de potencia. En unas realizaciones, una tensión de sub-dominio se regula mediante un DLDO sobre placa para una conmutación de tensión rápida. La frecuencia de reloj y la tensión de sub-dominio pueden conmutarse más rápido que la tensión del carril de alimentación de dominio de tensión, permitiendo una gestión de potencia granulada de manera más fina que puede ser sensible a la demanda de carga de trabajo de EU.
Description
Claims (1)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/134,598 US9563263B2 (en) | 2013-12-19 | 2013-12-19 | Graphics processor sub-domain voltage regulation |
US14/134,598 | 2013-12-19 |
Publications (3)
Publication Number | Publication Date |
---|---|
ES2540651A2 true ES2540651A2 (es) | 2015-07-10 |
ES2540651R1 ES2540651R1 (es) | 2015-08-04 |
ES2540651B1 ES2540651B1 (es) | 2016-05-13 |
Family
ID=53399973
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES201431706A Expired - Fee Related ES2540651B1 (es) | 2013-12-19 | 2014-11-19 | Regulación de tensión de sub-dominio de procesador de gráficos |
Country Status (2)
Country | Link |
---|---|
US (2) | US9563263B2 (es) |
ES (1) | ES2540651B1 (es) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10088891B2 (en) * | 2013-09-23 | 2018-10-02 | Cornell University | Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency |
US10048742B2 (en) * | 2014-01-16 | 2018-08-14 | Mediatek Inc. | Integrated circuit and electronic device |
US9817470B2 (en) * | 2015-02-25 | 2017-11-14 | Qualcomm Incorporated | Processor power management responsive to a sequence of an instruction stream |
WO2017049592A1 (en) | 2015-09-25 | 2017-03-30 | Intel Corporation | Method and apparatus to improve shared memory efficiency |
US10163557B2 (en) * | 2015-12-17 | 2018-12-25 | Intel Corporation | Helical plated through-hole package inductor |
US10209767B2 (en) * | 2016-02-02 | 2019-02-19 | Apple Inc. | Power management architecture |
US10193442B2 (en) | 2016-02-09 | 2019-01-29 | Faraday Semi, LLC | Chip embedded power converters |
US10103714B2 (en) | 2016-03-01 | 2018-10-16 | Qualcomm Incorporated | Adjust voltage for thermal mitigation |
US10684671B2 (en) * | 2016-05-27 | 2020-06-16 | Qualcomm Incorporated | Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit |
US10423206B2 (en) * | 2016-08-31 | 2019-09-24 | Intel Corporation | Processor to pre-empt voltage ramps for exit latency reductions |
US10235811B2 (en) | 2016-12-29 | 2019-03-19 | Intel Corporation | Replicating primitives across multiple viewports |
US10423209B2 (en) * | 2017-02-13 | 2019-09-24 | Apple Inc. | Systems and methods for coherent power management |
US9899922B1 (en) | 2017-02-13 | 2018-02-20 | Qualcomm Incorporated | Digital sub-regulators |
US10424107B2 (en) | 2017-04-01 | 2019-09-24 | Intel Corporation | Hierarchical depth buffer back annotaton |
US10444817B2 (en) * | 2017-04-17 | 2019-10-15 | Intel Corporation | System, apparatus and method for increasing performance in a processor during a voltage ramp |
US11010953B2 (en) | 2017-04-21 | 2021-05-18 | Intel Corporation | Dedicated fixed point blending for energy efficiency |
US10003337B1 (en) | 2017-05-17 | 2018-06-19 | International Business Machines Corporation | Resonant virtual supply booster for synchronous logic circuits and other circuits with use of on-chip integrated magnetic inductor |
EP3435192B1 (en) * | 2017-07-28 | 2022-08-24 | NXP USA, Inc. | Ultra low power linear voltage regulator |
US10178619B1 (en) * | 2017-09-29 | 2019-01-08 | Intel Corporation | Advanced graphics power state management |
US11353900B2 (en) * | 2018-06-27 | 2022-06-07 | Intel Corporation | Integrated cross-domain power transfer voltage regulators |
US11011495B2 (en) * | 2018-08-23 | 2021-05-18 | Advanced Micro Devices, Inc. | Multiple-die integrated circuit with integrated voltage regulator |
US10803909B2 (en) * | 2018-08-24 | 2020-10-13 | Micron Technology, Inc. | Power management component for memory sub system power cycling |
US10628910B2 (en) | 2018-09-24 | 2020-04-21 | Intel Corporation | Vertex shader with primitive replication |
US11656676B2 (en) * | 2018-12-12 | 2023-05-23 | Intel Corporation | System, apparatus and method for dynamic thermal distribution of a system on chip |
US10504848B1 (en) | 2019-02-19 | 2019-12-10 | Faraday Semi, Inc. | Chip embedded integrated voltage regulator |
WO2020214857A1 (en) | 2019-04-17 | 2020-10-22 | Faraday Semi, Inc. | Electrical devices and methods of manufacture |
US10447269B1 (en) | 2019-05-08 | 2019-10-15 | Nxp B.V. | Level shifter |
US10742215B1 (en) * | 2019-05-20 | 2020-08-11 | Nxp B.V. | Circuit to support multiple voltage level input/output |
US11314299B2 (en) * | 2020-03-27 | 2022-04-26 | Intel Corporation | System, apparatus and method for dynamic power state scaling of a voltage regulator for a processor |
US11063516B1 (en) | 2020-07-29 | 2021-07-13 | Faraday Semi, Inc. | Power converters with bootstrap |
US20220198022A1 (en) * | 2020-12-23 | 2022-06-23 | Intel Corporation | Secure device power-up apparatus and method |
US20230297159A1 (en) * | 2022-03-20 | 2023-09-21 | Intel Corporation | Granular gpu dvfs with execution unit partial powerdown |
US12081124B2 (en) | 2022-04-29 | 2024-09-03 | Apple Inc. | Regulator switch array |
US11990839B2 (en) | 2022-06-21 | 2024-05-21 | Faraday Semi, Inc. | Power converters with large duty cycles |
US12222797B2 (en) | 2022-12-19 | 2025-02-11 | Advanced Micro Devices, Inc. | Dynamic configuration of processor sub-components |
KR20240164240A (ko) * | 2023-05-12 | 2024-11-19 | 삼성전자주식회사 | 시스템 온 칩 및 그 동작 방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070008011A1 (en) * | 2005-06-29 | 2007-01-11 | Paulette Thurston | Distributed power and clock management in a computerized system |
WO2013077848A1 (en) * | 2011-11-21 | 2013-05-30 | Intel Corporation | Reconfigurable graphics processor for performance improvement |
US20130173933A1 (en) * | 2011-12-29 | 2013-07-04 | Advanced Micro Devices, Inc. | Performance of a power constrained processor |
KR101422924B1 (ko) * | 2012-10-18 | 2014-08-13 | 삼성전기주식회사 | 저전압 강하 레귤레이터 |
US9405357B2 (en) * | 2013-04-01 | 2016-08-02 | Advanced Micro Devices, Inc. | Distribution of power gating controls for hierarchical power domains |
-
2013
- 2013-12-19 US US14/134,598 patent/US9563263B2/en active Active
-
2014
- 2014-11-19 ES ES201431706A patent/ES2540651B1/es not_active Expired - Fee Related
-
2017
- 2017-01-18 US US15/409,366 patent/US10359834B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
ES2540651R1 (es) | 2015-08-04 |
ES2540651B1 (es) | 2016-05-13 |
US20170322617A1 (en) | 2017-11-09 |
US20150177823A1 (en) | 2015-06-25 |
US10359834B2 (en) | 2019-07-23 |
US9563263B2 (en) | 2017-02-07 |
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