ES2378865A1 - CONVERTER OF ELECTRICAL ENERGY OF INTERLOCKING OF FOUR OR MORE LEVELS AND CONTROL METHOD. - Google Patents

Abstract

Four or More Level Active Latching Power Converter and Control Method A four or more level static power converter topology is presented. The topology is formed by a pyramidal structure of elementary cells. Each elementary cell is formed by two elementary devices. Each elemental device is made up of a controlled electronic switch and an anti-parallel diode. The switching states of the converter that allow its control are defined, as well as a transition strategy between switching states. The proposed converter and control are applicable in drives of alternating current electric motors, systems for the use of renewable energy, electric traction equipment, power systems, etc.

Description

Electric power converter active interlocking of four or more levels and method of control.

Technical sector

Electronic hardware for electrical systems and power electronics

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State of the art

Multilevel conversion techniques have opened a door to advances in conversion technology electric power. For a specific semiconductor technology, these techniques allow a greater capacity of power by converter, greater efficiency and less harmonic distortion. They have proposed different multilevel topologies:

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Multilevel converters full bridge cascaded ("cascaded H-bridge").

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Multilevel converters diode interlock ("clamped diode").

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Multilevel converters interlocking by capacitors or floating capacitors ("clamped capacitor" or "flying capacitors").

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Hybrid combinations of previous.

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In particular, a topology has been proposed general in:

FZ Peng, "A generalized multilevel inverter topology with self voltage balancing", IEEE Transactions on Industry Applications , vol. 37, pp. 611-618, 2001.

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This topology includes floating capacitors, controlled electronic switches and diodes in antiparallel.

The topology contemplated herein invention incorporates only electronic switches controlled and diodes in antiparallel. No capacitors are incorporated floating, a fact that substantially modifies the control and operating characteristics of the converter.

In the literature appears the particular case of three levels of the topology object of the present invention, but its extension has not been presented at more levels, and the control of converter proposed in the literature differs from the one described here.

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Description of the invention

The topology of a converter is defined multilevel electric power interlocking active, the states of switching required for its control and a strategy of transition between these switching states.

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Topology

Figure 1 presents the topology of a m- level converter. The circuit has m input terminals (i_ {k}, k \ in {1, 2, ..., m }) and an output terminal (o). The number of converter levels corresponds to the number of input terminals. Between two consecutive input terminals (i_ {k} and i_ {k + 1}) typically a capacitive element (capacitor) or a voltage source (power supply, battery, etc.) is connected, so that the voltage of the terminal i_ {k} is less than or equal to the voltage of terminal i_ {k + 1}.

The circuit is formed by a pyramidal connection of m \ cdot ( m -1) / 2 elementary cells. Each elementary cell is formed by two elementary devices, as shown in Figure 1. Each elementary device consists of a controlled electronic switch (designated S_ {pxy} and S_ {nxy}; x , y \ in {1, 2 , ..., m -1}) and an uncontrolled electronic switch (diode), connected as shown in Figure 1 (anti-parallel connection).

The controlled electronic switch can be unidirectional ( i S can only be greater than or equal to zero) or bidirectional ( i S can be greater than, equal to or less than zero) in current. The controlled switch can be unidirectional ( v S can only be greater than or equal to zero) or bidirectional ( v S can be greater than, equal to or less than zero) in voltage. The typical case is that the controlled switch be bidirectional in current and unidirectional in voltage.

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The electronic controlled switch of the Elementary device presents two states, according to the two Possible states of your control signal:

a) On: The voltage v S at the terminals of the switch is approximately zero.

b) Off: The current i S flowing through the switch is approximately zero.

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The elementary device, defined by the set of controlled switch and uncontrolled switch, it can be done with a single transistor or can be done with any combination of transistors and diodes (series, parallel, etc.) that effectively has the same functionality.

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Switching states

The output terminal (o) can be galvanically connected with a low impedance to each of the input terminals (i_ {k}, k \ in {1, 2, ..., m }) properly controlling the status of all Electronic controlled switches. -1 m are defined control variables (c _ {j}, j \ {1, 2, ..., m -1}) to represent the state of the control signals of the electronic switches controlled. Each controlled switch is assigned a control variable ( c j) or its complementary value (\ overline {\ mathit {c}} _ j), as indicated in Figure 2. These control variables have Two possible values:

a) c j = 0, in which case all switches controlled with this associated control variable are off and those with the associated complementary value \ overline {\ mathit {c}} _ {j} = 1 are on.

b) c j = 1, in which case all switches controlled with this associated control variable are on and those with the associated complementary value \ overline {\ mathit {c}} _ {j} = 0 are off.

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To connect the output terminal (or) to the input terminal i_ {k}, the following values are assigned to the control signals:

one

In this way, the m switching states that allow the output terminal to be connected to the m input terminals are defined. The following table presents a summary of these switching states:

2

In the switching state k , all those controlled switches that allow galvanically connecting the input terminal i_ {k} with the output terminal (o) via m -1 elementary devices are switched on with a low impedance. Additionally, other controlled switches are switched on which allow to guarantee a blocking voltage v s in the controlled switches turned off equal to the voltage difference between consecutive input terminals.

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Transition between switching states

To make a transition between two adjacent switching states (transition from a switching state k to the immediately higher (k + 1) or lower ( k -1)), it is necessary to change the state of m controlled switches. The switches to be turned off are turned off first and then the switches to be turned on. Let k i be the initial switching state and k f the final switching state of the transition between adjacent states. If ( k f - k i) i i o> 0 (where i o is the output terminal current (Figure 1)), the energy losses of the transition They concentrate on the first device that turns on. If ( k f - k i) \ cdot i o <0, the energy losses of the transition are concentrated in the last device that shuts down. Therefore, a transition strategy is defined between adjacent switching states, in which in successive transitions the first switch that turns on between the switches to be switched on and the last switch that switches off between the switches to turn off is alternated. In this way, the energy losses of the successive transitions are distributed among all the switches.

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Brief explanation of the drawings

Figure 1: Topology of an active interlock converter of m levels.

Figure 2: Topology of an m- level active interlock converter, with indication of the control variable assigned to each controlled switch.

Figure 3: Topology of a converter five-level active interlocking (one branch), in which employ Metal Oxide Semiconductor Field Effect type transistors Transistor (MOSFET) of channel n and enrichment.

Figure 4: Topology of a converter five-level active interlocking (one branch), in which they use MOSFET type n and enrichment transistors, with indication of the control variable assigned to each transistor.

Figure 5: Current converter DC-DC (DC-DC) or direct current-alternating current (cc-ca) single-phase five-level, with four voltage sources and a branch.

Figure 6: cc-cc converter Five levels, with intermediate DC bus consisting of four series capacitors and two branches.

Figure 7: cc-cc converter or single-phase five-level cc-ca, with source voltage connected to four capacitors in series and two branches.

Figure 8: cc-ca converter three-phase five-level, with voltage source connected to four series capacitors and three branches.

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Embodiments of the invention

The present invention is further illustrated. by the following example, which is not intended to be limiting of its reach

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Example 1 Five-level active interlocking converter with MOSFETs

Figure 3 shows a branch of a five-level converter in which type transistors are used Metal Oxide Semiconductor Field Effect Transistor (MOSFET) channel n and enrichment. The diodes shown in Figure 3 are may correspond to the parasite diode of this type of transistors or with external diodes connected in antiparallel with MOSFET transistors, as indicated in Figure 3.

The assignment of control variables to each transistor. The branch presents the following five switching states to allow connecting the output terminal with each of the five terminals of entry:

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3

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The transition between switching states adjacent is done by first turning off the transistors to turn off and subsequently turning on the transistors to turn on. Additionally, in successive transitions of a state of switching to another, the transistor is switched to last off place and the transistor to turn on first. For example, in the transition from switching state 2 to switching state 3, transistors S_ {n21} and S_ {n22} must be turned off and the transistors S_ {p21}, S_ {p22} and S_ {p23} must be turn on. It would proceed as follows:

a) Sequence of transistors to turn off last place in successive transitions from switching state 2 to switching state 3:

a.1)

In the first transition, the transistor goes out last is S_ {n21}.

a.2)

In the second transition, the transistor goes out last is S_ {n22}.

a.3)

In subsequent transitions the cycle is repeated defined by a.1 and a.2.

b) Sequence of transistors to be switched on first in successive switching state transitions 2 to switching state 3:

b.1)

In the first transition, the transistor that turn on first is S_ {p21}.

b.2)

In the second transition, the transistor that Turn on first is S_ {p22}.

b.3)

In the third transition, the transistor that Turn on first is S_ {p23}.

b.4)

In subsequent transitions the cycle is repeated defined by b.1, b.2, and b.3.

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In Figure 5, Figure 6, Figure 7 and Figure 8, show examples of converters that can be performed using the use of the branch presented in Figure 3.

Figure 5 shows a DC-DC converter (DC-DC) or single-phase DC-AC converter, in which voltage sources are connected between each pair of adjacent input terminals of the branch . These voltage sources represent systems that maintain an approximately constant voltage between their terminals such as power supplies, batteries or photovoltaic panels with a capacitor connected between their positive and negative terminals. In a filter output terminal is connected and a load represented by a set inductance (L F {}), capacity (C {F}) and resistance (R {L}).

Figure 6 shows a cc-cc converter with two branches, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. The voltage source of value V cc is connected through an inductance ( L Fa) to the output terminal of the first branch. The output terminal of the second branch is connected to a filter and a load represented by a set inductance ( L Fb), capacity ( C F) and resistance ( R L).

A single-phase cc-cc or cc-ca converter with two branches is shown in Figure 7, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. A voltage source of value V cc is connected between the input terminals i_ {1} and i_ {5}. The output terminals of the branches are connected to a filter and a load represented by a set inductance (L F {}), capacity (C {F}) and resistance (R {L}).

A three-phase dc-ac converter with three branches is shown in Figure 8, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. A voltage source of value V cc is connected between the input terminals i_ {1} and i_ {5}. The output terminals of the branches are connected to a three - phase filter and a load represented by a set inductance (L F {}) and resistance (R {L}) in series per phase.

Claims (4)

1. An active interlocking electric power converter of four or more levels, characterized by being constituted by a pyramidal structure of m \ cdot ( m -1) / 2 elementary cells, with an output terminal and m input terminals, being m the number of levels; each elementary cell is constituted by two elementary devices; each elementary device is constituted by means to interrupt the current in a controlled manner and means to interrupt the current in an uncontrolled manner. 2. A method of controlling the power converter of active interlock four or more levels of claim 1, wherein m -1 defined control variables (c _ {j}, j \ {1, 2, ..., m -1}) to represent the status of the control signals of the controlled electronic switches, with two possible values, zero and one, indicating that the corresponding switch is off or on, respectively; the control variable c j is assigned to the diagonal of switches S_ {njy}, and \ in {1, 2, ..., j }, and its complementary value (\ overline {\ mathit {c}} j) to the diagonal of switches S_ {pjy}, and \ in {1, 2, ..., m -j}; to electrically connect the output terminal (or) to the input terminal
i_ {k} ( k \ in {1, 2, ..., m }) is set c j = 0 for all j <k and set c j = 1 for all j \ geqk. 3. A control method of an active interlocking electric power converter of four or more levels according to claim 2, characterized in that the successive transitions between two adjacent switching states are made by alternating the last switch to be switched off between the switches to be turned off. 4. A control method of an active interlocking electric power converter of four or more levels according to claim 2, characterized in that the successive transitions between two adjacent switching states are performed by alternating the first switch to be switched on between the switches to be switched on.