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ES2082823T3 - Procedimiento de fabricacion de dispositivos electronicos. - Google Patents

Procedimiento de fabricacion de dispositivos electronicos.

Info

Publication number
ES2082823T3
ES2082823T3 ES90302731T ES90302731T ES2082823T3 ES 2082823 T3 ES2082823 T3 ES 2082823T3 ES 90302731 T ES90302731 T ES 90302731T ES 90302731 T ES90302731 T ES 90302731T ES 2082823 T3 ES2082823 T3 ES 2082823T3
Authority
ES
Spain
Prior art keywords
substrate
loads
slot
barrier
members
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90302731T
Other languages
English (en)
Inventor
Brent J Blumenstock
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2082823T3 publication Critical patent/ES2082823T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

EN UN PROCESO DE ENCAPSULACION DE CIRCUITO INTEGRADO HIBRIDO, CADA SISTEMA DE CARGA (14) ES RODEADO POR UN MIEMBRO DE BARRERA ALARGADO CON FORMA DE C (17) QUE SE ABRAZA SOBRE LAS PORCIONES DEL SISTEMA DE CARGA ADYACENTE AL SUBSTRATO (11); ESTO ES, LOS LADOS OPUESTOS DE UNA RANURA (18) EN EL MIEMBRO DE BARRERA SE ASEN A LOS LADOS OPUESTOS DE LAS CARGAS. DESPUES DE ESO, LA SILICONA RTV SIN CURAR (15) SE REPARTE SOBRE EL SUBSTRATO, CIRCULA SOBRE Y RODEA LOS CHIPS (12) MONTADOS SOBRE LA SUPERFICIE DEL SUBSTRATO Y SE IMPIDE QUE CIRCULE A LO LARGO DE LAS CARGAS (14) MEDIANTE LOS MIEMBROS CON FORMA DE C (17), CADA UNO DE LOS CUALES, DEBIDO A SU CONFIGURACION, CONSTITUYE UNA BARRERA PARA QUE EL FLUIDO CIRCULE, TANTO A LO LARGO DE LA EXTENSION DE LAS DIVERSAS CARGAS COMO SOBRE LA PARTE SUPERIOR DE LOS MIEMBROS CON FORMA DE C. EN UNA PRESENTACION, LOS NIVELADORES PUEDEN INTEGRARSE SOBRE EL MIEMBRO CON FORMA DE C OPUESTO AL SUBSTRATO PARA AYUDAR A ABRIR LA RANURA PARA PERMITIR QUE LAS CARGAS PUEDAN INSERTARSE CON FACILIDAD DENTRO DEL MIEMBRO CON FORMA DE C. EN OTRA PRESENTACION, EL MIEMBRO EN FORMA DE C ESTA HECHO DE UN MATERIAL PLASTICO, Y VA INTEGRADO CON UN MIEMBRO EN FORMA DE O QUE PUEDE SER COMPRIMIDO MEDIANTE UN INSTRUMENTO DE PINZAS ASI COMO ABRIR LA RANURA PARA LA INSERCION FACIL DE LAS CARGAS DENTRO DEL MIEMBRO CON FORMA DE C.
ES90302731T 1989-03-22 1990-03-14 Procedimiento de fabricacion de dispositivos electronicos. Expired - Lifetime ES2082823T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/327,463 US4908935A (en) 1989-03-22 1989-03-22 Method for fabricating electronic devices

Publications (1)

Publication Number Publication Date
ES2082823T3 true ES2082823T3 (es) 1996-04-01

Family

ID=23276649

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90302731T Expired - Lifetime ES2082823T3 (es) 1989-03-22 1990-03-14 Procedimiento de fabricacion de dispositivos electronicos.

Country Status (6)

Country Link
US (1) US4908935A (es)
EP (1) EP0389170B1 (es)
JP (1) JPH02280345A (es)
DE (1) DE69025221T2 (es)
ES (1) ES2082823T3 (es)
HK (1) HK140196A (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2777500B2 (ja) * 1992-03-24 1998-07-16 株式会社日立製作所 半導体装置の保護層の形成方法
CA2120468A1 (en) * 1993-04-05 1994-10-06 Kenneth Alan Salisbury Electronic module containing an internally ribbed, integral heat sink and bonded, flexible printed wiring board with two-sided component population
US5644839A (en) * 1994-06-10 1997-07-08 Xetel Corporation Surface mountable substrate edge terminal
DE19541976A1 (de) * 1995-11-10 1997-05-15 Ego Elektro Blanc & Fischer Elektrische Schaltung
US6232153B1 (en) * 1998-06-04 2001-05-15 Ramtron International Corporation Plastic package assembly method for a ferroelectric-based integrated circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899305A (en) * 1973-07-23 1975-08-12 Capsonic Group Inc Insert frame for insert molding
NL189379C (nl) * 1977-05-05 1993-03-16 Richardus Henricus Johannes Fi Werkwijze voor inkapselen van micro-elektronische elementen.
US4271588A (en) * 1977-12-12 1981-06-09 Motorola, Inc. Process of manufacturing a encapsulated hybrid circuit assembly
US4396796A (en) * 1980-10-30 1983-08-02 Western Electric Company, Inc. Encapsulated electronic devices and encapsulating compositions
US4451973A (en) * 1981-04-28 1984-06-05 Matsushita Electronics Corporation Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
US4556896A (en) * 1982-08-30 1985-12-03 International Rectifier Corporation Lead frame structure
WO1984001922A1 (en) * 1982-11-17 1984-05-24 Max Jones Clip for paper and like material
US4508758A (en) * 1982-12-27 1985-04-02 At&T Technologies, Inc. Encapsulated electronic circuit
US4506416A (en) * 1983-02-09 1985-03-26 King Jim Co., Ltd. Paper clip
US4552818A (en) * 1984-05-10 1985-11-12 At&T Technologies, Inc. Silicone encapsulant containing porphyrin
DE3623766C1 (es) * 1986-07-15 1987-06-11 Kurt 7307 Aichwald De Lorber

Also Published As

Publication number Publication date
DE69025221D1 (de) 1996-03-21
JPH02280345A (ja) 1990-11-16
EP0389170A3 (en) 1992-02-26
DE69025221T2 (de) 1996-06-20
EP0389170B1 (en) 1996-02-07
JPH0584056B2 (es) 1993-11-30
EP0389170A2 (en) 1990-09-26
HK140196A (en) 1996-08-02
US4908935A (en) 1990-03-20

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