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ES2030476T3 - Instalacion de sincronizacion para un desmultiplexor de senales digitales. - Google Patents

Instalacion de sincronizacion para un desmultiplexor de senales digitales.

Info

Publication number
ES2030476T3
ES2030476T3 ES198888112055T ES88112055T ES2030476T3 ES 2030476 T3 ES2030476 T3 ES 2030476T3 ES 198888112055 T ES198888112055 T ES 198888112055T ES 88112055 T ES88112055 T ES 88112055T ES 2030476 T3 ES2030476 T3 ES 2030476T3
Authority
ES
Spain
Prior art keywords
digital signal
desmultiplexer
bit
slip
synchronization installation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198888112055T
Other languages
English (en)
Inventor
Wilhelm Dipl.-Ing. Volejnik
Johann Magerl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of ES2030476T3 publication Critical patent/ES2030476T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

EL PROBLEMA ESTA EN EL EQUILIBRADO DE UN RESBALAMIENTO DE BIT DE MULTIPLEX DE UNA SEÑAL MULTIPLEX. UNA INSTALACION DE RECONOCIMIENTO DE RESBALAMIENTOS DE BIT (10) TIENE UN RESBALAMIENTO DE BIT Y CONDUCE UNA CONMUTACION DE FRECUENCIA INTERMITENTE (11) DE TAL MANERA, QUE SE RETORNA LA PORCION DE LOS BITS, QUE CEDEN SOBRE LAS SALIDAS (4A - 4D) DEL DEMULTIPLEXER (3) A TRAVES DE ACELERACION INTERMITENTE O RETARDO INTERMITENTE SOBRE EL VALOR NOMINAL. EL INVENTO SE APLICA EN DEMULTIPLEXER DE SEÑALES DIGITALES.
ES198888112055T 1987-07-31 1988-07-26 Instalacion de sincronizacion para un desmultiplexor de senales digitales. Expired - Lifetime ES2030476T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3725477 1987-07-31

Publications (1)

Publication Number Publication Date
ES2030476T3 true ES2030476T3 (es) 1992-11-01

Family

ID=6332834

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198888112055T Expired - Lifetime ES2030476T3 (es) 1987-07-31 1988-07-26 Instalacion de sincronizacion para un desmultiplexor de senales digitales.

Country Status (6)

Country Link
EP (1) EP0301481B1 (es)
AT (1) ATE75087T1 (es)
AU (1) AU587947B2 (es)
DE (1) DE3870073D1 (es)
ES (1) ES2030476T3 (es)
GR (1) GR3004923T3 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241541A (en) * 1990-03-15 1993-08-31 International Business Machines Corporation Burst time division multiplex interface for integrated data link controller
FR2682842B1 (fr) * 1991-10-18 1994-07-22 France Telecom Procede et dispositif de comptage des glissements d'horloge.
FR2689709B1 (fr) 1992-04-01 1995-01-06 France Telecom Procédé de correction de glissements non contrôlés de séquences de données portées par des liaisons numériques et dispositf pour la mise en Óoeuvre de ce procédé.
DE10154252B4 (de) * 2001-11-05 2005-12-01 Siemens Ag Verfahren zur Erkennung und Kompensation von Bit-slip-Fehlern bei der seriellen Übertragung digitaler Daten sowie hierfür empfängerseitig verwendbare Schaltungsanordnung
JP3945287B2 (ja) * 2002-03-28 2007-07-18 日本電気株式会社 データ受信回路、データ受信方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2930586A1 (de) * 1979-07-27 1981-02-12 Siemens Ag Schaltungsanordnung zur synchronisierung einer untergeordneten einrichtung, insbesondere einer digitalen teilnehmerstation, durch eine uebergeordnete einrichtung, insbesondere eine digitale vermittlungsstelle eines pcm-fernmeldenetzes
DE3212450A1 (de) * 1982-04-02 1983-10-13 Siemens AG, 1000 Berlin und 8000 München Synchronisiereinrichtung einer digitalsignal-demultiplexeinrichung
DE3374829D1 (en) * 1983-09-07 1988-01-14 Ibm Phase-locked clock

Also Published As

Publication number Publication date
DE3870073D1 (de) 1992-05-21
AU2019388A (en) 1989-02-02
EP0301481A1 (de) 1989-02-01
GR3004923T3 (es) 1993-04-28
EP0301481B1 (de) 1992-04-15
AU587947B2 (en) 1989-08-31
ATE75087T1 (de) 1992-05-15

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