EP4638738A1 - Circuit for detecting current in microarray synthesis chip, resulting chip and system, and methods of using the same - Google Patents

Abstract

A microarray chip, a system comprising the microarray chip, and methods for testing or using the microarray chip are provided. The microarray chip includes an electrode array comprising a plurality of cells. Each of the plurality of cells comprises an anode and a cathode, each of which comprise an electrically conductive material. The microarray chip further includes a plurality of current comparator circuits. Each current comparator circuit includes a first current mirror connected with a reference current source, a first capacitor connected with the first current mirror, a second current mirror configured to be connected with one of the plurality of cells, and a second capacitor and a third capacitor connected in parallel and connected with the second current mirror. Each current comparator circuit also includes two voltage comparators configured to compare the voltages from the capacitors and provide digital signals selected from 0 and 1.

Description

CIRCUIT FOR DETECTING CURRENT IN MICRO ARRAY SYNTHESIS CHIP, RESULTING CHIP AND SYSTEM, AND METHODS OF USING THE SAME

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims the priority benefit of U.S. Provisional Application No. 63/476,441, filed December 21, 2022, which is expressly incorporated by references herein in its entirety.

FIELD OF THE INVENTION

[0002] The disclosure relates to microarray synthesis generally. More particularly, the disclosed subject matter relates to a circuit for measuring current of a cell in a microarray chip, a chip or system comprising such a circuit, and methods of using the circuit, the chip, and the system.

BACKGROUND

[0003] Microarrays have been used for synthesis of oligomers or polymers such as DNA and peptides.

[0004] Rapid developments in the field of DNA microarrays have led to different methods for synthetic preparation of DNA. Such methods include spotting pre-synthesized oligonucleotides, photolithography using mask or maskless techniques, in situ synthesis by printing reagents, and in situ parallel synthesis on a microarray of electrodes using electrochemical deblocking of protective groups.

[0005] Synthetic preparation of a peptide array was originally reported in 1991 using photo-masking techniques. This method was extended in 2000 to include an addressable masking technique using photogenerated acids and/or in combination with photosensitizers for deblocking. Spotting pre-synthesized peptides or isolated proteins has been used to create peptide arrays.

[0006] During the synthesis of DNA or peptides on a microarray or other substrate, each successive addition of a respective monomer (i.e., nucleotide or amino acid, respectively) involves the removal of a protecting group to allow addition of the next monomer unit. This process step is often called “deblocking.” In such a removal or deblocking step, a specific type of solution can be used that is referred to as a deblocking solution, i.e., the solution deblocks the end of the chain of a species such as a DNA or peptide by removing a protective group to allow the addition of a next monomer unit. In general, protective groups can be acid-labile or base- labile, i.e., acidic conditions remove the acid-labile group and basic conditions remove the base- labile group. Additionally, some protecting groups are labile to only specific types of reagents. Alternatively, deblocking can be accomplished using photolabile-protecting groups, which can be removed by light of a certain wavelength.

[0007] Protecting groups can be removed by electrochemically generated reagents on a microarray of electrodes (e.g., electrode array) as a step in the synthesis of polymers on the microarray. In this method, protecting groups are removed only at selected electrodes by applying a potential only at the selected electrodes. In order to prevent deprotection at neighboring electrodes (i.e., “crosstalk”), the method and the solution need to confine the electrochemically generated reagents to the region immediately adjacent to the electrode undergoing deblocking. Crosstalk refers to the bleed-over of reagents generated at one electrode to another nearby electrode causing undesirable extra synthesis at that nearby electrode.

Minimal crosstalk is most desirable. Where an aqueous-based deblock solution having a buffer is used, the solution likely buffers the generation of acidic or basic species to the region near the electrode and prevents diffusion of such species to adjacent electrodes. However, in organicbased deblock solutions, the mechanism of preventing crosstalk is not necessarily well understood but may involve molecular interactions that remove or pacify acidic reagent by some other species.

[0008] Protecting groups can be removed by electrochemical methods on an electrode array device as a step in the synthesis of polymers on the microarray, for example, as described in U.S. Pat. Nos. 6,093,302, 6,280,595, and 6,444,111, referred to as the “Montgomery patents.” In these patents, protecting groups are removed only at selected electrodes by applying a potential only at the selected electrodes. In order to prevent deprotection at neighboring electrodes (i.e., “crosstalk”), the method and the solution need to confine the electrochemically generated reagents to the region immediately adjacent to the electrode undergoing deblocking. In the Montgomery patents, a buffered aqueous-based deblock solution such as a 0.10 M solution and a 0.05 M solution of aqueous sodium phosphate buffer, is used. The buffer absorbs acidic or basic species generated by an activated electrode (electrochemically) so that a pH change is confined to the region near the electrode.

[0009] The electrochemical system described in the Montgomery patents works best if the buffering system is weak acid/weak base system (or a redox system). Hence the drop-off in acid or base becomes exponential and is related to the pKi of the weak acid/conjugate base system. However, such a system encounters problems when the distance between electrodes is decreased (or the density of electrodes per unit area of an electrode array is increased). The extent of the proton plume will then depend upon the quantity of acid produced, the buffer capacity, and limits of diffusion.

[0010] There was a need to improve such a system for electrochemical synthesis of oligomers when the density of electrodes is increased. To address such a need, as described in U.S. Patent No. 10,525,436, an electrode array architecture employing continuous or discontinuous circumferential electrodes are provided. Reagents, such as acid, generated in a center electrode are countered (neutralized) by reagents, such as base, generated at the corners or at the outer ring. A process is provided for the neutralization of acid generated at anodes by base generated at cathodes circumferentially located to each other so as to confine a region of pH change.

SUMMARY

[0011] The present disclosure provides a circuit for measuring current of cells in a high throughput microarray chip for synthesis, a microarray chip comprising such a circuit, a system comprising the microarray chip, and methods for testing or using the microarray chip. Such a microarray chip is used for electrochemical synthesis of an oligomer such as DNA, peptide, RNA, or any other suitable oligomers.

[0012] In accordance with some embodiments, such a microarray chip comprises an electrode array, which comprises a plurality of cells. Each of the plurality of cells comprises an anode and a cathode. Each of the anode and the cathode comprises an electrically conductive material.

[0013] The microarray chip further comprises a plurality of current comparator circuits. Each of the plurality of current comparator circuits comprises: a first current mirror connected with a reference current source, a first capacitor connected with the first current mirror, a second current mirror configured to be connected with one of the plurality of cells, and a second capacitor and a third capacitor connected with the second current mirror. The second capacitor and the third capacitor are connected in parallel. Each current comparator circuit further comprises a first voltage comparator and a second voltage comparator. The first voltage comparator is connected with the first capacitor and the second capacitor, and is configured to compare the first voltage from the first capacitor and the second voltage from the second capacitor and provide a first digital signal selected from 0 and 1. The second voltage comparator is connected with the first capacitor and the third capacitor, and is configured to compare the first voltage from the first capacitor and the third voltage from the third capacitor and provide a second digital signal selected from 0 and 1. The microarray chip is configured to be used for parallel synthesis of oligomers such as DNA, RNA, and peptides on selected cells.

[0014] In each cell, the anode may be a central electrode and the cathode may be a circumferential electrode or a grid surrounding the anode.

[0015] In some embodiments, the microarray chip further comprises a current supplying circuit, a switching circuit, and a read back controlling circuit connected with each of the plurality of cells. The read back controlling circuit is configured to control the switching circuit so as to turn on a selected cell and supply a current from the current supplying circuit to the selected cell.

[0016] In some embodiments, the plurality of cells comprises cells in a number in a range of from 10,000 to 20 million. The plurality of cells may comprise from 1 million to 20 million cells, for example, 8 million, 9 million, 10 million, 11 million, 12 million of cells.

[0017] In some embodiments, each of the plurality of current comparator circuits is configured to be connected with two or more of the plurality of cells, and measure the current from the two or more of the plurality of cells. A number of the plurality of current comparator circuits may be less than that of the plurality of cells.

[0018] The first voltage comparator and the second voltage comparator provide and output digital signals indicating current capability of a cell based on a set of criteria. For example, in some embodiments, the first voltage comparator is configured to provide 0 as the first digital signal when the first voltage is lower than or equal to the second voltage, and provide 1 as the first digital signal when the first voltage is higher than the second voltage. The second voltage comparator is configured to provide 0 as the second digital signal when the first voltage is higher than or equal to the third voltage, and provide 1 as the second digital signal when the first voltage is lower than the third voltage.

[0019] The first voltage comparator and the second voltage comparator are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) selected from the group consisting of (0, 0), (0, 1), and (1, 0). A respective cell is within a specification and is configured to be used for synthesis only when the respective cell has the signal combination of (0, 0). If all or more of the cells show a signal combination (0, 0), the cells in the microarray chip have the desired uniformity. [0020] In some embodiments, each of the first capacitor, the second capacitor, and the third capacitor comprises one or more capacitors configured to be turned on or off so as to provide an adjustable capacitor. For example, each of the first capacitor, the second capacitor, and the third capacitor comprises four or five capacitors configured to be turned on or off.

[0021] The plurality of current comparator circuits are built-in circuits in the same microarray chip. The microarray chip is in a form of a rectangle, a square, a circle, or any other suitable shape, and have a flat top surface, where the anodes are reaction sites for synthesis of an oligomer. For example, in some embodiments, the microarray chip is in a rectangular shape. The plurality of cells are disposed in a central region of the microarray chip and the plurality of current comparator circuits are disposed on an edge of the microarray chip.

[0022] In another aspect, the present disclosure also provides a system comprising the microarray chip as described herein. The system may further comprise a controller, which is configured to be coupled with the microarray chip. The system may further comprise a display connected with the controller. The controller is configured to control testing current of each of the plurality of cells. The display is configured to display results including the first digital signal and the second digital signal. The first voltage comparator and the second voltage comparator are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) such as (0, 0), (0, 1), and (1, 0) while a cell having the signal combination of (0, 0) is desirable.

[0023] In another aspect, the present disclosure provides methods for testing or using the microarray chip or the system described herein. Such a method comprises steps including: supplying a current to a cell selected from the plurality of cells for testing current, activating a respective current comparator circuit in the plurality of current comparator circuits corresponding to the cell selected from the plurality of cells, supplying a reference current to a reference current source in the respective current comparator circuit, and outputting the first digital signal from the first voltage comparator and the second digital signal from the second voltage comparator.

[0024] In some embodiments, the first voltage comparator provides 0 as the first digital signal when the first voltage is lower than or equal to the second voltage, and provides 1 as the first digital signal when the first voltage is higher than the second voltage. The second voltage comparator provides 0 as the second digital signal when the first voltage is higher than or equal to the third voltage, and provides 1 as the second digital signal when the first voltage is lower than the third voltage. The first voltage comparator and the second voltage comparator are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal), which is selected from the group consisting of (0, 0), (0, 1), and (1, 0).

[0025] In some embodiments, the plurality of current comparator circuits are activated simultaneously for parallel testing of a corresponding number of cells selected from the plurality of cells.

[0026] In some embodiments, the method further comprises selecting a respective cell for synthesis. A cell is selected for synthesis only when the respective cell has the signal combination of (0, 0). The combinations (0, 1) and (1, 0) are considered as out of the desired specification while a cell provides a current too low or too high as required.

[0027] The microarray chip in the present disclosure may be made through complementary metal-oxide semiconductor (CMOS) process, and is a high throughput chip, which can include millions of cells. The microarray chip also includes the plurality of current comparator circuits as built-in structures, which convert current from a cell into voltage and output digital signals to present its current capability. The chip or the system described herein enables a method for testing current and quality of the cells with fast speed, and a method of using the microarray chip for synthesis with high quality. The testing results are also useful to guide future manufacturing of a microarray chip with better quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like reference numerals denote like features throughout specification and drawings.

[0029] FIG. 1 illustrates a reaction scheme for electrochemical parallel DNA synthesis including a deprotection step on an electrode array, which is a complementary metal-oxide- semiconductor (CMOS) type, in accordance with some embodiments.

[0030] FIG. 2 illustrates a reaction scheme showing a portion of a polypeptide or protein parallel electrochemical synthesis in some embodiments.

[0031] FIG. 3 shows a 3-D sectional diagram illustrating an exemplary array comprising a continuous circumferential electrode in accordance with some embodiments.

[0032] FIG. 4 is a sectional view illustrating an exemplary array in accordance with some embodiments, with only two continuous circumferential electrodes shown.

[0033] FIG. 5 is a sectional view illustrating an exemplary array of electrodes in row and column format comprising anodes and a surrounding line-based grid of counter electrodes (cathodes) in accordance with some embodiments.

[0034] FIG. 6 is a schematic diagram illustrating a system comprising a pad configured to be connected with an exterior current meter for measuring current from an electrode cell in an array.

[0035] FIG. 7 is a plot showing non-uniformity in current of electrode cells in an exemplary array in some embodiments.

[0036] FIG. 8 is a schematic diagram illustrating an exemplary microarray chip comprising a comparator circuit for measuring current from electrode cells in accordance with some embodiments.

[0037] FIG. 9 is a plan view of an exemplary chip comprising an array and comparator circuits for measuring current from electrode cells in an array in accordance with some embodiments.

[0038] FIG. 10 is a block diagram illustrating an exemplary system comprising the exemplary chip of FIG. 9 in accordance with some embodiments. [0039] FIG. 11 is a block diagram illustrating an exemplary controller comprising one or more processor and at least one tangible, non-transitory machine readable medium encoded with one or more programs, for measuring current of electrode cells in an array in accordance with some embodiments.

[0040] FIG. 12 is a diagram illustrating an exemplary capacitor having adjustable capacitance used in some embodiments.

[0041] FIG. 13 is a plot showing uniformity in current of electrode cells in an exemplary array in some embodiments.

[0042] FIG. 14 is a block diagram illustrating an exemplary synthesizer with the exemplary chip of FIG. 9 disposed therein for synthesizing oligomers or polymers in accordance with some embodiments.

[0043] FIG. 15 is a flow chart illustrating an exemplary method of using the system as described herein for measuring current of electrodes in an array in accordance with some embodiments.

DETAILED DESCRIPTION

[0044] This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

[0045] For purposes of the description hereinafter, it is to be understood that the embodiments described below may assume alternative variations and embodiments. It is also to be understood that the specific articles, compositions, and/or processes described herein are exemplary and should not be considered as limiting.

[0046] In the present disclosure the singular forms “a,” “an,” and “the” include the plural reference, and reference to a particular numerical value includes at least that particular value, unless the context clearly indicates otherwise. Thus, for example, a reference to “an electrode” is a reference to one or more of such structures and equivalents thereof known to those skilled in the art, and so forth. When values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. As used herein, “about X” (where X is a numerical value) preferably refers to ±10% of the recited value, inclusive. For example, the phrase “about 8” preferably refers to a value of 7.2 to 8.8, inclusive; as another example, the phrase “about 8%” preferably (but not always) refers to a value of 7.2% to 8.8%, inclusive. Where present, all ranges are inclusive and combinable. For example, when a range of “1 to 5” is recited, the recited range should be construed as including ranges “1 to 4”, “1 to 3”, “1-2”, “1-2 & 4-5”, “1-3 & 5”, “2-5”, and the like. In addition, when a list of alternatives is positively provided, such listing can be interpreted to mean that any of the alternatives may be excluded, e.g., by a negative limitation in the claims. For example, when a range of “1 to 5” is recited, the recited range may be construed as including situations whereby any of 1, 2, 3, 4, or 5 are negatively excluded; thus, a recitation of “1 to 5” may be construed as “1 and 3-5, but not 2”, or simply “wherein 2 is not included.” It is intended that any component, element, attribute, or step that is positively recited herein may be explicitly excluded in the claims, whether such components, elements, attributes, or steps are listed as alternatives or whether they are recited in isolation.

[0047] The term “microarray chip” used herein refer to a chip having a plurality of repeating units called cells or pixels arranged in an array, wherein each cell comprises an anode and a cathode, which comprise an electrically conductive material. Each electrode may have a sized at micrometer level (e.g., in a range of from 1 micron to 500 microns). A chip also includes circuits connected with the cells. Each chip may include thousands to millions of cells, and each cell is used for binding and/or synthesizing in parallel a chain of an oligomer or polymer such as DNA, RNA, or peptide. The binding and synthesis are in situ on a solid surface. Each cell can be selectively turned on or off. The microarray chip can be made on a substrate such as a semiconductor (e.g., silicon), glass or a combination thereof using CMOS technology. The “microarray chip” may be also referred as “microarray synthesis chip,” “microarray,” or “microarray device.”

[0048] Unless expressly indicated otherwise, the term “polymer” used herein is understood to encompass a molecule having at least two repeating units, including from dimer, trimer, tetramer, to a substance having millions of repeating units. Unless expressly indicated otherwise, the term “oligomer” used herein is understood to encompass a polymer having at least two repeating units, including from dimer, trimer, tetramer, to a substance having thousands of repeating units. The terms “oligomer” and “polymer” can be used in the present disclosure. [0049] The chip synthesis technology utilizes a microelectrode array system to generate current for the electrochemical reaction required to synthesize oligomers or polymers such as DNA and peptide. This technology platform is based on an electrode array on a chip. Such a chip having an electrode array can be called as a DNA synthesis chip or a peptide synthesis chip. Such an electrode array comprises a plurality of anodes and a plurality of cathodes. For example, as described in U.S. Patent No. 10,525,436, an electrode array may include continuous or discontinuous circumferential electrodes. The cathodes can be displayed as concentric rings (continuous) or as counter electrodes in a cross pattern (discontinuous) surrounding anodes.

[0050] The electrode arrays may be manufactured using semiconductor processing techniques. For example, a mixed signal process may be used to fabricate an active circuit to control the electrode cells in the array.

[0051] Have a good uniformity of current from each electrode cell of array can achieve a good quality of synthesized products such as DNA or peptide. The uniformity of current from each electrode needs to be monitored and controlled. The present disclosure provides a device or system and a method to measure the current from each electrode cell in a microarray by integrating additional built-in circuits to have a current test with improved efficiency for a chip for high throughput synthesis. Based on the testing results, a plurality of electrode cells are selected to be used for a synthesis process. The selected electrode cells provide a good uniformity of current during the synthesis process. In some other embodiments, the current measurement results can be used to provide guidance in controlling the quality of electrode cells in an array to be manufactured so that the electrode cells in an array provide uniformity in currents. [0052] In accordance with some embodiments, a synthesis chip such as a DNA synthesis chip or a peptide synthesis chip having a microarray is provided. For example, in a DNA synthesis chip, different sequences of DNA are synthesized on an array of electrodes. The number of electrodes varies from thousands to millions or more depending on the chip design. Each electrode is populated with a DNA of a specific sequence. A complementary metal-oxide semiconductor (CMOS) circuit is used to control activation and electrical behavior of the electrode cells to enable the DNA synthesis. Due to process variation in CMOS manufacturing processes, current output for each electrode cell might be different or an electrode may have malfunction. To test current uniformity of a chip before doing synthesis is necessary.

[0053] The present disclosure provides a microarray chip, a system comprising the microarray chip, and methods for testing or using the microarray chip. Such a microarray chip is used for electrochemical synthesis of an oligomer or polymer such as DNA, peptide, RNA, or any other suitable oligomers.

[0054] In FIGS. 1-14, like items are indicated by like reference numerals, and for brevity, descriptions of the structure, provided above with reference to the preceding figures, are not repeated. The method described in FIG. 15 is described with reference to the exemplary structure described in FIGS. 1-14.

[0055] The crux of an in-situ microarray fabrication technology (or called chip synthesis technology, or parallel synthesis technology) is the ability to perform a reaction to remove a protecting group (“deprotection reaction”) and a reaction of chemically adding a monomer unit (“coupling”) with spatial selectivity. The selectivity can be achieved by different methods, one of which is electrochemically generating acids (or protons) on selected electrodes, for example, for synthesis of oligonucleotides such as DNA. For example, in a microelectrode array such as a CMOS chip as described herein, protons (H⁺) can be produced at anodes. In a microarray, there are many electrode cells (or called electrochemical cells, or “pixels”). Each cell or pixel includes one respective anode and one respective cathode. A bias voltage can be selectively applied to some selected electrochemical cells.

[0056] Suitable chemicals can be used in electrochemical reactions to generate protons. One type of electrochemical reaction is based on quinone chemistry. For example, hydroquinone, which may be substituted, can be oxidized at an anode to generate protons. With loss of electrons, hydroquinone becomes benzoquinone. At a cathode, benzoquinone can gain electrons and become quinone dianions.

[0057] Protons are used to remove acid-labile protection groups before a reaction to add more monomer units. Protons and neutralizing reagents generated in opposite electrodes need to be confined separately to prevent cross-talk.

[0058] Referring to FIG. 1, a reaction scheme is illustrated for electrochemical parallel synthesis of an oligonucleotide such as DNA or RNA strands. The synthesis includes at a deprotection step on an electrode array. Such an array is a CMOS type in accordance with some embodiments. The array includes a plurality of electrochemical cells on a substrate 10. Each electrochemical cell 20 includes two electrodes: one anode 22 and a cathode (not shown in FIG. 1). The electrodes can be turned on and off on an individual basis.

[0059] FIG. 1 illustrates a selective deprotection reaction followed by a couple reaction occurred at one electrode (left anode). In FIG. 1, “O” stands for the oxygen atom on the matrix covering the electrode. “T” stands for the nucleotide T, “A” stands for the nucleotide A, and “x” is a protecting group. One of the steps in the oligonucleotide (DNA) synthesis on any solid surface is the deprotection of the C-5 hydroxyl group of the sugar ring. Any suitable protecting group can be used. For example, the protecting group can be a bulky “trityl moiety” such as dimethyltrityl (DMT) that can be removed in the presence of a trace of acid. Generation of acid at the anode removes the protecting group so that the next activated nucleotide (e.g., A as shown in FIG. 1) may be attached. By repeating steps above with different nucleotides as monomer units, specific oligomers or polymers can be formed.

[0060] The electrochemical reaction can only be confined and effective locally if enough protons (H⁺) is generated at an electrode functioning as an anode. Any bleeding of acid to the neighboring electrode will produce incorrect oligonucleotide sequences at that electrode. The net result would be not only sequence infidelity, but also oligomers that would be composed of various lengths.

[0061] Referring to FIG. 2, a reaction scheme is illustrated for a portion of parallel electrochemical synthesis of polypeptide or protein in some embodiments. Peptide synthesis is carried out in a similar manner as the oligonucleotide synthesis as illustrated in FIG. 1. In FIG. 2, “-NH2” represents amino group, “Leu” is leucine as an exemplary amino acid, and “tBoc” represents tert-butyloxycarbonyl as an exemplary blocking group (i.e., protecting group). In the first step shown in FIG. 2, at every electrode, leucine with the blocking group is grafted through a condensation reaction. The protecting group such as tBoc is acid-labile, and can be removed in the presence of an acid media. Acid generated at the electrodes or cells 20 such as anodes 22 removes the protecting group when the selected electrode or cells 20 is turned on. As illustrated in the second step of FIG. 2, two electrodes are turned on, the protecting group tBoc thereon are removed, and further reaction with more amino acids can be performed. A peptide chain can be synthesized by repeating steps with specific amino acids. As in the case of oligonucleotide synthesis, it is crucial that the acid produced should be contained within the area of the electrode. [0062] Referring to FIG. 3, an exemplary array comprising a continuous circumferential electrode in accordance with some embodiments is illustrated. As shown in FIG. 3, an inner electrode, which is one central electrode, is an anode 22 for generating protons electrochemically. A circumferential electrode is a cathode 24, and is used as a counter electrode to contain the acid and neutralize the electrochemically generated reagents. A buffer may or may not need to be used. The inner and outer electrodes are separated by insulated gap material. The gap region is called a diffusion zone 23. In some embodiments, a porous reaction layer 25 covers both electrodes and the gap region.

[0063] For DNA synthesis, a reactive chemical such as protons and a reagent which neutralizes that chemical such as deprotonated hydroquinone are produced at anodes and circumferential counter electrodes, respectively. These protons are used to produce the desired reaction and their spatial containment is important to specific sequence formation. By biasing counter electrodes, when a selected anode 22 is turned on and generates acid (protons) electrochemically, the circumferential electrode, i.e., the cathode 24, is biased and generate a base electrochemically. The base generated will act to neutralize acids diffusing away from the region of the selected (anode) electrode. Through surrounding the selected anode with the counter electrode, a wall 27 of concentrated highly reactive neutralizing agent is formed to contain the desired reactant to the specific area of the active electrodes and its overlaying porous reaction layer.

[0064] Referring to FIG. 4, an exemplary array 100 in accordance with some embodiments is illustrated. Only two sets of continuous circumferential electrodes are shown for the purpose of illustration only. The exemplary array 100 provided in the present disclosure may include a suitable numbers of a set of electrodes or cells or pixels. Each cell may have a size at micrometer level, for example, in a range of from 1 micron to 500 microns. For example, the diameter labeled as “a” in cathode 24 may be in an arrange of from 10 microns to 150 microns. The width “b” in cathode 24 may be in a range of from 1 micron to 50 microns. Each cell 20 or pixel includes two electrodes: one anode 22 and a cathode 24. In some embodiments, each anode 22 is one central electrode, while the cathode 24 may comprise a ring, which is an extension of a neighboring electrode. The electrodes are made of a conductive material such as aluminum, platinum, gold, carbon, or any other metal or conductive material.

[0065] In some embodiments, the exemplary array 100 comprising continuous circumferential electrodes is fabricated using a CMOS technology. This array or device utilizes alternating array of circular active electrodes (i.e., anodes 22) and continuous circumferential counter electrodes (i.e., cathodes 24). In such a CMOS process, the semiconductor silicon wafer is fabricated using aluminum wiring and electrodes and then “post-processed” by sputtering another metal, for example, Pt or Au in the regions marked as electrodes 22 and 24. The post process masks the electrodes 22 and 24 with platinum and passivation opening 26 and 28 for this device were modified to define a circumferential cathode around each anode.

[0066] Referring to FIG. 5, another exemplary array comprising electrodes in row and column format is illustrated. The electrodes comprise anodes 22 and a surrounding line-based grid of counter electrodes (cathodes 24). This array can be referred to as the “tic-tac-toe” configuration.

[0067] Referring to FIG. 6, an exemplary array 102 having a testing pad 53 in some embodiments is illustrated. The exemplary array 102 is similar to the exemplary array 100 except its testing configuration. The exemplary array can be in a chip for synthesis of DNA or peptide. In FIG. 6, only three electrodes in three cells 20, which are anodes 22, are shown for the purpose of illustration only. The array 102 may have a suitable number of cells, i.e., pairs of an anode and a cathode. In some embodiments, the array 102 has 10,000 cells. The array 102 comprises current supplying circuits 30 and switching circuits 40. The current supplying circuits 30 are configured to supply current from external sources to each cell 20 having electrodes. The switching circuits 40 (marked as A, B, and C in FIG. 6) are configured to turn on the electrodes or cells 20 in selected cells. The array 102 also comprises read back controlling circuits 52. The read back controlling circuits 52 are configured to control the switching circuits 40. Each electrode cell has a respective set of circuits including a current supplying circuit 30, a switching circuit 40, and a read back controlling circuit 52.

[0068] In the array 102, the testing pad 53, which also include integrated circuits, is connected with the read back controlling circuits 52, and is configured to be connected with an exterior current meter for measuring current from a cell 20 having electrodes in the array. The pad 53 may be a component of the array 102 or external to the array 102, and is configured for current read back from the electrodes. In a method of testing current from an electrode cell, each electrode cell is turned on sequentially through the switching circuits 40 and the read back controlling circuits 52. The current from such a tumed-on cell is measured from the pad 53 by an external current meter. This is referred as 1 bit current read-out.

[0069] When the current from one electrode cell is measured by an external current meter, it takes about 10 milliseconds (ms) for 1 bit current read-out. For 10,000 set of electrodes, the test time for the current read-out is about 100s in total. But a high throughput array as provided herein may have a large number of electrode cells. For example, a high throughput array may have about 10 million electrode cells. So the test time could be 100,000 seconds (i.e., about 27.8 hours). The cost associated with such testing is extreme high. It is not efficient for high throughput synthesis chip.

[0070] In addition, the uniformity of an array needs to be improved. Referring to FIG. 7, the exemplary array 102, which has 10,000 cells in some embodiments, show variation and distribution of currents from different cells under the same conditions. The variations in the current results indicated that the cells may be uniform and have different capabilities in supplying currents for the chemical reactions performed on the array. The non-uniformity may be caused by differences in cell structures and/or material conductivity. However, uniform currents are needed for synthesis of DNA or peptide on an array. It is important to provide a high throughput array, which may have about 10 million electrode cells in some embodiments, with uniform cells. The cells with current capabilities outside a desired range should not be used for synthesis. On the other hand, the current testing results can be used to guide the manufacturing process for making a high throughput array (or chip) with uniform quality.

[0071] In accordance with some embodiments, the present disclosure further provides a circuit for measuring current of cells in a high throughput microarray chip for synthesis and a resulting microarray chip. The microarray chip is configured to be used for parallel synthesis of oligomers such as DNA, RNA, and peptides on selected cells.

[0072] Referring to FIG. 8, an exemplary microarray chip 140 is illustrated. Such a microarray chip 140 comprises two portions including the array portion 110 as the first portion and a plurality of current comparator circuits 120 as the second portion.

[0073] The exemplary microarray chip 140 comprises an electrode array 100. As described in FIGS. 1-5, the electrode array 100 comprises a plurality of cells. Each of the plurality of cells 20 comprises an anode 22 and a cathode 24. Each of the anode 22 and the cathode 24 comprises an electrically conductive material. In each cell, the anode 22 may be a central electrode and the cathode 24 may be a circumferential electrode or a grid surrounding the anode.

[0074] In some embodiments, the array portion 110 of the microarray chip 140 further comprises a current supplying circuit 30, a switching circuit 40, and a read back controlling circuit 52 connected with each of the plurality of cells. The read back controlling circuit 52 is configured to control the switching circuit 40 so as to turn on a selected cell and supply a current from the current supplying circuit 30 to the selected cell 20.

[0075] In FIG. 8, only three electrodes in three cells 20, which are anodes 22, are shown for the purpose of illustration only. The array 100 may have a suitable number of cells, i.e., pairs of an anode 22 and a cathode 24. The plurality of cells 20 comprises cells in a number in a range of from 10,000 to 20 million. The plurality of cells may comprise from 1 million to 20 million cells, for example, 8 million, 9 million, 10 million, 11 million, 12 million, or any suitable number of cells.

[0076] The microarray chip 140 further comprises a plurality of current comparator circuits 120. Each current comparator circuit 120 comprises a first current mirror 51 connected with a reference current source 50, and a first capacitor 62 (labelled as F in FIG. 8) connected with the first current mirror 51. Each current comparator circuit 120 also comprises a second current mirror 54 configured to be connected with one of the plurality of cells 20, and a second capacitor 64 (labeled as G) and a third capacitor 66 (labeled as H) connected with the second current mirror 54. The second capacitor 64 and the third capacitor 66 are connected in parallel, and are connected with the second current mirror 54 in series. [0077] A current mirror is a circuit designed to copy a current through a source such as the reference current source 50 or a cell 20 and keep the output current constant. The capacitors 60 used, including the first capacitor 62 for a reference, and the second and the third capacitors 64 and 66, are used to discharge and convert a current to a voltage for testing. The three capacitors 60 are grounded through a grounding structure 76.

[0078] Each current comparator circuit 120 further comprises two voltage comparator 70 including a first voltage comparator 72 and a second voltage comparator 74. The components described herein and shown in FIG. 8 are collected with conductive wires 80. The first voltage comparator 72 (labelled as I in FIG. 8) is connected with the first capacitor 62 and the second capacitor 64, and is configured to compare the first voltage (Vf) from the first capacitor 62 (i.e., the reference voltage) and the second voltage (Vg) from the second capacitor 64 and provide a first digital signal selected from 0 and 1. The second voltage comparator 74 (labelled as J in FIG. 8) is connected with the first capacitor 62 and the third capacitor 66, and is configured to compare the first voltage (Vf) from the first capacitor 62 and the third voltage (Vh) from the third capacitor 66 and provide a second digital signal selected from 0 and 1.

[0079] As shown in FIG. 8, the first capacitor 62 is connected to the positive terminal of the first voltage comparator 72 and is connect to the negative terminal of the second voltage comparator 74. These connections are for illustration only. As the voltage at the terminal with + sign of a comparator 72 or 74 is larger than the voltage at the terminal with -sign of the comparator 72 or 74, then the output of the comparator is “1”, otherwise is “0”.

[0080] In FIG. 8, only one current comparator circuit 120 connected with three cells 20 is shown for the purpose of illustration only. In some embodiments, each of the plurality of current comparator circuits 120 is configured to be connected with two or more of the plurality of cells 20, and measure the current from the two or more of the plurality of cells. A number of the plurality of current comparator circuits 120 may be less than that of the plurality of cells. For example, in some embodiments, the exemplary microarray chip 140 may include 8-10 million cells 20. For example, such a chip may include about a number of 1,000 to 20,000 current comparator circuits 120. Each current comparator circuit 120 may be configured to test current from 10,000 to 60,000 cells. These numbers are for illustration only.

[0081] The first voltage comparator 72 and the second voltage comparator 74 provide and output digital signals indicating current capability of a cell 20 based on a set of criteria. For example, in some embodiments, the first voltage comparator 72 is configured to provide 0 as the first digital signal when the first voltage (Vf) is lower than or equal to the second voltage (Vg), and provide 1 as the first digital signal when the first voltage (Vf) is higher than the second voltage (Vg). The second voltage comparator 74 is configured to provide 0 as the second digital signal when the first voltage (Vf) is higher than or equal to the third voltage (Vh), and provide 1 as the second digital signal when the first voltage (Vf) is lower than the third voltage (Vh). [0082] These criteria are represented as follows:

First voltage comparator 72 outputs: 0 when Vf <=Vg; or

1 when Vf > Vg.

Second voltage comparator 74 outputs: 0 when Vf >=Vh; or

1 when Vf < Vg.

[0083] The first voltage comparator 72 and the second voltage comparator 74 are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal), which is selected from the group consisting of (0, 0), (0, 1), and (1, 0). A combination of (1, 1) may not exist. A respective cell 20 is within a specification and can be used for synthesis only when the respective cell has the signal combination of (0, 0). If all or more of the cells show a signal combination (0, 0), the cells in the microarray chip have the desired uniformity.

[0084] So as described herein, when a built-in current comparator circuit 120, no external current meter is needed. The built-in current compared circuit transfers current to voltage and use digital signal to output result. The speed of digital signal operation can reach to nanoseconds (nsec) and test time can be reduced dramatically. As the build-in current test is performed, there are other testing involved such as open/short test and initialization of the build-in circuit. With a built-in circuit, which is a current comparator circuit in some embodiments, the testing time can be significantly reduced. For example, for a synthesis microarray chip with 10 million electrode cells, the time for testing current of the electrodes was reduced to about 300 seconds. So the built-in current comparator circuit reduces test time for a high throughput synthesis chip such as one comprising 10 million or above cells (electrode pairs). Such a microarray chip 140 including comparator circuit 120 has been made by the inventors, and can be used for synthesis of oligomers such as DNA and peptide. [0085] The built-in current comparator circuit 120 uses a current from a reference current source 50 to compare with current of each electrode cell 20. First, the reference source current is mirrored by the first current mirror 51 (labelled as D). The mirror current (Iref) is used for the discharge of the first capacitor 62 (labelled as F). The current of an electrode cell 20 (Icell) is duplicated to two paths by the second current mirror 54 (labeled as E). Icell is used for the discharge of the second capacitor 64 (labeled as G) and the third capacitor 66 (labeled as H). [0086] Before discharge, these capacitors 60 are pre-charged to Vdd and then released. Additional circuits and switches (not shown) are configured to pre-charge each capacitor 60 to Vdd. The capacitance values of the first, the second, and the third capacitors are different and adjustable. In some embodiments, for an example, the ratio for the capacitance of each capacitor, i.e., Cf /Cg/ Ch is set as 1/1.05/0.95. After a period of discharged by the reference current and the electrode cell current, the voltage of each capacitor will drop based on the capacitance of each capacitor. The voltage of a larger capacitor will drop less compared to the r voltage of a smaller capacitor based on the formula (1): V=J₀ i dt/C ~ t*I/C.

[0087] The voltage and the capacitances of the capacitors 60 are represented as follows: Vf : the voltage of the first capacitor 62 (i.e., F), Cf: the capacitance of the first capacitor 62,

Vg: the voltage of the second capacitor 64 (i.e., G), Cg: the capacitance of the second capacitor 64, Vh: the voltage of the third capacitor 66 (i.e., H), and Ch: the capacitance of the third capacitor 66.

[0088] The reference current may be selected as the desired current for each electrochemical reaction, and is the same as the desired current (i.e., a sample current) for each cell. In normal situation, current from each path should be closed to the reference current.

[0089] In some embodiments, it is assumed that Icell is in the range between 0.96Iref and 1.04Iref.

[0090] After a period, t, the voltage of each capacitor can be calculated as shown below. The ratio of Cg : Cf : Ch is set as 1.05: 1: 0.95 in some embodiments.

[0091] In the lower side, it is assumed that the cell current is about ~ 0.96Iref. After a period (t), voltage of each capacitor can be calculated as follows: [0092] Vf = Vdd -t*Iref/Cf, [0093] Vg = Vdd - t*Icell/Cg = Vdd -t*0.96Iref/l .05 Cf, and

[0094] Vh = Vdd - t*Ircell/Ch = Vdd -t*0.96Iref/0.95 Cf.

[0095] Icell should be the same as Ircell. Therefore, the order in a decreasing order is: Vg > Vf > Vh.

[0096] In the higher side of Icell being in the range between 0.96Iref and 1.04Iref, it is assumed that the cell current is about ~ 1.04 Iref. After a period (t), voltage of each capacitor can be calculated as follows:

Vf = Vdd -t*Iref/Cf,

Vg = Vdd - t*Icell/Cg = Vdd -t*1.04Iref/1.05 Cf, and

Vh= Vdd - t*Ircell/Ch = Vdd -t*1.04Iref/0.95 Cf.

[0097] Therefore, the order in a decreasing order is: Vg > Vf > Vh.

[0098] As described above, the criteria for outputting digital signals are represented as follows:

First voltage comparator 72 outputs: 0 when Vf <=Vg; or

1 when Vf > Vg.

Second voltage comparator 74 outputs: 0 when Vf >=Vh; or

1 when Vf < Vg.

[0099] For voltage comparison, the first voltage comparator 72 (labeled as I) outputs 0 as the second digital signal because Vg> Vf. The second voltage comparator 74 (labeled as J) outputs 0 as the first digital signal because Vf> Vh.

[0100] If the value of Icell is within +-5%, based on the set capacitance ratio of capacitors, the voltage comparators 70 output as a signal combination (0, 0) for the two voltage comparators (I, J).

[0101] In another scenario that the Icell is 5% higher than Iref, for example, Icell being ~ 1.08Iref, after a period (t), voltage of each capacitor can be calculated as follows:

Vf = Vdd -t*Iref/Cf,

Vg= Vdd - t*Icell/Cg = Vdd -t*1.08Iref/1.05 Cf, and

Vh= Vdd - t*Ircell/Ch = Vdd -t*1.08Iref/0.95Iref.

[0102] Therefore, the order in a decreasing order is: The Vf> Vg > Vh.

[0103] For voltage comparison, the first voltage comparator 72 (labeled as I) outputs 1 as the second digital signal because Vf> Vg. The second voltage comparator 74 (labeled as J) outputs 0 as the first digital signal because Vf> Vh. In this scenario when the value of Icell output from a cell 20 is 5% higher than Iref, the voltage comparators output as a signal combination (1, 0) for the two voltage comparators (I, J).

[0104] In another scenario that the Icell is 5% lower than Iref, for example Icell ~ 0.92Iref, after a period (t), voltage of each capacitor can be calculated as follows:

Vf= Vdd -t*Iref/Cf,

Vg= Vdd - t*Icell/Cg=Vdd -t*0.92ref/1.05 Cf, and

Vh= Vdd - t*Ircell/Ch=Vdd -t*0.92Iref/0.95 Cf

[0105] Therefore, the order in a decreasing order is: Vg> Vh > Vf.

[0106] For voltage comparison, the first voltage comparator 72 (labeled as I) outputs 0 as the second digital signal because Vg > Vf. The second voltage comparator 74 (labeled as J) outputs 1 as the first digital signal because Vh> Vf. In this scenario when the value of Icell output from a cell 20 is 5% lower than Iref, the voltage comparators output as a signal combination (1, 0) for the two voltage comparators (I, J).

[0107] With the setting for capacitance value of capacitors, the Icell current can be transferred to digital signal as within specification (0, 0), higher than the specification (1,0), or lower than the specification (0, 1). The digital signal could be read out in much high speed. The +7-5% is a specification for illustration. It can be adjusted to other percentages. The capacitance ratio can be also set in another suitable ratio. Other Cf/Cg/Ch ratios can be used. Other percentages other than 5% can be considered as within a specification. These limits can be adjusted based on yield performance during fabrication process.

[0108] The plurality of current comparator circuits 120 are built-in circuits in the same microarray chip. The microarray chip 140 is in a form of a rectangle, a square, a circle, or any other suitable shape, and have a flat top surface, where the anodes are reaction sites for synthesis of an oligomer.

[0109] Referring to FIG. 9, an exemplary design, which has been fabricated and used for DNA synthesis, is illustrated. High quality of synthesis performance has been achieved. For example, in some embodiments, the microarray chip 140 is in a rectangular shape. Such a microarray chip is a CMOS chip built on a substrate 10. The array portion 110 comprising the plurality of cells 20 is disposed in a central region of the microarray chip 140 and the plurality of current comparator circuits 120 are disposed on an edge 121 of the microarray chip 140. Other conductive pads 123 (shown as blank pads in FIG. 9) may be disposed among the plurality of current comparative circuits 120, and may be treated as different grounds during synthesis when the microarray chip 140 is used for synthesis. The microarray chip 140 may include other conductive pad 84 for electrical connections or other testing purposes. One or more of the plurality of current comparator circuits 120 may be included in one testing pad as shown in FIG. 9. Pads 84 may be other functional pads needed, for example, for SPI communication, current read back, and power/ground pad.

[0110] Referring to FIG. 10, an exemplary system 150 comprising the microarray chip 140 as described herein is illustrated. The system 150 may further comprise a controller 130, which is configured to be coupled with the microarray chip. The system 150 may further comprise a display 160 connected with the controller 130. The display 160 may be a part of the controller 130. The controller 130 is configured to control testing current of each of the plurality of cells 20. The display 160 is configured to display results including the first digital signal and the second digital signal. The first voltage comparator 72 and the second voltage comparator 74 are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) such as (0, 0), (0, 1), and (1, 0) while a cell having the signal combination of (0, 0) is desirable.

[0111] Referring to FIG. 11, a block diagram illustrates an exemplary controller 130 comprising one or more processor 131 and at least one tangible, non-transitory machine readable medium encoded with one or more programs, for measuring current of electrode cells 20 and using the microarray chip 140 the results in accordance with some embodiments.

[0112] Referring to FIG. 11, the controller 130 comprises one or more processors 131 and at least one tangible, non-transitory machine readable medium encoded with one or more programs configured to perform steps as described herein, for example, those described in FIG. 15. The controller 130, the processor 131, and/or the program 132 may be an external device to the microarray chip 140, or be an internal device inside the microarray chip 140.

[0113] The processor 131 may include a central control 134, which includes a parameter input module 136, a model module 138, a parameter control module 142, and information and instruction output module 144. The parameter input module 136 coordinates with the voltage comparator circuits 70, to read the data from the comparator circuits 70. The parameter control module 142 determines the digital signals to be output based on the criteria described, and also coordinates with the microarray chip 140, for example, provide information regarding the cells within the specification and to be used for a synthesis. Together with the one or more programs 132, the model module 138, which includes the criteria, is configured to process the data from the parameter input module 136 to provide information and instruction to the parameter control module 142 and the information and instruction output module 144. The processors 131 may be optionally connected with one or more displays 160 for displaying the information and instructions from module 144 and to an operator. The controller 130 with the programs 132 and the processor 131 are configured to perform the methods as described herein. As described in FIG. 15, in some embodiments, the controller 130 is configured to perform the steps described herein.

[0114] In some embodiments, each of the first capacitor 62, the second capacitor 64, and the third capacitor 66 comprises one or more capacitors 60 configured to be turned on or off so as to provide an adjustable capacitor. Referring to FIG. 12, such a capacitor 122 is illustrated. For example, each of the first capacitor 62, the second capacitor 64, and the third capacitor 66 comprises four or five capacitors configured to be turned on or off. One of the capacitors 60 may include a switch 55 and can be turned on or off through the switch 55. The adjustable capacitor can be achieved by turning on different capacitors (labelled as “ 1 ~ 4”) to have different capacitance of capacitor. The adjustable capacitor 122 can be used as any of the first capacitor 62, the second capacitor 64, and the third capacitor 66 as described in FIG. 8.

[0115] Based on the results obtained, specific electrodes with tighten current distribution can be chosen for synthesis to achieve the better quality of synthesized DNA. On the other hand, the results can used to guide the manufacturing process so that a good chip is made.

[0116] Referring to FIG. 13, a microarray chip 140 with uniformity in the electrode cells 20 can be fabricated in some embodiments. This exemplary microarray chip 140 includes 8 million cells. The vast majority of the cells are configured to supply current in a desired range, for example, within variation within a range from -13.2% to 12.4% deviated from a standard current.

[0117] Referring to FIG. 14, an exemplary synthesizer 170 is illustrated. The exemplary microarray chip 140 of FIG. 8 is disposed therein for synthesizing oligomers or polymers in accordance with some embodiments. Only the cells within a specification are selected to be used for the synthesis. The synthesizer 170 may include wires 172 connected with an external current source, a control dial 174, and chemical supplying devices 175.

[0118] Referring to FIG. 15, an exemplary method 200 for using or testing the microarray chip or the system as described herein. Such a method 200 comprises steps including steps 202, 204, 206, 208 and 210.

[0119] At step 202, a current (a cell current) is supplied to a cell selected from the plurality of cells 20 for testing current.

[0120] At step 204, a respective current comparator circuit 120 in the plurality of current comparator circuits corresponding to the cell selected from the plurality of cells is activated.

[0121] At step 206, a reference current is provided to a reference current source in the respective current comparator circuit 120.

[0122] At step 208, the first digital signal from the first voltage comparator and the second digital signal from the second voltage comparator are output.

[0123] In some embodiments, the first voltage comparator 72 provides 0 as the first digital signal when the first voltage is lower than or equal to the second voltage, and provides 1 as the first digital signal when the first voltage is higher than the second voltage. The second voltage comparator 74 provides 0 as the second digital signal when the first voltage is higher than or equal to the third voltage, and provides 1 as the second digital signal when the first voltage is lower than the third voltage. The first voltage comparator 72 and the second voltage comparator 74 are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal), which is selected from the group consisting of (0, 0), (0, 1), and (1, 0).

[0124] In some embodiments, the plurality of current comparator circuits are activated simultaneously for parallel testing of a corresponding number of cells selected from the plurality of cells.

[0125] At step 210, a respective cell is selected for synthesis. A cell is selected for synthesis only when the respective cell has the signal combination of (0, 0). The combinations (0, 1) and (1, 0) are considered as out of the desired specification while a cell provides a current too low or too high as required. Such information is stored in the controller. All the measurements described above are done when the microarray chip in a dry state. It is moved into the synthesis stage, liquid chemicals are added. So the microarray chip will be in a wet state.

[0126] The methods and system described herein may be at least partially embodied in the form of computer-implemented processes and apparatus for practicing those processes. The disclosed methods may also be at least partially embodied in the form of tangible, non-transient machine readable storage media encoded with computer program code. The media may include, for example, RAMs, ROMs, CD-ROMs, DVD-ROMs, BD-ROMs, hard disk drives, flash memories, or any other non-transient machine-readable storage medium, or any combination of these mediums, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the method. The methods may also be at least partially embodied in the form of a computer into which computer program code is loaded and/or executed, such that, the computer becomes an apparatus for practicing the methods. When implemented on a general-purpose processor, the computer program code segments configure the processor to create specific logic circuits. The methods may alternatively be at least partially embodied in a digital signal processor formed of application specific integrated circuits for performing the methods.

[0127] The microarray chip, the system, and the methods provided in the present disclosure have significant advantages. The microarray chip in the present disclosure may be made through complementary metal-oxide semiconductor (CMOS) process, and is a high throughput chip, which can include millions of cells. The microarray chip also includes the plurality of current comparator circuits as built-in structures, which convert current from a cell into voltage and output digital signals to present its current capability. The chip or the system described herein enables a method for testing current and quality of the cells with fast speed, and a method of using the microarray chip for synthesis with high quality. The design for testing is beneficial as it is applied to a high-throughput microarray chip including millions of electrode pairs, and saves test time from couple days to couple minutes. The testing results are also useful to guide future manufacturing of a microarray chip with better quality.

[0128] Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.

Claims

What is claimed is:

1. A microarray chip, comprising: an electrode array comprising a plurality of cells, each of the plurality of cells comprising an anode and a cathode, each of the anode and the cathode comprising an electrically conductive material; and a plurality of current comparator circuits, each of the plurality of current comparator circuits comprising: a first current mirror connected with a reference current source; a first capacitor connected with the first current mirror; a second current mirror configured to be connected with one of the plurality of cells; a second capacitor and a third capacitor connected with the second current mirror, the second capacitor and the third capacitor connected in parallel; a first voltage comparator connected with the first capacitor and the second capacitor and configured to compare the first voltage from the first capacitor and the second voltage from the second capacitor and provide a first digital signal selected from 0 and 1 ; and a second voltage comparator connected with the first capacitor and the third capacitor and configured to compare the first voltage from the first capacitor and the third voltage from the third capacitor and provide a second digital signal selected from 0 and 1.

2. The microarray chip of claim 1, wherein the microarray chip is configured to be used for parallel synthesis of an oligomer selected from the group consisting of DNA, RNA and peptide on selected cells.

3. The microarray chip of claim 1, wherein the anode is a central electrode and the cathode is a circumferential electrode or a grid surrounding the anode.

4. The microarray chip of claim 1, further comprising a current supplying circuit, a switching circuit, and a read back controlling circuit connected with each of the plurality of cells, wherein the read back controlling circuit is configured to control the switching circuit so as to turn on a selected cell and supply a current from the current supplying circuit to the selected cell.

5. The microarray chip of claim 1, wherein each of the plurality of current comparator circuits is configured to be connected with two or more of the plurality of cells, and measure the current from the two or more of the plurality of cells.

6. The microarray chip of claim 1, wherein the first voltage comparator is configured to provide 0 as the first digital signal when the first voltage is lower than or equal to the second voltage, and provide 1 as the first digital signal when the first voltage is higher than the second voltage.

7. The microarray chip of claim 6, wherein the second voltage comparator is configured to provide 0 as the second digital signal when the first voltage is higher than or equal to the third voltage, and provide 1 as the second digital signal when the first voltage is lower than the third voltage.

8. The microarray chip of claim 7, wherein the first voltage comparator and the second voltage comparator are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) selected from the group consisting of (0, 0), (0, 1), and (1, 0).

9. The microarray chip of claim 8, wherein a respective cell is within a specification and is configured to be used for synthesis only when the respective cell has the signal combination of (0, 0).

10. The microarray chip of claim 1, wherein each of the first capacitor, the second capacitor, and the third capacitor comprises one or more capacitors configured to be turned on or off so as to provide an adjustable capacitor.

11. The microarray chip of claim 10, wherein each of the first capacitor, the second capacitor, and the third capacitor comprises four capacitors configured to be turned on or off.

12. The microarray chip of claim 1, wherein the plurality of cells comprises cells in a number in a range of from 10,000 to 20 million.

13. The microarray chip of claim 1, wherein the plurality of cells comprises from 1 million to 20 million cells.

14. The microarray chip of claim 1, wherein a number of the plurality of current comparator circuits is less than that of the plurality of cells.

15. The microarray chip of claim 1, wherein the plurality of cells are disposed in a central region of the microarray chip and the plurality of current comparator circuits are disposed on an edge of the microarray chip.

16. A system, comprising the microarray chip of claim 1.

17. The system of claim 16, further comprising a controller configured to be coupled with the microarray chip, and a display connected with the controller, wherein the controller is configured to control testing current of each of the plurality of cells, and the display is configured to display results including the first digital signal and the second digital signal.

18. The system of claim 16, wherein the first voltage comparator and the second voltage comparator are configured to output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) selected from the group consisting of (0, 0), (0, 1), and (1, 0).

19. A method for testing or using the microarray chip of claim 1, comprising: supplying a current to a cell selected from the plurality of cells for testing current; activating a respective current comparator circuit in the plurality of current comparator circuits corresponding to the cell selected from the plurality of cells; supplying a reference current to a reference current source in the respective current comparator circuit; and outputting the first digital signal from the first voltage comparator and the second digital signal from the second voltage comparator.

20. The method of claim 19, wherein the first voltage comparator provides 0 as the first digital signal when the first voltage is lower than or equal to the second voltage, and provides 1 as the first digital signal when the first voltage is higher than the second voltage.

21. The method of claim 20, wherein the second voltage comparator provides 0 as the second digital signal when the first voltage is higher than or equal to the third voltage, and provides 1 as the second digital signal when the first voltage is lower than the third voltage.

22. The method of claim 19, wherein the first voltage comparator and the second voltage comparator output a signal combination indicating a current capability of a respective cell in a format of (the first digital signal, the second digital signal) selected from the group consisting of (0, 0), (0, 1), and (l, 0).

23. The method of claim 19, wherein the plurality of current comparator circuits are activated simultaneously for parallel testing of a corresponding number of cells selected from the plurality of cells.

24. The method of claim 19, further comprising selecting a respective cell for synthesis only when the respective cell has the signal combination of (0, 0).