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EP4227809A4 - Procédé de détection d'erreur et dispositif associé - Google Patents

Procédé de détection d'erreur et dispositif associé Download PDF

Info

Publication number
EP4227809A4
EP4227809A4 EP21885232.5A EP21885232A EP4227809A4 EP 4227809 A4 EP4227809 A4 EP 4227809A4 EP 21885232 A EP21885232 A EP 21885232A EP 4227809 A4 EP4227809 A4 EP 4227809A4
Authority
EP
European Patent Office
Prior art keywords
detection method
error detection
related device
error
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21885232.5A
Other languages
German (de)
English (en)
Other versions
EP4227809A1 (fr
Inventor
Zhe TAO
Ge SHEN
Jianlong CAO
Ming Wang
Rui Fang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Yinwang Intelligenttechnologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP4227809A1 publication Critical patent/EP4227809A1/fr
Publication of EP4227809A4 publication Critical patent/EP4227809A4/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3668—Testing of software
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
EP21885232.5A 2020-10-29 2021-10-28 Procédé de détection d'erreur et dispositif associé Pending EP4227809A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011180288.7A CN114428694A (zh) 2020-10-29 2020-10-29 一种错误检测方法及相关装置
PCT/CN2021/126873 WO2022089505A1 (fr) 2020-10-29 2021-10-28 Procédé de détection d'erreur et dispositif associé

Publications (2)

Publication Number Publication Date
EP4227809A1 EP4227809A1 (fr) 2023-08-16
EP4227809A4 true EP4227809A4 (fr) 2024-04-17

Family

ID=81310326

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21885232.5A Pending EP4227809A4 (fr) 2020-10-29 2021-10-28 Procédé de détection d'erreur et dispositif associé

Country Status (4)

Country Link
US (1) US12174254B2 (fr)
EP (1) EP4227809A4 (fr)
CN (1) CN114428694A (fr)
WO (1) WO2022089505A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12099791B1 (en) * 2021-09-30 2024-09-24 Cadence Design Systems, Inc. Method, product, and system for rapid sequence classification through a coverage model
US12141512B1 (en) 2021-09-30 2024-11-12 Cadence Design Systems, Inc. Method, product, and system for universal verification methodology (UVM) sequence selection using machine learning
US12038477B1 (en) 2021-09-30 2024-07-16 Cadence Design Systems, Inc. Method, product, and system for protocol state graph neural network exploration
US12242784B1 (en) 2021-09-30 2025-03-04 Cadence Design Systems, Inc. Method, product, and system for a sequence generation ecosystem using machine learning

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150161323A1 (en) * 2013-12-06 2015-06-11 Robert Bosch Gmbh Method for checking a hardware-configurable logic circuit for faults
US20190303260A1 (en) * 2018-03-29 2019-10-03 Arm Ltd. Device, system and process for redundant processor error detection

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EP0729097A1 (fr) * 1995-02-07 1996-08-28 Sun Microsystems, Inc. Méthode et appareil de contrÔle d'accès à la mémoire pendant l'exécution d'un programme à fils multiples
US6715062B1 (en) 2000-07-26 2004-03-30 International Business Machines Corporation Processor and method for performing a hardware test during instruction execution in a normal mode
WO2008001818A1 (fr) * 2006-06-30 2008-01-03 Japan Science And Technology Agency dispositif de conversion, procédé de conversion, programme et support d'enregistrement
US7836372B2 (en) * 2007-06-08 2010-11-16 Apple Inc. Memory controller with loopback test interface
US8127192B2 (en) * 2007-07-18 2012-02-28 International Business Machines Corporation Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode
CN103430155B (zh) * 2011-01-17 2015-11-25 明导公司 具有与模式无关的测试访问机制的测试调度
US20140046615A1 (en) * 2012-08-13 2014-02-13 Texas Instruments Incorporated Test Case Crash Recovery
GB2514402A (en) * 2013-05-23 2014-11-26 Ibm Method and test environment for testing an integrated circuit
KR102352068B1 (ko) * 2014-08-04 2022-01-17 인텔 코포레이션 복수의 프로세서를 포함하는 기능 안전이 있는 애플리케이션을 위한 전자 시스템에서 프로그램을 실행하는 방법, 대응되는 시스템 및 컴퓨터 프로그램 제품
JP6266137B2 (ja) 2015-07-09 2018-01-24 古河電気工業株式会社 金属微粒子含有組成物
US10248484B2 (en) 2017-02-21 2019-04-02 Intel Corporation Prioritized error-detection and scheduling
US11408934B2 (en) 2017-12-22 2022-08-09 Nvidia Corporation In system test of chips in functional systems
CN113167831B (zh) 2018-10-10 2024-09-03 辉达公司 在已部署的汽车平台上执行自测的测试系统
US11693753B2 (en) 2018-10-15 2023-07-04 Nvidia Corporation Enhanced in-system test coverage based on detecting component degradation
CN109376090A (zh) * 2018-10-25 2019-02-22 京信通信系统（中国）有限公司 软件自动测试方法及装置
CN109490753B (zh) 2018-11-13 2020-12-08 吉林大学 一种结合极小碰集约简集成电路测试模式集的方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150161323A1 (en) * 2013-12-06 2015-06-11 Robert Bosch Gmbh Method for checking a hardware-configurable logic circuit for faults
US20190303260A1 (en) * 2018-03-29 2019-10-03 Arm Ltd. Device, system and process for redundant processor error detection

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2022089505A1 *

Also Published As

Publication number Publication date
US20230258718A1 (en) 2023-08-17
US12174254B2 (en) 2024-12-24
CN114428694A (zh) 2022-05-03
EP4227809A1 (fr) 2023-08-16
WO2022089505A1 (fr) 2022-05-05

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Owner name: SHENZHEN YINWANG INTELLIGENTTECHNOLOGIES CO., LTD.