Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
  • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
  • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
  • G11C13/0021—Auxiliary circuits
  • G11C13/003—Cell access
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
  • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
  • G11C13/0021—Auxiliary circuits
  • G11C13/0069—Writing or programming circuits or methods
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/011—Manufacture or treatment of multistable switching devices
  • H10N70/061—Shaping switching materials
  • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/20—Multistable switching devices, e.g. memristors
  • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/20—Multistable switching devices, e.g. memristors
  • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/20—Multistable switching devices, e.g. memristors
  • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
  • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/801—Constructional details of multistable switching devices
  • H10N70/881—Switching materials
  • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N70/801—Constructional details of multistable switching devices
  • H10N70/881—Switching materials
  • H10N70/883—Oxides or nitrides
  • H10N70/8833—Binary metal oxides, e.g. TaOx
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N89/00—Integrated devices, or assemblies of multiple devices, comprising at least one bulk negative resistance effect element covered by group H10N80/00
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
  • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
  • G11C13/0021—Auxiliary circuits
  • G11C13/0069—Writing or programming circuits or methods
  • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
  • G11C2213/70—Resistive array aspects
  • G11C2213/72—Array wherein the access device being a diode
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
  • G11C2213/70—Resistive array aspects
  • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Definitions

• TITLE ELEMENTARY CELL CONTAINING A RESISTIVE MEMORY AND A DEVICE INTENDED TO FORM A SELECTOR, CELL MATRIX, ASSOCIATED MANUFACTURING AND INITIALIZATION PROCEDURES
• the technical field of the invention is that of elementary cells comprising a resistive memory in series with a selector device.
• the present invention relates to an elementary cell comprising a resistive memory in series with a device intended to form a selector and a matrix comprising a plurality of elementary cells.
• the present invention also relates to a matrix comprising a plurality of elementary cells, a manufacturing method making it possible to obtain the matrix and a method for initializing the elementary cell or the matrix.
• rewritable non-volatile resistive memories are commonly used. These are based on active materials such as ionic conduction (CBRAM or “Conductive Bridging RAM”), metal oxide (OxRAM or “Oxide Resistive RAM”), ferroelectric (FERAM or “Ferroelectric RAM” memories) materials. ), magnetic (MRAM or “Magnetic RAM” memories, magnetic spin transfer (STTRAM or “Spin Torque Transfer RAM”) or phase change (PCRAM or “Phase Change RAM” memories). These memories are resistive type memories, that is to say they can have at least two resistive states, corresponding to a highly resistive state (“Fl RS” state for “High Resistance State”) and to a high resistance state. weakly resistive (“LRS” for “Low Resistance State”), under the application of a voltage.
• CBRAM memories comprise an active zone based on an ionically conductive material forming a solid ionically conductive electrolyte arranged between an electrode forming an inert cathode and an electrode comprising a portion of ionizable metal, that is to say a portion of metal which can easily form metal ions, and forming an anode.
• the operation of CBRAM memories is based on the formation, within the solid electrolyte, of one or more metallic filaments (also called “dendrites”) between its two electrodes when these electrodes are brought to appropriate potentials.
• the formation of the filament makes it possible to obtain a given electrical conduction between the two electrodes.
• By modifying the potentials applied to the electrodes it is possible to modify the distribution of the filament, and thus to modify the electrical conduction between the two electrodes.
• PCRAM memories comprise an active zone based on a chalcogenide material.
• the operation of PCRAM memories is based on the phase transition of the chalcogenide material, induced by heating of this material under the effect of specific electrical pulses applied between the two electrodes. This transition takes place between a crystalline, ordered, low resistance and thermodynamically stable phase and an amorphous, disordered, high resistance and thermodynamically unstable phase.
• OxRAM memories have an MlM (Metal-lsolant-Metal) structure comprising an active material of variable electrical resistance, in general a transition metal oxide (eg HfC> 2, Ta20s, PO2 ...), arranged between two metal electrodes.
• a transition metal oxide eg HfC> 2, Ta20s, PO2 .
• Resistive memories are particularly advantageous in being able to integrate with high densities, via integration of the "cross-bar” type (also referred to by the terminology “cross-point”).
• FIG 1 Such an architecture 200 is illustrated in Figure 1 and comprises a plurality of access lines 201, 202, 203, 204 and a plurality of memory cells (here four cells C11, C21, C22, C12 ) rewritable nonvolatiles based on active materials (eg CBRAM cells).
• the access lines are formed by upper parallel bit lines 201, 202 and lower word lines 203, 204 perpendicular to the bit lines, the elementary cells C11, C21, C22, C12 being sandwiched at the intersection between bit lines 201, 202 and the word lines 203, 204.
• the architecture 200 thus forms a network where each memory cell is individually addressable, by selecting the right bit line and the right word line.
• a selector device To avoid parasitic leakage currents passing through adjacent cells during the reading phase of the state of a cell carried out by polarization of the desired row and column, it is known to add in series with each of the cells, a selector device. In this case, the selector devices block the passage of the parasitic current, thus allowing only the current induced by the polarization of the bit line and the word line (application of a potential difference Vbias between these two lines).
• selector devices such as FAST (for "Field Assisted Superlinear Threshold”), MIEC (for “Mixed-lonic-Electronic Conduction”) and OTS (for "Ovonic Threshold Switching” ).
• FAST for "Field Assisted Superlinear Threshold”
• MIEC for "Mixed-lonic-Electronic Conduction”
• OTS for "Ovonic Threshold Switching”
• a selector device consists of two electrodes and an active material, the electrodes being arranged on either side of the active material and allowing a voltage to be applied to this active material.
• the active material can be a chalcogenide alloy, generally in an amorphous state.
• FIG 2 The basic principle of operation of a selector device is shown in Figure 2.
• the device is very resistive in the OFF state. As soon as a voltage greater than a threshold voltage Vth is applied to it, the current increases rapidly to reach the ON state of the device, a low resistive state. As soon as the current or voltage is reduced below a specific so-called holding or "holding” Ih value, the device becomes OFF again.
• the selector and possibly the resistive memory of an elementary cell must be initialized, the initialization consisting in applying an initialization voltage to the terminals of the element to be initialized.
• the initialization of the resistive memory and of the selector are carried out simultaneously during the same operation by applying an initialization voltage having a value generally of the order of the sum of the voltage necessary to initialize the resistive memory only and the voltage necessary to initialize the selector alone.
• Such an initialization voltage is generally greater than the threshold voltage of the selector and especially the programming voltage of the resistive memory, which is liable to damage it.
• a known means of protecting the resistive memory during the initialization of the cell is to use specific circuitry, but this complicates the operation of the elementary cell and generates additional costs.
• the invention offers a solution to the problems mentioned above, by making it possible to initialize an elementary cell without using dedicated circuitry.
• a first aspect of the invention relates to an elementary cell comprising a device and a non-volatile resistive memory connected in series, the device comprising: an upper selector electrode, a lower selector electrode, a layer made of a first material active, called active selective layer, said device being intended to form a volatile selector passing from a first resistive selector state to a second resistive selector state by application of a threshold voltage between the upper selector electrode and the electrode lower selector and returning to the first resistive selector state as soon as the current flowing through it or the voltage across the upper selector electrode and the lower selector electrode becomes respectively lower than a current or a holding voltage, the first resistive selector state being more resistive than the second resistive selector state, said memory comprising: an upper memory electrode, a lower memory electrode, a layer made of at least one second active material, called an active memory layer, said memory passing from a first resistive memory state to a second resistive memory state by applying a voltage or current between the upper memory electrode and the lower memory electrode, said selective
• the elementary cell can be initialized by applying an initialization voltage or forming voltage lower than the programming voltage of the elementary cell, without having to resort to an additional circuit.
• the electrical isolation of the cell between manufacture and initialization is provided by the resistive memory in the initial resistive state which is a very highly resistive state, and not as conventionally by the selector device in its highly resistive OFF state.
• the first resistive selector state corresponds to the OFF state of the selector device
• the second resistive selector state corresponds to the ON state of the selector device
• the first and second resistive memory state correspond to the HRS and LRS states resistive memory, defined previously.
• the elementary cell according to the first aspect of the invention may have one or more additional characteristics among the following, considered individually or in any technically possible combination: the device is intended to form an OTS type selector; the resistive memory is of the PCRAM, OxRAM or CbRAM type; the upper selector electrode coincides with the lower memory electrode.
• a second aspect of the invention relates to a matrix comprising a plurality of cells according to the first aspect of the invention, a plurality of upper access lines and a plurality of lower access lines, each cell being located at an intersection between an upper access line and a lower access line allowing its individual addressing
• the elementary cell according to the first aspect of the invention is compatible with a structure with high integration density.
• a third aspect of the invention relates to a method of manufacturing a matrix according to the second aspect of the invention, comprising the following steps: conformal deposition of a first layer of dielectric material; fabrication of a plurality of lower metal lines forming the lower electrodes for the selector of the elementary cells of the matrix, by damascene the first layer of dielectric material; conformal deposition, on the first layer of dielectric material, of a selective active layer in a crystalline state or in an amorphous state, an upper selector electrode layer, a lower memory electrode layer, d an active memory layer followed by an upper memory electrode layer; etching of at least a first trench with stopping on the first layer of dielectric material; filling with a second layer of dielectric material so as to fill the first trench; planarization with stop on the parts of the upper memory electrode layer which have not been etched; etching of at least a second trench perpendicular to the first trench with stop on the first layer of dielectric material; filling with a third layer of dielectric material so as to fill
• the selective active layer is deposited in a crystalline state by epitaxy which allows better control of the thickness of the selective active layer and to overcome the problems of homogeneity of a deposited amorphous material then crystallized.
• the selective active layer is deposited in an amorphous state by a conventional deposition method which facilitates the implementation of the process and is followed by annealing to crystallize the selective active layer.
• the annealing is carried out during the filling step with a second layer of dielectric material or during the manufacturing step of the upper metal line.
• the method according to the third aspect of the invention comprises a step of compliant deposition of a carbon layer before and after the deposition of the selective active layer .
• a fourth aspect of the invention relates to a method for initializing a cell according to the first aspect of the invention or of each cell of a matrix according to the second aspect of the invention comprising an application step an initialization current and a single voltage pulse having an intensity equal to a predetermined, predetermined initialization voltage and fall time between the upper memory electrode and the lower selector electrode.
• the initialization voltage is chosen to initialize the memory
• the current applied during the initialization or initialization current allows the melting of the crystalline selective active layer
• the fall time of the pulse is chosen for allow the quenching of the selective active layer, which allows the amorphization of the selector device to place the selector device in its highly resistive OFF state.
• the selector device can then perform its function of electrical insulation of the cell.
• FIG. 1 represents an addressing architecture of a plurality of memory cells according to the state of the art
• Figure 2 shows a graph explaining the operating principle of a selector device
• Figure 3 shows a schematic representation of an elementary cell according to the first aspect of the invention
• Figure 4 shows a schematic representation of the first step of the manufacturing process according to the third aspect of the invention.
• Figure 5 shows a schematic representation of the second step of the manufacturing process according to the third aspect of the invention.
• Figure 6 shows a schematic representation of the third step of the manufacturing process according to the third aspect of the invention
• Figure 7 shows a schematic representation of the fourth step of the manufacturing process according to the third aspect of the invention
• Figure 8 shows a schematic representation of the fifth step of the manufacturing process according to the third aspect of the invention.
• Figure 9 shows a schematic representation of the sixth step of the manufacturing process according to the third aspect of the invention.
• Figure 10 shows a schematic representation of the seventh step of the manufacturing process according to a third aspect of the invention.
• Figure 11 shows a schematic representation of the eighth step of the manufacturing process according to the third aspect of the invention.
• Figure 12 shows a schematic representation of the ninth step of the manufacturing process according to the third aspect of the invention to obtain a die according to the second aspect of the invention
• Figure 13 shows a block diagram showing the sequence of steps of the manufacturing process according to the third aspect of the invention.
• Fig. 14 shows a block diagram showing the step of the initialization process according to the fourth aspect of the invention.
• Figure 15 shows a curve illustrating the resistance of the selective active layer, initially crystalline and conductive, of a cell as a function of the current density applied to it, each point being measured after the application of a rectangular pulse having a duration of 1 microsecond.
• Figure 16 shows the current passing through the selective active layer of an elementary cell as a function of the voltage applied to it, before and after initialization.
• a first aspect of the invention illustrated in Figure 3 relates to an elementary cell 100 comprising a selector stack allowing the addressing of a resistive memory 102 non-volatile when it is integrated within a cross-bar type architecture.
• the elementary cell 100 comprises:
• a layer of conductive material forming an upper selector electrode and a lower memory electrode
• a layer of conductive material, forming an upper memory electrode 1015 is a layer of conductive material.
• the layer of conductive material of the upper selector electrode and the layer of conductive material of the lower memory electrode are merged into one and the same layer 1013 but it is also possible to have two separate layers to form these elements.
• the first active material is intended to form a selector device 101 and the second active material is able to form a resistive memory 102, the selector device 101 and the resistive memory 102 each requiring an upper electrode and a lower electrode to ensure their operation.
• an upper electrode of a device as the electrode located above this device and the lower electrode of a device such as the electrode located below this device, the electrodes being located on both sides. other part of the device.
• the adjectives “upper” and “lower” here relate to the orientation of the assembly including the upper electrode, the device and the lower electrode so that by turning this assembly over, the previously qualified electrode of upper becomes the lower electrode and the previously qualified lower electrode becomes the upper electrode.
• the material or materials of the active memory layer 1014 are chosen according to the type of memory desired, for example, a memory of the PCRAM, OxRAM or even CBRAM type: this choice then conditions the choice of the conductive materials of the electrodes 1013, 1015 of the memory 102.
• a CBRAM to function, it needs two electrodes arranged on either side of its ionically conductive active material, including one electrode comprising a portion of ionizable metal, c that is, a portion of metal which can easily form metal ions.
• the electrodes are for example made of Ag or Cu.
• the material of the active memory layer 1014 is for example In-Ge-Sb-Te, Ga-Sb, Ge-Sb, Ga-Sb-Te, Ti-Sb-Te, Ge- Sb-Se-Te, Si-Sb-Te, Ge-Sb-Te, Sb-Te or even Ge-Te.
• the thickness of the active memory layer 1014 is for example between 50 and 100 nm.
• the material of the active memory layer 1014 is for example Ge-S, Ge-Se, Cu-S, Ag-S, Ta-O, Si-O, W-O.
• the active memory layer 1014 may for example comprise a first sublayer of Al2O3 and a second sublayer of Cu-Te-Ge.
• the first sublayer has for example a thickness of 3.5 nm and the second sublayer has for example a thickness of 20 nm.
• the material of the active memory layer 1014 is for example Hf-O, Ta-O, Ti-O, Al-O.
• the active memory layer 1014 may for example comprise a first sublayer of HfC> 2 and a second sublayer of Ti.
• the first sublayer has for example a thickness of 5 to 10 nm and the second sublayer has for example a thickness of 5 to 10 nm.
• the selective active layer 1012 is in a conductive crystalline state and the resistive memory 102 is in an initial resistive state, more resistive than its strongly resistive state H RS.
• the material of the selective active layer 1012 is for example chosen so that the selector device to be formed is of the OTS type.
• the selective active layer 1012 is made of Ge-Se, As-Te-AI, Ge-Se-Te, Ge-Se-Sb, As-Ge-Te, As-Ge-Te-Si, Si-Te , C-Te, Al-Te, B-Te, Ge-Te, or alternatively in As-Ge-Se-Te
• the thickness of the selective layer 1012 is for example from 15 to 50 nm.
• the properties of the selector such as its threshold voltage or its sustaining current, can be adjusted by the thickness and the composition of the active selective layer 1012.
• the selective active layer 1012 can be sandwiched between two carbon layers.
• the carbon layers have for example a thickness of 3 to 15 nm.
• the material used for the electrodes 1011, 1013, 1015 is for example TiN, TaN, W, Cu, TiWN, TiSiN or even WN.
• the electrodes 1011, 1013, 1015 can all be made of the same material or else be made of different materials.
• a second aspect of the invention relates to a matrix 1000 illustrated in Figure 12 comprising a plurality of elementary cells 100.
• Figure 13 is a block diagram illustrating the sequence of steps 301 to 309 of a manufacturing process 300 according to a third aspect of the invention of the die 1000.
• Figure 4 illustrates the first step 301 of the process 300, which consists in performing a conformal deposition of a first layer of dielectric material 1010.
• a conformal deposition means that the material is deposited uniformly on the whole of a surface.
• the plane along which the first layer of dielectric material 1010 extends contains the X direction and the Y direction.
• the orthogonal coordinate system (X; Y; Z) defines the sides of the matrix 1000 if it is rectangular in shape.
• the dimension of the layers in the Z direction is called thickness.
• the dielectric material of the first layer of dielectric material 1010 is for example SiN, S1O2, SiC, SiON, SiCN or even SiHN.
• the deposition of this step 301 like those of the following deposition steps can be a physical vapor deposition or PVD (for “Physical Vapor Deposition”), a chemical vapor deposition or CVD (for “Chemical Vapor Deposition”), or atomic layer deposition or ALD (for “Atomic Layer Deposition”).
• FIG. 5 illustrates the second step 302 of the method 300 consisting in producing a damascene of the first layer of dielectric material 1010.
• the term "damascene” is understood to mean the method consisting in filling a trench with conductive material, beforehand formed in a dielectric material, followed by mechanical-chemical polishing. Damascene is for example made with Cu copper.
• the first layer of dielectric material 1010 comprises exposed metallic lower lines 1011, allowing metallic contacts to be established with an upper layer.
• the metallic lower lines constitute the lower selector electrodes 1011 of elementary cells 100 of matrix 1000.
• FIG 6 illustrates the third step 303 of the method 300 consisting in performing a conformal deposition on the first layer of dielectric material 1010 comprising lower metal lines 1011.
• This third step 303 comprises the conformal deposition of a selective active layer 1012, then a conformal deposition of a layer of conductive material 1013 forming both the upper selector electrode and the lower memory electrode, then a conformal deposition of an active memory layer 1014, then a deposition conformal of a layer of conductive material of upper memory electrode 1015.
• the third step 303 of the method 300 comprises the conformal deposition of a selective active layer 1012, then a conformal deposition of a first layer of conductive material forming the upper selector electrode, then a second layer of conductive material forming the lower memory electrode, followed by conformal deposition of an active memory layer 1014, then conformal deposition of a top memory electrode conductive material layer 1015.
• the third step 303 of the process 300 may additionally comprise a conformal deposition of a first layer of carbon on the first layer of dielectric material 1010 comprising lower metallic lines 1011 and of a second layer of carbon on the selective active layer 1012 such that the selective active layer 1012 is sandwiched between the first and the second carbon layer.
• the selective active layer 1012 is deposited directly in the crystalline state by epitaxy.
• epitaxy is understood to mean the method of growing a crystal or a poly-crystal.
• the selective active layer 1012 is deposited in an amorphous state by conventional deposition techniques, such as PVD, CVD or ALD deposition.
• the material of the selective active layer 1012 is then chosen to have a crystallization temperature compatible with the integration temperatures.
• an annealing will be carried out during the manufacture of the cell, so as to make this selective active layer 1012 crystalline, on leaving the manufacturing process.
• FIG. 7 illustrates the fourth step 304 of the method 300 consisting in etching at least a first trench 1016 with stopping on the first layer of dielectric material 1010.
• the etching is for example carried out by photoengraving or by lithography.
• the first trench 1016 extends along its length in the Y direction.
• the first trench 1016 is engraved so that the non-engraved parts are substantially of the same height after engraving.
• the first trenches 1016 are all parallel to each other and the etching depth is the same for all the first trenches 1016.
• FIG 8 illustrates the fifth step 305 of the method 300 consisting of encapsulating the stack of Figure 7. More specifically, this fifth step 305 consists of filling the first trench 1016 previously etched and covering the parts of the layer of conductive material of the upper memory electrode 1015 not having been etched in the previous etching step 304, with a second layer of dielectric material 1017.
• the filling is for example carried out by assisted chemical vapor deposition by plasma or PECVD (for “Plasma- Enhanced Chimical Vapor Déposition”) at a temperature of 350 ° C.
• Figure 9 illustrates the sixth step 306 of planarization of the process 300 consisting in removing material with stopping on the parts of the layer of conductive material of upper memory electrode 1015 that have not been etched during the etching step 304 so as to obtain a planar layer, in a plane containing the X and Y directions. Planarization is for example carried out by planarizing polishing.
• FIG. 10 illustrates the seventh step 307 of the method 300 consisting in etching at least a second trench 1018 in a direction, here along X, perpendicular to Y, with stopping on the first layer of dielectric material 1010.
• the second trenches 1018 are mutually parallel and the etching depth is substantially the same for all of the second trenches 1018.
• the second trench 1018 is etched so that the non-etched parts are substantially of the same height after The second trench 1018 extends, along its length, perpendicular to the first trench 1016, that is to say along the X axis.
• FIG 11 illustrates the eighth step 308 of the method 300 consisting in encapsulating the stack illustrated by Figure 10.
• This eighth step 308 consists in filling the second trench 1018 previously etched and covering the parts of the upper memory electrode conductive material layer 1015 that has not been etched in the etching steps 304, 308, with a third dielectric material layer 1019.
• Figure 12 illustrates the ninth step 309 of the method 300 consisting in producing a damascene of the third layer of dielectric material 1019 to form upper metal lines 1020.
• the process 300 comprises annealing making it possible to crystallize the selective active layer 1012 in order to make it crystalline.
• Annealing is for example carried out: during the fifth filling step 305; during the ninth damascene step 309, with an annealing temperature for example equal to 400 ° C .; during a specific annealing step.
• the matrix 1000 comprises a plurality of elementary cells 100 each having a device 101 intended to form a selector but not playing the role of selector, and an uninitialized memory 102.
• Figure 14 is a block diagram of an initialization method 400 according to a fourth aspect of the invention.
• the method 400 makes it possible to initialize an elementary cell 100 or each elementary cell 100 of a matrix 1000.
• Step 401 of the method 400 consists in applying an initialization current and a voltage pulse having an intensity equal to a given initialization voltage and a given fall time, to each elementary cell 100 to initialize its memory 102 and amorphizing the selective active layer 1012 of its device 101.
• the initialization current must be chosen to allow the melting of the crystalline selective active layer 1012
• the fall time of the pulse must be chosen to allow quenching of the selective active layer 1012 and to freeze it in its amorphous phase
• the initialization voltage must be chosen to allow the initialization of the memory 102.
• the term "fall time of a pulse” is understood to mean the time necessary for the pulse to go from 90% of its maximum value to 10% of its maximum value.
• the initialization pulse is for example a rectangular pulse having a duration of 1 microsecond with a fall time of 10 nanoseconds. and an intensity at least equal to the initialization voltage of the memory 102.
• the bias of the pulse allows the initialization of the memory 102.
• the pulse current is for example chosen so that the current density applied to the active selective layer 1012 is of the order of 20 ⁇ 10 6 A / cm 2 .
• FIG. 15 In Figure 15 is shown the resistance R of the selective active layer 1012 made of an alloy As2Te3 + Al + N, depending on the current density DI which is applied to it. Each point corresponds to the application of a rectangular pulse having a duration of 1 microsecond.
• the resistance of the selective active layer 1012 that is to say its rate of amorphization increases until it reaches a level corresponding to a resistance of 10 7 W around 20 ⁇ 10 6 A. / cm 2 .
• a rectangular pulse having a duration of 1 microsecond and a current density of 20 ⁇ 10 6 A / cm 2 to the active selective layer 1012, the latter is completely transformed.
• step 401 of method 400 in each cell 100, the selective active layer 1012 is in an amorphous state and therefore the selector device 101 is in its highly resistive OFF state, the memory 102 is initialized. and its active memory layer 1014 is in its low resistive state LRS.
• FIG. 16 illustrates the intensity I passing through the active selective layer 1012 of an elementary cell 100 as a function of the voltage T which is applied to it before and after the amorphization of the active selective layer 1012.
• the selective active layer 1012 behaves like a conductive metal and after amorphization, the active selective layer 1012 behaves like a selector device, as shown in Figure 2.
• the device 101 operates as a selector and the cell 100 or the matrix 1000 is then operational.

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• 2019
  • 2019-12-16 FR FR1914466A patent/FR3104813A1/fr active Pending
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  • 2020-12-11 EP EP20820959.3A patent/EP4078678A1/de active Pending
  • 2020-12-11 US US17/785,699 patent/US20230047263A1/en active Pending
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