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EP3840202A1 - Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten - Google Patents

Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten Download PDF

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Publication number
EP3840202A1
EP3840202A1 EP19218723.5A EP19218723A EP3840202A1 EP 3840202 A1 EP3840202 A1 EP 3840202A1 EP 19218723 A EP19218723 A EP 19218723A EP 3840202 A1 EP3840202 A1 EP 3840202A1
Authority
EP
European Patent Office
Prior art keywords
circuit
discharge
sub
resistor
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19218723.5A
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English (en)
French (fr)
Inventor
Max Richter
Eike MEINTS
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Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Priority to EP19218723.5A priority Critical patent/EP3840202A1/de
Priority to PCT/JP2020/040185 priority patent/WO2021124685A1/en
Priority to EP20803979.2A priority patent/EP4078792B1/de
Priority to CN202080069569.7A priority patent/CN114467247A/zh
Priority to US17/640,166 priority patent/US11716042B2/en
Publication of EP3840202A1 publication Critical patent/EP3840202A1/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock

Definitions

  • the present subject matter relates to generally to power distribution-units and, more particularly to discharging mechanism therein.
  • a state of the art electric motor drive-device for driving an electric motor via an inverter has a smoothing-capacitor (i.e. a DC Link capacitor) provided in parallel with a DC power supply at the inverter input side.
  • a smoothing-capacitor i.e. a DC Link capacitor
  • an electric motor driven vehicle such as a hybrid vehicle includes a drive motor, a high-voltage battery for supplying power to the drive motor, and an inverter.
  • the smoothing capacitor or the DC link capacitor is provided between the input terminals of the inverter to smooth voltage-fluctuations and stabilize the operation of the inverter.
  • the smoothing capacitor serves to reduce the impedance of a main-circuit, suppresses surge voltage, serves to absorb regenerative-power in the case of abnormality, and prevents overvoltage in the main circuit.
  • An example scenario of abnormality is a load dump. In this scenario, while the electric motor is performing regenerative operation, input wiring of the inverter is disconnected due to vibration or the like. In other example, a breaker provided on the input side fails during abnormal-scenario, and thus a connection between a smoothing capacitor on the inverter input side and a DC power supply is opened
  • Another example scenario is when to rescue a driver in an event of car accident or vehicle maintenance, it is necessary to quickly discharge smoothing-capacitor or the DC link capacitor. Such scenarios also remain prone to voltage-surges and require overvoltage protection.
  • an overvoltage protection device which includes: a bypass-resistance circuit interposed between terminals at an input part of an inverter; a relay interposed in series to the bypass resistance circuit and controlled, to be opened/closed, and a control-means for controlling the relay to make the bypass resistance-circuit active when input-voltage of the inverter is equal to or greater than reference-voltage.
  • Figure 1 illustrates a state of the art discharge-circuit with parallel-branches of semiconductors in series with resistor.
  • the discharge-circuit is configured by connecting, in parallel, about three series circuits of discharge-resistors and IGBTs.
  • the concept of adjusting discharge- duration within the circuit to a certain target-duration also corresponds to the conventional mechanisms.
  • the conventional circuits exhibit a complicated-configuration and a large-circuit area.
  • all branches i.e. the three series circuits or three discharge branches
  • controlling the multiple discharge-circuits for setting the discharge duration to a target value is always a challenging task and requires frequent quality-checks and maintenance owing to complex arrnangement.
  • the present subject matter refers a discharge circuit for a smoothing capacitor within a power-distribution-unit.
  • the discharge circuit comprises a first sub-circuit connected in parallel to a DC-Link capacitor.
  • the first sub-circuit in turn comprises a series connection of a first switching element (SE) and a first discharge resistor, wherein the DC-link capacitor is connected in parallel to a power supply.
  • a second sub-circuit is connected in parallel to the DC-Link capacitor and comprises a series connection of a second switching element (SE) and a second discharge resistor.
  • a control device is configured to control the plurality of SEs within the sub-circuits by scheduling switching of the plurality of SEs. Such scheduling comprises switching ON of the second SE after a switching ON of the first SE for enabling a discharging of the DC link capacitor within a predetermined duration.
  • the first discharge resistor of the first sub-circuit exhibits a resistance greater than second discharge-resistor of the second sub-circuit, and the first SE is a smaller-scale device than the second SE.
  • the present subject matter illustrates an electric motor drive comprising a DC-link capacitor connected in parallel to a DC power supply.
  • An inverter converts DC power from the DC capacitor to multi-phase AC power, to drive an electric motor.
  • An overvoltage-protection unit is provided within the electric motor drive, wherein such overvoltage protection unit may be defined by the discharge circuit in accordance with the present subject matter.
  • FIG. 2 illustrates an electronic system or a discharge circuit for a smoothing capacitor within a power-distribution unit.
  • the discharge-circuit comprises a first sub-circuit connected in parallel to a DC-Link capacitor (i.e. DC-Link).
  • the first sub-circuit in turn comprises a series-connection of a first switching element SE (Q_FDa) and a first discharge resistor (R_FDa).
  • the DC-link capacitor is connected in parallel to the power-supply which may be a high voltage battery.
  • the discharge circuit further comprises a second sub-circuit connected in parallel to the DC-Link capacitor and comprises a series-connection of a second switching element SE (Q_FDb) and a second discharge resistor (R_FDb).
  • the first SE (Q_FDa) conducts an electrical power greater than the electrical power conducted by the second SE (Q_FDb) during the discharging of the DC-link capacitor within the predetermined duration.
  • the first discharge resistor (R_FDa) of the first sub-circuit exhibits a resistance greater than second discharge resistor (R_FDb) of the second sub-circuit.
  • the first SE (Q_FDa) of the first sub-circuit is a smaller scale device than the second SE (Q_FDb) of the second sub-circuit.
  • at-least one of the first SE (Q_FDa) and second SE (Q_FDb) is an IGBT.
  • the discharge circuit further comprises a control-device configured to generate a "Gate-signal" to control the plurality of SEs within the sub-circuits by scheduling switching of the plurality of SEs. Such scheduling comprises switching ON the second SE (Q_FDb) after switching ON the first SE (Q_FDa) for enabling a discharging of the DC link capacitor within a predetermined duration.
  • the control-device comprises a gate-driver configured to output a control signal (i.e. "Gate-signal") for all branches within the discharge circuit.
  • the circuit connected to the gate driver comprises a first branch and a second branch connected to the first SE and the second SE respectively.
  • a first resistor (Ra1) is disposed on the first branch, and a second resistor (Rb1) is disposed on the second branch, connected in series with the first resistor (Ra1).
  • a gate of the first SE (Q_FDa) is connected to a connection point within the first branch between the first resistor (Ra1) and the gate driver, and a gate of the second SE (Q_FDb) is connected to a connection point within the second branch between the first resistor (Ra1) and the second resistor (Rb1).
  • Each of the branches comprises two semiconductor switching elements (PNP and NPN) defining a logic circuit to switch ON/OFF the first SE (Q_FDa) and second SE(Q FDb).
  • the two semiconductor switching elements are defined by NPN and PNP transistors to switch ON/OFF the first SE (Q_FDa) by connecting and disconnecting a high-voltage power supply to the first SE (Q FDa).
  • the transistors Qa1 and Qa2 are used to stabilize the gate voltage of the IGBT Q_FDa.
  • the transistors Qb1 and Qb2 are used to stabilize the gate voltage of the IGBT Q_FDb.
  • the discharge circuit further comprises a third sub-circuit connected in parallel to the DC-Link capacitor and comprises a series connection of a third switching element SE (Q_FDc) and a third discharge-resistor (R_FDc).
  • a circuit connected to the gate driver for serving the present third sub-circuit comprises a third-branch connected to the third SE (Q_FDc) and accordingly a third resistor (Rc1) disposed on the third branch.
  • the third resistor (Rc1) disposed on the third branch is connected in series with the second resistor (Rb1) of the second branch.
  • a gate of the third SE (Q_FDc) is connected to a connection point within the third branch between the second resistor (Rb1) and the third resistor (Rc1).
  • the third SE (Q_FDc) conducts an electrical-power lesser than the electrical power conducted by the second SE (Q_FDb) during the discharging of the DC-link capacitor within the predetermined duration.
  • the third discharge resistor (R_FDc) exhibits a resistance lesser than the second discharge resistor (R_FDb), and the third SE (Q_FDc) corresponds to a large scale device analogous to the second SE(Q FDb). Further, the transistors Qc1 and Qc2 are used to stabilize the gate voltage of the IGBT Q_FDc.
  • a logical-operation of the logic-elements present (NPN, PNP) within the three branches and all the IGBTs may be summarized through the following truth table represented by Table 1: Table 1 Qa1 (NPN) Qa2 (PNP) Q_FDa or First SE 1 1 1 0 0 0 Qb1 (NPN) Qb2 (PNP) Q_FDb or Second SE 1 1 1 0 0 0 Qa1 (NPN) Qa2 (PNP) Q_FDc or Third SE 1 1 1 1 0 0 0 0
  • the discharge circuit of Fig. 2 may be incorporated for example in an electric motor drive.
  • the electric motor drive comprises a DC-link capacitor connected in parallel to a DC power supply.
  • An inverter converts DC power from the DC capacitor to multi-phase AC power, to drive an electric motor.
  • An overvoltage protection unit is defined by the present discharge-circuit of Fig. 2 and is connected in parallel to the DC-link capacitor.
  • FIG. 3 illustrates a gate-driver arrangement of Fig. 2 , in accordance with an embodiment of the present subject matter. More specifically, while Fig 3a represents the delay circuit with respect to all the branches, Fig. 3b represents the timing of the triggering of the gates of all three IGBTs (Q_FDa, Q_FDb, Q_FDc).
  • the present discharge circuit sets the discharge duration to a target range as may be specified by a third party or defined by a user (i.e. human operator) of the power distribution unit. Accordingly, all IGBTs (Q_FDa, Q_FDb, Q_FDc) are triggered or fired at different-instants of time, since the duration until completing discharge is set to a certain range. Accordingly, as represented in Fig. 3a , a common driving-signal or a single gate signal may be rendered for three delay circuits (Delay circuit 1, 2, 3) for sequentially triggering the three IGBTs (Q_FDa, Q_FDb, Q_FDc) through the first, second and third branches, respectively.
  • Delay circuit 1, 2, 3 for sequentially triggering the three IGBTs (Q_FDa, Q_FDb, Q_FDc) through the first, second and third branches, respectively.
  • a corresponding number of delay circuits may be employed.
  • the present implementation merely represents a design example and may be construed to cover two, three or more branches associated with a plurality of delay circuits.
  • Fig. 3a illustrates a serial connection of the delay circuits-1, 2, 3 for the plurality of IGBTs with just one driving signal.
  • the delay circuit may be an RC delay circuit of state of the art.
  • the present example may be construed to cover other example delay circuits.
  • an adjustable impedance-element may be provided in the driver circuit for scheduling turning ON/OFF of the IGBTs at different points of time.
  • Fig. 3b illustrates the sequential triggering of gates of the IGBTs (Q_FDa, Q_FDb, Q_FDc) after respective time-delays 'a', 'b' and 'c' subsequent to the provision of the common gate-driver signal.
  • the gate signal rendered by the microcontroller or gate driver undergoes a delay by the "RC delay circuit 1".
  • the same triggers the transistor Qa1 and Qa2 (of the first branch) to be switched substantially simultaneously, thereby in turn switching ON the corresponding IGBT Q_FDa.
  • Neglecting a substantially small propagation delay of the transistor Qa1 and Qa2, all of the switches Qa1, Qa2 and Q_FDa may be switched after a "delay a" at substantially the same-time.
  • the delay or the timing of the gate trigger may be adjusted by the underlying RC circuit, i.e. Ra1, Ca1.
  • the switches Qb1, Qb2 and Q_FDb may be switched after a "delay b" at substantially the same-time.
  • the delay or the timing of the gate trigger may be adjusted by the underlying RC circuit, i.e. Rb1, Cb1.
  • the switches Qc1, Qc2 and Q_FDc may be switched after a "delay c" at substantially the same-time.
  • the delay or the timing of the gate trigger may be adjusted by the underlying RC circuit, i.e. Rc1, Cc1.
  • FIG. 4 illustrates a discharge pattern with respect to the discharge-circuit with plurality of branches, in accordance with an embodiment of the present subject matter.
  • Fig 4a correspond to Fig. 3b , such that V(gate1), V(gate2), and V(gate3) correspond to gate voltages of Q_FDa, Q_FDb, Q_FDc, respectively.
  • Fig. 4b corresponds to variation of the discharge voltage of the DC link capacitor during discharge of the DC link capacitor.
  • Fig. 4c illustrates the resulting current flow (due to the discharge of the DC link capacitor) through the discharge resistors R_FDa, R_FDb, R_FDc, represented as R1, R2 and R3, respectively. Accordingly, the discharge current flow through R FDa, R FDb, R_FDc may be represented as I(R1), I(R2) and I(R3), respectively. Owing to high peak currents I(R2) and I(R3), the second SE Q_FDb and third SE Q_FDc may be sized higher than the first SE Q FDc.
  • Fig 4d represents the propagation of electrical power across the three branches, each branch corresponding to a series combination of discharge resistor R_FD and a corresponding switching element IGBT 'Q_FD'. More specifically, an area with 'hatching' represents electrical power passed through the first branch comprising the Q_FDa and R_FDa. As may be observed, the first SE or Q_FDa conducts an electrical power greater than the electrical power conducted by the second and third branches represented by the second SE Q_FDb and third SE Q_FDc, respectively, during the discharging of the DC-link capacitor.
  • FIG. 5 illustrates an example testing of operation of the discharge circuit, in accordance with an embodiment of present subject matter. More specifically, the present figure illustrates experimental data based on experimental resistance values of R_FDa, R_FDb, R_FDc and a target discharge duration of 30 ms.
  • Such example values for R_FDa, R_FDb, R FDc may be represented as follows through following Table 2: Table 2 R_Fda R_FDb R_FDc Resistance [Ohm] 13 6 1
  • the waveform represented in Fig. 5 corresponds to Fig. 4b and illustrates an example variation of the discharge voltage (V_DC link) during the discharge of the DC- link capacitor within the example target duration of 30ms.
  • the time milestones ⁇ a , ⁇ b and ⁇ c within the x axis corresponds to the gate circuit delay a, delay b and delay c as depicted in Fig. 4 and accordingly represent the timing of triggering of Q FDa, Q FDb, Q FDc, respectively.
  • ⁇ a ⁇ 0 ms While ⁇ a ⁇ 0 ms, however ⁇ b > ⁇ c > 0 ms.
  • Tend represents the time milestone of the completion of discharge and accordingly represents the end of the 30ms discharge duration
  • the discharge current flow I DC Link during the entire discharge duration may be time-segmented into three time-segments based on the time milestones ⁇ a , ⁇ b , ⁇ c , and ⁇ end . Further, the values of various segments of I DC Link may be derived through standard RC Discharging Circuit equations.
  • the time-segmented discharge current flow I DC Link may be represented as follows through following Table 3: Table 3 Time segment Applicable RC time constant I dc ( t ) [ ⁇ a , ⁇ b ) R FDa ⁇ C U dc t R FDa e ⁇ t R FDa C [ ⁇ b , ⁇ c ) R FDa ⁇ R FDb ⁇ C U dc t R FDa ⁇ R FDb e ⁇ t R FDa ⁇ R FDb C [ ⁇ b ,T end ] R FDa ⁇ R FDb ⁇ R FDc ⁇ C U dc t R FDa ⁇ R FDb ⁇ R FDc e ⁇ t R FDa ⁇ R FDb ⁇ R F
  • RMS current and energy expended in terms of the discharge resistors may be represented as follows through following Table 4 : Table 4 R_FDa R_FDb R_FDc RMS Power [kW] 17 14 1.1 Energy [J] 690 450 19
  • FIG. 6 illustrates an example-size variation of the components across the discharge circuit, in accordance with embodiment of the present subject matter.
  • the first discharge resistor (R_FDa) of the first sub-circuit exhibits a resistance greater than second discharge resistor (R_FDb) of the second sub-circuit.
  • the third discharge resistor (R FDc) of the third sub-circuit exhibits a resistance lesser than second discharge resistor (R FDb) of the second sub-circuit. Accordingly, the third discharge resistor (R FDc) exhibits least resistance, while the first discharge resistor R_FDa exhibits the highest.
  • the first SE (Q_FDa) of the first sub-circuit is a smaller scale device than the second SE (Q_FDb) of the second sub-circuit.
  • the third SE (Q_FDc) corresponds to a large scale device than the first SE (Q_FDa) and may be analogous to the second SE. In other example, the third SE (Q_FDc) may be evenlarger scale device than the second SE (Q_FDb)
  • the following table 5 represents example size-values with respect to the discharge resistors and the IGBTs Table 5 R_FDa R_FDb R_FDc 30937,5mm 3 6885mm 3 469,3mm 3 Q_FDa or First SE Q_FDb or second SE Q_FDc or third SE 469,3mm 3 1071,7mm 3 1071,7mm 3
  • FIG. 7 illustrates method steps in accordance with an embodiment of the present subject matter. More specifically, the present Fig. 7 illustrates a method of operation in a discharge circuit for a smoothing capacitor or the DC link capacitor in a power-distribution unit
  • Step 702 represents generating a control signal by a microcontroller or a gate-driver circuit.
  • Step 704 represents scheduling switching operations by switching ON a second switching element (SE) after a switching ON of the first SE among a plurality of sequentially arranged SEs based on said control signal, wherein the plurality of SEs are sequentially arranged through providing a first sub-circuit connected in parallel to a DC-Link capacitor and a second sub-circuit connected in parallel to the DC-Link capacitor.
  • the DC-link capacitor is connected in parallel to a power supply.
  • the switching facilitates a sequential communication of the control signal from the microcontroller to a plurality of branches of a driver-circuit to enable said scheduling the switching of the plurality of SEs.
  • the switching comprises switching ON/OFF the first SE and second SE by connecting and disconnecting a high voltage power supply to the first SE and second SE, respectively.
  • the switching comprises receiving the control signal from the microcontroller via a first RC circuit and communicating the control signal with a first delay to a first driver-circuit branch for communication to the first SE. Further, the switching comprises receiving the control signal through a series connection of a second R-C circuit and the first R-C circuit and communicating the control signal with a second delay to a second-driver-circuit branch for communication to the second SE.
  • Step 706 represents controlling the plurality of switching elements (SEs) based on the control-signal through the scheduled switching of the plurality of SEs for enabling a discharging of a DC link capacitor within a predetermined target duration.
  • the controlling comprises enabling a higher electric power conduction through the first SE with respect to the second SE during the discharging of the DC link capacitor.
  • the discharge circuit and the electronic system in accordance with the present subject matter at least allows an ease of setting of discharge duration of the DC Link capacitor to a target value while resorting to a simple electronic circuit configuration.
  • a single gate signal is enabled to sequentially drive different switching element-discharge resistor based branches, thereby obviating the need of separate gate drivers otherwise needed by conventional mechanisms in case of multiple branches forming part of the discharge circuit.
  • the switching elements and discharge resistors are differently sized thereby further adding to the simplification in the present scenario.
  • the present subject matter allows maintaining substantially unequal sized discharge resistors and switching elements across the multiple branches.
  • the present discharge circuit is scalable to employ various types of delay circuits, driver circuits and logic circuits (other than referred in the preceding description) for sequencing the triggering of different switching element across different branches and thereby achieve the discharge within the target duration.
  • the phrase “A or B” should be understood to include the possibilities of "A” or “B” or “A and B.”

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
EP19218723.5A 2019-12-20 2019-12-20 Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten Withdrawn EP3840202A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP19218723.5A EP3840202A1 (de) 2019-12-20 2019-12-20 Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten
PCT/JP2020/040185 WO2021124685A1 (en) 2019-12-20 2020-10-27 Method, system and apparatus for discharging dc link capacitors in power-distribution-units
EP20803979.2A EP4078792B1 (de) 2019-12-20 2020-10-27 Verfahren, system und vorrichtung zum entladen von spannungszwischenkreiskondensatoren in stromverteilungseinheiten
CN202080069569.7A CN114467247A (zh) 2019-12-20 2020-10-27 使配电单元中的dc链路电容器放电的方法、系统和设备
US17/640,166 US11716042B2 (en) 2019-12-20 2020-10-27 Method, system and apparatus for discharging DC link capacitors in power-distribution-units

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19218723.5A EP3840202A1 (de) 2019-12-20 2019-12-20 Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten

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EP19218723.5A Withdrawn EP3840202A1 (de) 2019-12-20 2019-12-20 Verfahren, system und vorrichtung zum entladen von gleichstromzwischenkreiskondensatoren in stromverteilungseinheiten
EP20803979.2A Active EP4078792B1 (de) 2019-12-20 2020-10-27 Verfahren, system und vorrichtung zum entladen von spannungszwischenkreiskondensatoren in stromverteilungseinheiten

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DE102018221209A1 (de) * 2018-12-07 2020-06-10 Zf Friedrichshafen Ag Vorrichtung und Verfahren zur Entladung eines Zwischenkreiskondensators
KR20230072209A (ko) * 2021-11-17 2023-05-24 엘지디스플레이 주식회사 표시 장치
KR102740575B1 (ko) * 2022-12-02 2024-12-11 재단법인 한국섬유기계융합연구원 Dc 버스 전압 방전 회로

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EP4078792B1 (de) 2024-04-17
US11716042B2 (en) 2023-08-01

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