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EP3707972A1 - Method and device for the integration of semiconductor wafers - Google Patents

Method and device for the integration of semiconductor wafers

Info

Publication number
EP3707972A1
EP3707972A1 EP18792891.6A EP18792891A EP3707972A1 EP 3707972 A1 EP3707972 A1 EP 3707972A1 EP 18792891 A EP18792891 A EP 18792891A EP 3707972 A1 EP3707972 A1 EP 3707972A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
glass substrate
recesses
semiconductor wafer
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18792891.6A
Other languages
German (de)
French (fr)
Inventor
Roman Ostholt
Norbert AMBROSIUS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LPKF Laser and Electronics SE
Original Assignee
LPKF Laser and Electronics AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LPKF Laser and Electronics AG filed Critical LPKF Laser and Electronics AG
Publication of EP3707972A1 publication Critical patent/EP3707972A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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Definitions

  • the invention relates to a method for integrating semiconductor wafers in a small space, in particular 3D integration, in which the semiconductor wafers after positioning relative to a substrate and / or a redistribution layer (RDL) protected by introducing a potting compound and in be fixed in their relative position. Furthermore, the invention relates to a device for use in the method, a corresponding integrated semiconductor wafer device as a production intermediate and as an end product.
  • RDL redistribution layer
  • active circuits such as logic, memory, processor circuits, and the like are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device.
  • Such bonding processes employ sophisticated techniques and improvements are desired.
  • the assembly and connection technology (AVT) deals with the further processing of the semiconductor wafer packaging and integration into the circuitry environment.
  • a wafer level package (WLP) structure is used as a package structure for
  • an electrical rewiring structure which comprises one or more electrical redistribution layers (redistribution layers: RDL).
  • RDL redistribution layers
  • Each RDL can be designed as a structured metallization layer and serves as an electrical
  • An interconnect configured to package the electronic component embedded in the packaging with the external terminals of the semiconductor device package and / or one or more electrodes on the underside of the semiconductor device package
  • Semiconductor device package arranged to connect semiconductor wafers.
  • A1 shows a semiconductor package in which a semiconductor wafer is embedded in a potting compound.
  • a redistribution layer is provided with solder balls for surface mounting the semiconductor wafer package.
  • Through-holes through the semiconductor package are provided with solder material on a surface of the semiconductor package with which a second semiconductor package can be stacked on top of the first.
  • US 6 716 670 B1 shows a surface mount semiconductor wafer package. On a main surface, contacts are provided to which a second semiconductor wafer package can be attached.
  • DE 10 2006 033 175 A1 shows an electronic module comprising a logic part and a power part. Logic part and power unit are arranged on superposed substrates and potted together.
  • US 2015/0303174 A1 relates to the complex 3D integration and US 2017/0207204 A1 to the "integrated fan out packaging".
  • the introduction of the potting compound can lead to a relative displacement of the semiconductor wafer with each other and with respect to a predetermined desired position of the semiconductor wafer. In addition, it comes due to the solidification-related shrinkage of
  • the invention has for its object to provide a way to avoid the associated adverse effects.
  • a method is provided in which prior to the introduction of potting compound a substrate made of glass with a plurality of by wall surfaces or better expressed "partitions" separate recesses for receiving one or more semiconductor wafers positioned relative to the semiconductor wafers such or In this way, one or more semiconductor wafers are arranged in a respective recess and separated from other semiconductor wafers
  • Glass substrate a mask with the recesses adapted to the semiconductor wafer, which may be preferably already equipped with through-holes (through glass via: TGV) and allow a via.
  • TGV through glass via
  • the laser-induced deep etching is used, which has become known under the name LIDE (Laser Induced Deep Etching).
  • LIDE Laser Induced Deep Etching
  • TGV through glass via
  • Redistribution Layer is connected to this layer, wherein the intermediate walls between the recesses enclose the semiconductor wafer on all sides.
  • RDL Redistribution Layer
  • the semiconductor wafers are cast within the recesses of the glass substrate.
  • the semiconductor wafers can be fitted in the glass substrate, so that the substrate could possibly be omitted.
  • the object according to the invention is additionally achieved in that the glass substrate is provided with a plurality of recesses, which are also referred to as cavities, which enclose the semiconductor wafers with a small gap or even fitting, wherein the recesses are delimited by side wall surfaces, have a largely flat course, in particular so no reduced between the surfaces of the glass substrate clear width or no convex extending into the recess wall surface area.
  • a plurality of recesses which are also referred to as cavities, which enclose the semiconductor wafers with a small gap or even fitting, wherein the recesses are delimited by side wall surfaces, have a largely flat course, in particular so no reduced between the surfaces of the glass substrate clear width or no convex extending into the recess wall surface area.
  • the wall surface may have a V-shaped course, that is to say a continuously increasing clear width of the recess, the pitch preferably being constant without
  • a transparent, translucent or transmissive potting compound for example a polymer
  • Redistribution layer and thereon contact elements are applied.
  • Semiconductor wafer device in particular integrated semiconductor device arrangement, as a production intermediate, preferably produced by the method according to the invention, characterized by the following features:
  • a finished semiconductor product device that can be produced from this is an integrated semiconductor wafer device in which removal of the carrier substrate and the adhesive film leaves a glass substrate with recesses formed between intermediate walls, in each of which one or more semiconductor wafers, in particular semiconductor components embedded with a potting compound. Furthermore, the device has a rewiring layer in electrical contact with the one or more semiconductor wafers, in particular semiconductor components and contact elements, in particular solder balls, on the rewiring layer.
  • Fig. 1 is a vertical sectional view of a glass substrate with recesses and
  • FIG. 2 is a horizontal sectional view of a glass substrate with recesses and plated-through holes in a second embodiment
  • Fig. 3 is a vertical sectional view of a glass substrate with recesses and
  • FIG. 5 (a-d) vertical sectional views of various embodiments of a
  • Fig. 6 (a-c) are schematic vertical sectional views of various others
  • Fig. 7 - 9 are schematic, partial plan views of various others
  • Embodiments of a semiconductor integrated wafer device Embodiments of a semiconductor integrated wafer device.
  • a glass substrate 1 of thickness D is provided with a plurality of recesses 2 and a distance b.
  • Through holes 4 - so-called “through glass vias” (abbreviated to TGV) - are placed in the intermediate walls 3 of the glass substrate 1 surrounding the recesses 2, in which a metallization 5 is introduced in a conventional manner.
  • the glass substrate 1 consists at least essentially of an alkali-free glass , in particular an aluminoborosilicate glass or borosilicate glass.
  • FIG. 2 shows the plan view of a similar glass substrate 1, which in turn has rectangular recesses 2 in plan view.
  • the narrow sides 6, 7 flanking through-holes 4 are introduced.
  • Through holes 4 are located in two rows parallel below the recess 2 shown on the right in FIG.
  • the recesses 2 can - as shown in Figure 1 - be formed as a continuous openings, but also as blind holes.
  • Recesses 2 introduced with intermediate walls 3 between them.
  • the opposite side wall surfaces 8 of the recesses 2 are not arranged - as in the embodiment of FIG. 1 - perpendicular to the main plane of the glass substrate 1, but open in a V-shape with respect to FIG. 3, in which the
  • Side wall surfaces 8 occupy a flank angle a relative to the surface normal to the glass substrate 1, which may be up to 10 °, in particular up to 8 ° or 5 °.
  • the side surfaces 8 need not necessarily be flat, they can also be a
  • its material thickness D can be, for example, ⁇ 500 ⁇ m
  • the wall thickness b of the intermediate walls 3 is ⁇ 500 ⁇ m, preferred gradations are ⁇ 300 ⁇ m, ⁇ 200 ⁇ m, ⁇ 100 ⁇ m or ⁇ 50 ⁇ m and is preferably less than the material thickness D of the glass substrate 1. Accordingly, the ratio b / D of the maximum remaining wall thickness b between two recesses 2 in the glass substrate 1 to its material thickness D ⁇ 1: 1, preferably ⁇ 2: 3, ⁇ 1: 3 or ⁇ 1: 6 be.
  • the size of the recesses 2 in the glass substrate 1 is basically chosen so that semiconductor components 9 can be accommodated therein with the smallest possible distance to the side wall surfaces 8.
  • the positions of the recesses 2 are chosen so that they correspond to the desired later positioning of the semiconductor components 9 in an integrated semiconductor component arrangement - a so-called "chip package” or "fan out package”.
  • Fig. 4 a) to f) shows schematically how an inventive glass substrate 1 can be used in the manufacture of a chip package.
  • Fig. 4 a) shows as
  • step d) a potting compound 12 is poured into the recesses 2 in step c) in order to fix the semiconductor components 9 in their position within the glass substrate 1.
  • step d) the adhesive film 1 1 is detached with the carrier substrate 10. This is a compact unit of the glass substrate 1, introduced therein through holes 4 with metallization 5 and embedded in the potting compound 12 semiconductor devices 9 before.
  • a redistribution layer - a so-called “RDL” - 13 is deposited on the side of the unit on which the electronic components 9 are exposed - in Figure 4 e) this is the top after the unit has been turned are, as can be seen in Figure 4 f), applied at corresponding connection points (not shown) of the redistribution layer 13 solder balls 14 for contacting the semiconductor devices.
  • FIG. 5 shows various embodiments of a semiconductor integrated-device arrangement, each of which has been processed up to step c) in FIG. 4.
  • adhesive film 1 1 and a glass substrate 1 with one or more semiconductor devices 9 is implemented fixed in corresponding recesses 2 by means of the potting compound 12.
  • Fig. 5 a) shows a glass substrate 1 with a single semiconductor device 9, Fig. 5 b) with several components 9.
  • Fig. 5 c) are in
  • Edge region to the recesses 2 through holes 4 have been generated, which are partially filled with a metallization 5.
  • FIG. 5 d shows the use of a transparent encapsulant 12, which enables optical data communication 15 between the semiconductor components 9 through the transmissive glass substrate 1.
  • the recess 2 in the glass substrate 1 is cut so closely that the semiconductor component 9 is virtually prefixed in direct contact with the intermediate wall 3 on the carrier substrate 10 in its position in this plane.
  • FIG. 6b takes up the configuration shown in FIG. 3, in which the side wall surfaces 8 of the glass substrate are inclined at a flank angle.
  • the open bottom surface of the recess 2 is in turn dimensioned so that the semiconductor device 9 rests with its foot on the lower edge of the inclined side wall surface 8 and thus also takes place a position pre-fixing of the device.
  • the same effect is achieved in the embodiment shown in Figure 6c, characterized in that two opposite side wall surfaces 8 are provided approximately at half the height respectively with V-shaped projections 16 on which the semiconductor devices 9 is applied.
  • recesses 17 for the corners of the recesses can be made in the corner regions of the respective recess 2 Components 9 may be created in the glass substrate 1.
  • outstanding stops 18 are additionally arranged on the glass substrate 1 by the side wall surface 8, whereby so-called “overdeterminations” in the position fixing of the semiconductor component 9 in the recess 2 are avoided.
  • the prefixing of the semiconductor component 9 is finally additionally optimized by two spring elements 19 in the side wall surfaces 8 opposite the stops 18, the glass substrate 1 being further optimized. It should be noted, however, that the construction elements recess 17, stop 18 and spring element 19 can also be used separately, individually or in different combinations in different recesses 2 of an integrated semiconductor wafer device.

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Abstract

The invention relates to a method for the integration of semiconductor components (9) in a confined space, in particular for 3D integration, in which, after positioning relative to a supporting substrate (10) and/or redistribution layer RDL (13) the semiconductor components (9) are protected and fixed in their relative position by introduction of a potting compound (12), is characterised in that before the introduction of the potting compound (12) a glass substrate (1) having a plurality of recesses (2) separated by partitions (3) to receive a semiconductor component (9) is positioned in such a way that the semiconductor component (9) is surrounded by the side wall surfaces (8) facing the semiconductor component of the respective partitions (3) of the glass substrate (1).

Description

Verfahren und Vorrichtung zur Integration von Halbleiter-Wafern  Method and device for integrating semiconductor wafers

Die Erfindung betrifft ein Verfahren zur Integration von Halbleiter-Wafern auf engem Raum, insbesondere 3D-lntegration, bei dem die Halbleiter-Wafer nach der Positionierung relativ zu einem Substrat und/oder einer Umverdrahtungsschicht (Redistribution Layer RDL) durch Einbringen einer Vergussmasse geschützt und in ihrer relativen Position fixiert werden. Weiterhin betrifft die Erfindung eine Vorrichtung zur Anwendung bei dem Verfahren, eine entsprechende integrierte Halbleiter-Wafer-Vorrichtung als Fertigungszwischenprodukt sowie als Endprodukt. The invention relates to a method for integrating semiconductor wafers in a small space, in particular 3D integration, in which the semiconductor wafers after positioning relative to a substrate and / or a redistribution layer (RDL) protected by introducing a potting compound and in be fixed in their relative position. Furthermore, the invention relates to a device for use in the method, a corresponding integrated semiconductor wafer device as a production intermediate and as an end product.

Die Halbleiterindustrie hat Dank kontinuierlicher Verbesserungen bei der Integrationsdichte verschiedener elektronischer Bauteile ein rasches Wachstum erfahren. Größtenteils geht diese Verbesserung der Integrationsdichte aus wiederholten Reduzierungen der minimalen Merkmalsgröße hervor, sodass mehr Bauteile in einen bestimmten Bereich integriert werden können. The semiconductor industry has experienced rapid growth thanks to continuous improvements in the integration density of various electronic components. For the most part, this improvement in integration density is due to repeated reductions in the minimum feature size, so more components can be integrated into a particular area.

Da die Nachfrage nach Miniaturisierung, höherer Geschwindigkeit und größerer Bandbreite sowie geringerem Stromverbrauch in jüngerer Zeit gestiegen ist, ist ein Bedarf an kleineren und kreativeren Packaging-Techniken von auch als Dies bezeichneten ungehäusten Halbleiter-Wafer entstanden. As demand for miniaturization, higher speed, and greater bandwidth, and lower power consumption has recently increased, a need has arisen for smaller and more creative packaging techniques of unpackaged semiconductor wafers, also referred to as dies.

Im Zuge der fortschreitenden Integration werden immer mehr Baugruppen, die zuvor als einzelne Halbleiter-Wafer nebeneinander auf einer Platine angebracht wurden, in einem „größeren" Halbleiter-Wafer vereint. Mit„größer" ist dabei die Anzahl der Schaltungen auf dem Die gemeint, da die absolute Größe durch fortschreitende Verfeinerung des As integration progresses, more and more assemblies, previously mounted as single semiconductor wafers next to each other on a board, are merged into a "larger" semiconductor wafer, with "larger" indicating the number of circuits on the die absolute size through progressive refinement of the

Fertigungsprozesses abnehmen kann. Can decrease manufacturing process.

In einer gestapelten Halbleitervorrichtung werden aktive Schaltungen wie Logik, Speicher, Prozessorschaltungen und dergleichen mindestens teilweise auf separaten Substraten hergestellt und danach physisch und elektrisch aneinander gebondet, um eine funktionelle Vorrichtung zu bilden. Solche Bonding-Prozesse wenden hochentwickelte Techniken an, wobei Verbesserungen gewünscht werden. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes employ sophisticated techniques and improvements are desired.

Eine Kombination von zwei sich ergänzenden Baugruppen, wie beispielsweise CPU und Cache auf einem Halbleiter-Wafer, lässt sich mit dem Begriff„on-Die" umschreiben: die CPU hat den Cache„on-Die", also direkt auf dem gleichen Halbleiter-Wafer, was den Datenaustausch deutlich beschleunigt. Mit der Weiterverarbeitung der Halbleiter-Wafer- Gehäusung und Integration in die schaltungstechnische Umgebung beschäftigt sich die Aufbau- und Verbindungstechnik (AVT). A combination of two complementary assemblies, such as CPU and cache on a semiconductor wafer, can be described by the term "on-die": the CPU has the cache "on-die", ie directly on the same semiconductor wafer, which considerably speeds up the data exchange The assembly and connection technology (AVT) deals with the further processing of the semiconductor wafer packaging and integration into the circuitry environment.

Viele integrierte Schaltungen werden üblicherweise auf einem einzigen Halbleiter-Wafer hergestellt und einzelne Halbleiter-Wafer auf dem Wafer werden vereinzelt, indem die integrierten Schaltungen entlang einer Risslinie gesägt werden. Die einzelnen Halbleiter- Wafer werden üblicherweise getrennt gekapselt, beispielsweise in Mehr-Halbleiter-Wafer - Modulen oder in anderen Arten von Gehäusen (Packaging). Many integrated circuits are typically fabricated on a single semiconductor wafer and individual semiconductor wafers on the wafer are singulated by sawing the integrated circuits along a tear line. The individual semiconductor wafers are usually encapsulated separately, for example in multi-semiconductor wafer modules or in other types of packages (packaging).

Eine Wafer-Level-Package-(WLP)-Struktur wird als eine Gehäusestruktur für A wafer level package (WLP) structure is used as a package structure for

Halbleiterkomponenten von elektrischen Produkten verwendet. Eine gestiegene Zahl von elektrischen Eingangs-Ausgangs-(l/0)-Kontakten und gestiegene Nachfrage nach integrierten Hochleistungsschaltungen (ICs) hat zur Entwicklung von WLP-Strukturen vom Fan-Out-Typ geführt, die größere Mittenabstände für die elektrischen I/O-Kontakte erlauben. Semiconductor components used by electrical products. An increase in the number of input / output (I / O) electrical contacts and increased demand for high performance integrated circuits (ICs) has led to the development of fan-out type WLP structures having larger center distances for the electrical I / O. Allow contacts.

Dabei kommt eine elektrische Umverdrahtungsstruktur zum Einsatz, die eine oder mehrere elektrische Umverdrahtungsschichten (Redistribution Layers: RDL) umfasst. Jede RDL kann als strukturierte Metallisierungsschicht ausgelegt sein und dient als elektrische In this case, an electrical rewiring structure is used, which comprises one or more electrical redistribution layers (redistribution layers: RDL). Each RDL can be designed as a structured metallization layer and serves as an electrical

Zwischenverbindung, die dafür ausgelegt ist, die in die Verkapselung eingebettete elektronische Komponente mit den externen Anschlüssen des Halbleiterbauelement- Package und/oder einer oder mehreren Elektrode(n) des/der an der Unterseite des An interconnect configured to package the electronic component embedded in the packaging with the external terminals of the semiconductor device package and / or one or more electrodes on the underside of the semiconductor device package

Halbleiterbauelement-Package angeordneten Halbleiter-Wafer zu verbinden. Semiconductor device package arranged to connect semiconductor wafers.

DE 10 2007 022 959 A1 zeigt ein Halbleiter-Package, bei dem ein Halbleiter-Wafer in eine Vergussmasse eingebettet ist. Eine Umverdrahtungsschicht ist mit Lötkugeln für eine Oberflächenmontage des Halbleiter-Wafer-Package versehen. Durchkontaktierungen durch das Halbleiter-Package sind mit Lötmaterial auf einer Oberfläche des Halbleiter-Package versehen, mit dem ein zweites Halbleiter-Package auf dem ersten gestapelt werden kann. DE 10 2007 022 959 A1 shows a semiconductor package in which a semiconductor wafer is embedded in a potting compound. A redistribution layer is provided with solder balls for surface mounting the semiconductor wafer package. Through-holes through the semiconductor package are provided with solder material on a surface of the semiconductor package with which a second semiconductor package can be stacked on top of the first.

Die US 6 716 670 B1 zeigt ein Halbleiter-Wafer-Package für die Oberflächenmontage. An einer Hauptoberfläche sind Kontakte vorgesehen, an denen ein zweites Halbleiter-Wafer- Package angebracht werden kann. Die DE 10 2006 033 175 A1 zeigt ein Elektronikmodul, das ein Logikteil und ein Leistungsteil umfasst. Logikteil und Leistungsteil sind auf übereinander angeordneten Substraten angeordnet und gemeinsam vergossen. US 6 716 670 B1 shows a surface mount semiconductor wafer package. On a main surface, contacts are provided to which a second semiconductor wafer package can be attached. DE 10 2006 033 175 A1 shows an electronic module comprising a logic part and a power part. Logic part and power unit are arranged on superposed substrates and potted together.

Außerdem beschreiben die US 2014/0091473 A1 und die US 2015/0069623 A1 die 3D- Halbleiter-Wafer-Integration von TSMC, wobei Halbleiter-Wafer in Kunststoffharz In addition, US 2014/0091473 A1 and US 2015/0069623 A1 describe the 3D semiconductor wafer integration of TSMC, semiconductor wafers in plastic resin

eingegossen werden und eine Durchkontaktierung als Through-Silicon-Vias erfolgt oder als Metallstege in die Vergussmasse eingebettet sind. be cast and a plated through hole as through-silicon vias or embedded as metal webs in the potting compound.

Weiterhin beziehen sich die US 2015/0303174 A1 auf die komplexe 3D-lntegration und die US 2017/0207204 A1 auf das„integrated fan out packaging". Furthermore, US 2015/0303174 A1 relates to the complex 3D integration and US 2017/0207204 A1 to the "integrated fan out packaging".

Das Einbringen der Vergussmasse kann zu einer relativen Verlagerung der Halbleiter-Wafer untereinander sowie gegenüber einer vorbestimmten Sollposition des Halbleiter-Wafers führen. Zudem kommt es aufgrund der erstarrungsbedingten Schrumpfung der The introduction of the potting compound can lead to a relative displacement of the semiconductor wafer with each other and with respect to a predetermined desired position of the semiconductor wafer. In addition, it comes due to the solidification-related shrinkage of

Vergussmasse zu Spannungen, die zu einer unebenen Verformung führen können. Potting compound to stresses that can lead to uneven deformation.

Weiterhin kommt es zu einem Driften der Halbleiter-Wafer auf dem Substrat aufgrund der dynamischen Kräfte der einströmenden Vergussmasse. Es ist auch bereits bekannt, dass die Bearbeitung der Rückseitenmetallisierung zu Wölbungsproblemen (engl,„warpage") führen kann. Furthermore, there is a drifting of the semiconductor wafer on the substrate due to the dynamic forces of the inflowing potting compound. It is also already known that the processing of the backside metallization can lead to buckling problems (English, "warpage").

Der Erfindung liegt die Aufgabe zugrunde, eine Möglichkeit zu schaffen, die damit verbundenen nachteiligen Einflüsse zu vermeiden. The invention has for its object to provide a way to avoid the associated adverse effects.

Diese Aufgabe wird erfindungsgemäß mit einem Verfahren gemäß den Merkmalen des Anspruches 1 gelöst. Die weitere Ausgestaltung der Erfindung ist in verfahrenstechnischer Hinsicht den weiteren Ansprüchen 2 bis 7 zu entnehmen. This object is achieved by a method according to the features of claim 1. The further embodiment of the invention can be seen in procedural terms the further claims 2 to 7.

Erfindungsgemäß ist also ein Verfahren vorgesehen, bei dem vor dem Einbringen von Vergussmasse ein Substrat aus Glas mit einer Vielzahl von durch Wandflächen oder besser ausgedrückt„Zwischenwände" getrennte Ausnehmungen zur Aufnahme von einem oder mehreren Halbleiter-Wafern relativ zu den Halbleiter-Wafern derart positioniert bzw. fixiert wird, dass zumindest einzelne Halbleiter-Wafer durch die Zwischenwand des Glas- Substrates voneinander getrennt sind. Indem also ein oder mehrere Halbleiter-Wafer in einer jeweiligen Ausnehmung angeordnet und separiert von anderen Halbleiter-Wafern According to the invention, therefore, a method is provided in which prior to the introduction of potting compound a substrate made of glass with a plurality of by wall surfaces or better expressed "partitions" separate recesses for receiving one or more semiconductor wafers positioned relative to the semiconductor wafers such or In this way, one or more semiconductor wafers are arranged in a respective recess and separated from other semiconductor wafers

angeordnet werden, sind diese vor den unerwünschten Einflüssen durch das Einbringen der Vergussmasse optimal geschützt. Bei Versuchen hat sich bereits herausgestellt, dass das Glassubstrat die Verlagerung der Halbleiter-Wafer parallel zur Haupterstreckungsebene des Substrates bzw. des die Halbleiter-Wafer tragenden Kunststoffsubstrates auf weniger als 100 μηη und je nach Ausführung auf weniger als 10 μηι beschränkt. Hierzu bildet das are arranged, they are optimally protected from the unwanted influences by the introduction of the potting compound. In experiments, it has already been found that the Glass substrate, the displacement of the semiconductor wafer parallel to the main extension plane of the substrate or of the semiconductor wafer-carrying plastic substrate to less than 100 μηη and depending on the design to less than 10 μηι limited. This forms the

Glassubstrat eine Maske mit den an die Halbleiter-Wafer angepassten Ausnehmungen, die vorzugsweise bereits mit Durchgangslöchern (Through Glass Via: TGV) ausgestattet sein können und eine Durchkontaktierung ermöglichen. Glass substrate, a mask with the recesses adapted to the semiconductor wafer, which may be preferably already equipped with through-holes (through glass via: TGV) and allow a via.

Erfindungsgemäß wird durch das Glassubstrat eine unerwünschte Verlagerung des According to the invention, an undesired displacement of the glass substrate by the

Halbleiter-Wafers ebenso wie eine Verformung des Trägersubstrates aufgrund der erheblich reduzierten Menge des Vergussmaterials ausgeschlossen. Darüber hinaus wird auch eine Dehnung, insbesondere thermische oder aufgrund veränderter Feuchtigkeit, vermieden. In positiver Weise wirkt sich dabei auch das erhöhte E-Modul des Glassubstrates auf den Herstellungsprozess sowie auf die Geräteeigenschaften aus. Zudem führt der Einsatz des Glassubstrates zu verbesserten HF-Eigenschaften, die zu vielfältigen praktischen Semiconductor wafers as well as a deformation of the carrier substrate due to the significantly reduced amount of the potting excluded. In addition, an elongation, in particular thermal or due to altered moisture, is avoided. In a positive way, the increased modulus of elasticity of the glass substrate also affects the manufacturing process as well as the device properties. In addition, the use of the glass substrate leads to improved RF properties, resulting in a variety of practical

Anwendungen in der Hochfrequenztechnik führt. Applications in high frequency technology leads.

Indem das Glassubstrat durch Laserstrahlung durch nichtlineare Selbstfokussierung bearbeitet und nachfolgend einem anisotropen Materialabtrag durch Ätzen mit einer angepassten Ätzrate und -dauer unterzogen wird, werden erstmals nahezu ebene By processing the glass substrate by laser radiation by non-linear self-focusing and subsequently subjected to an anisotropic removal of material by etching with an adapted etch rate and duration, are almost flat for the first time

Seitenwandflächen der Zwischenwände als Begrenzungsflächen der Ausnehmungen in dem Substrat erzeugt, sodass die Halbleiter-Wafer mit einem sehr geringen Abstand zu den Seitenwandflächen und infolgedessen auch zu benachbarten Halbleiter-Wafern angeordnet werden können. Side panels of the intermediate walls are produced as boundary surfaces of the recesses in the substrate, so that the semiconductor wafers can be arranged with a very small distance to the side wall surfaces and consequently also to adjacent semiconductor wafers.

Bei dem Verfahren zur Herstellung der die Seitenwandflächen bildenden Ausnehmungen in dem Glassubstrat kommt das laserinduzierte Tiefenätzen zum Einsatz, das unter der Bezeichnung LIDE (Laser Induced Deep Etching) bekannt geworden ist. Dabei ermöglicht das LIDE-Verfahren das Einbringen von extrem präzisen Löchern (Through Glass Via = TGV) und Strukturen in höchster Geschwindigkeit und schafft somit die Voraussetzungen für die Herstellung des Glassubstrates. In the method for producing the recesses forming the side wall surfaces in the glass substrate, the laser-induced deep etching is used, which has become known under the name LIDE (Laser Induced Deep Etching). The LIDE process enables the introduction of extremely precise holes (through glass via = TGV) and structures at high speed, thus creating the conditions for the production of the glass substrate.

Es wird grundsätzlich davon ausgegangen, dass das Glassubstrat nach der erfolgten Positionierung der Halbleiter-Wafer entweder auf einer Trägerschicht oder auf einer It is generally assumed that the glass substrate after the successful positioning of the semiconductor wafer either on a carrier layer or on a

Umverdrahtungsschicht (Redistribution Layer: RDL) mit dieser Schicht verbunden wird, wobei die Zwischenwände zwischen den Ausnehmungen die Halbleiter-Wafer jeweils allseitig einschließen. Darüber hinaus ist auch eine Fixierung der Halbleiter-Wafer in dem Glassubstrat unabhängig von einer Trägerschicht oder sonstigen Schicht denkbar, sodass Halbleiter-Wafer und Glassubstrat eine für den weiteren Produktionsprozess nutzbare Baueinheit bilden. Redistribution Layer (RDL) is connected to this layer, wherein the intermediate walls between the recesses enclose the semiconductor wafer on all sides. In addition, a fixation of the semiconductor wafer in the glass substrate, regardless of a carrier layer or other layer is conceivable, so that Semiconductor wafer and glass substrate form a usable for the further production process unit.

Dadurch lässt sich auch ein Verfahren realisieren, bei dem die Halbleiter-Wafer innerhalb der Ausnehmungen des Glassubstrates vergossen werden. Hierzu können die Halbleiter-Wafer in dem Glas-Substrat bestückt werden, sodass das Substrat gegebenenfalls entfallen könnte. As a result, it is also possible to realize a method in which the semiconductor wafers are cast within the recesses of the glass substrate. For this purpose, the semiconductor wafers can be fitted in the glass substrate, so that the substrate could possibly be omitted.

Weiterhin wird die erfindungsgemäße Aufgabe noch dadurch gelöst, dass das Glassubstrat mit einer Vielzahl von Ausnehmungen, die auch als Kavitäten bezeichnet werden, ausgestattet ist, welche die Halbleiter-Wafer mit einem geringen Spalt oder sogar anliegend einschließen, wobei die Ausnehmungen durch Seitenwandflächen begrenzt sind, die einen weitgehend ebenen Verlauf aufweisen, insbesondere also keine zwischen den Oberflächen des Glassubstrates reduzierte lichte Weite bzw. keinen konvex in die Ausnehmung hineinreichenden Wandflächenbereich aufweisen. Furthermore, the object according to the invention is additionally achieved in that the glass substrate is provided with a plurality of recesses, which are also referred to as cavities, which enclose the semiconductor wafers with a small gap or even fitting, wherein the recesses are delimited by side wall surfaces, have a largely flat course, in particular so no reduced between the surfaces of the glass substrate clear width or no convex extending into the recess wall surface area.

Dabei kann die Wandfläche einen V-förmigen Verlauf, also eine stetig zunehmende lichte Weite der Ausnehmung aufweisen, wobei die Steigung vorzugsweise konstant ohne In this case, the wall surface may have a V-shaped course, that is to say a continuously increasing clear width of the recess, the pitch preferably being constant without

Umkehrstelle ausgeführt sein kann. Reversing point can be executed.

Indem eine transparente, translucente oder transmissive Vergussmasse, beispielsweise ein Polymer verwendet wird, lässt sich erfindungsgemäß auch eine optische Verbindung zwischen verschiedenen Halbleiter-Wafern realisieren. By using a transparent, translucent or transmissive potting compound, for example a polymer, it is also possible according to the invention to realize an optical connection between different semiconductor wafers.

Eine spezifische Ausprägung des erfindungsgemäßen Verfahrens gemäß Anspruch 6 ist charakterisiert durch folgende Verfahrensschritte: A specific embodiment of the method according to the invention is characterized by the following method steps:

Bereitstellen eines Trägersubstrates mit mindestens einem darauf über eine  Providing a carrier substrate with at least one on it via a

Klebeschicht befestigten Halbleiter-Wafer, insbesondere Halbleiter-Bauelement, Adhesive layer attached semiconductor wafer, in particular semiconductor device,

Bereitstellen eines Glassubstrates mit mindestens einer Ausnehmung,  Providing a glass substrate having at least one recess,

Positionieren des Glassubstrates auf der Klebeschicht des Trägersubstrats derart, dass der mindestens eine Halbleiter-Wafer, insbesondere Halbleiter-Bauelement, in der mindestens einen Ausnehmung angeordnet ist,  Positioning the glass substrate on the adhesive layer of the carrier substrate in such a way that the at least one semiconductor wafer, in particular a semiconductor component, is arranged in the at least one recess,

Einbetten des mindestens einen Halbleiter-Wafers, insbesondere Halbleiter- Bauelements, in der mindestens einen Ausnehmung mittels einer Vergussmasse, sowie Embedding the at least one semiconductor wafer, in particular semiconductor component, in the at least one recess by means of a potting compound, and

Entfernen von Trägersubstrat und Klebefolie von der verbleibenden Packung aus Halbleiter-Wafer, Glassubstrat und Vergussmasse. In einer bevorzugten Weiterbildung kann dann auf die Packung mit elektrischem Kontakt zu dem mindestens einen Halbleiter-Wafer, insbesondere Halbleiter-Bauelement, eine Removing the carrier substrate and adhesive film from the remaining package of semiconductor wafer, glass substrate and potting compound. In a preferred development can then on the package with electrical contact to the at least one semiconductor wafer, in particular semiconductor device, a

Umverdrahtungsschicht und darauf Kontaktelemente, insbesondere Lotkugeln, aufgebracht werden. Redistribution layer and thereon contact elements, in particular solder balls, are applied.

Als bevorzugte Weiterbildung in vorrichtungstechnischer Hinsicht ist eine integrierte As a preferred development in device-technical terms is an integrated

Halbleiter-Wafer-Vorrichtung, insbesondere integrierte Halbleiter-Bauelement-Anordnung, als Fertigungs-Zwischenprodukt vorzugsweise hergestellt nach dem erfindungsgemäßen Verfahren durch folgende Merkmale charakterisiert: Semiconductor wafer device, in particular integrated semiconductor device arrangement, as a production intermediate, preferably produced by the method according to the invention, characterized by the following features:

ein Trägersubstrat,  a carrier substrate,

eine darauf angeordnete Klebefolie,  an adhesive film arranged thereon,

mindestens ein auf dieser Klebefolie befestigter Halbleiter-Wafer, insbesondere  at least one semiconductor wafer mounted on this adhesive film, in particular

Halbleiter-Bauelement, sowie Semiconductor device, as well

ein auf der Klebefolie befestigtes Glassubstrat mit zwischen sich Zwischenwände bildenden Ausnehmungen, in denen jeweils ein oder mehrere der Halbleiter-Wafer, insbesondere Halbleiter-Bauelemente mit einer Vergussmasse eingebettet sind.  a glass substrate fastened on the adhesive film with recesses forming between intermediate walls, in each of which one or more of the semiconductor wafers, in particular semiconductor components, are embedded with a potting compound.

Als daraus herstellbares fertiges Endprodukt ist erfindungsgemäß eine integrierte Halbleiter- Wafer-Vorrichtung vorgesehen, bei der durch Entfernung des Trägersubstrates und der Klebefolie ein Glassubstrat mit zwischen sich Zwischenwände bildenden Ausnehmungen übrig bleibt, in denen jeweils ein oder mehrere Halbleiter-Wafer, insbesondere Halbleiter- Bauelemente mit einer Vergussmasse eingebettet sind. Ferner weist die Vorrichtung eine Umverdrahtungsschicht in elektrischem Kontakt mit dem einen oder mehreren Halbleiter- Wafern, insbesondere Halbleiter-Bauelementen und Kontaktelemente, insbesondere Lotkugeln, auf der Umverdrahtungsschicht auf. According to the invention, a finished semiconductor product device that can be produced from this is an integrated semiconductor wafer device in which removal of the carrier substrate and the adhesive film leaves a glass substrate with recesses formed between intermediate walls, in each of which one or more semiconductor wafers, in particular semiconductor components embedded with a potting compound. Furthermore, the device has a rewiring layer in electrical contact with the one or more semiconductor wafers, in particular semiconductor components and contact elements, in particular solder balls, on the rewiring layer.

Zwischen- und Fertigprodukt vermeiden die oben bereits im Zusammenhang mit dem erfindungsgemäßen Verfahren beschriebenen Nachteile des Standes der Technik. Weitere bevorzugte Ausführungsformen gemäß den abhängigen Ansprüchen 8 und 1 1 bis 17 betreffen spezielle Merkmale und Parameter der erfindungsgemäßen Vorrichtung, die zur Vermeidung unnötiger Wiederholungen in der Beschreibung der Ausführungsbeispiele näher erläutert sind. Intermediate and finished products avoid the disadvantages of the prior art already described above in connection with the method according to the invention. Further preferred embodiments according to the dependent claims 8 and 1 1 to 17 relate to specific features and parameters of the device according to the invention, which are explained in detail in order to avoid unnecessary repetition in the description of the embodiments.

Die Erfindung lässt demnach verschiedene Ausführungsformen zu. Zur weiteren The invention accordingly allows for various embodiments. To further

Verdeutlichung der Grundprinzipien sind mehrere solcher Ausführungsbeispiele in den Zeichnungen dargestellt und nachfolgend beschrieben. Die Zeichnungen zeigen in Fig. 1 eine Vertikal-Schnittdarstellung eines Glassubstrats mit Ausnehmungen undClarification of the basic principles, several such embodiments are illustrated in the drawings and described below. The drawings show in Fig. 1 is a vertical sectional view of a glass substrate with recesses and

Durchkontaktierungen (TGV) in einer ersten Ausführungsform, Vias (TGV) in a first embodiment,

Fig. 2 eine Horizontal-Schnittdarstellung eines Glassubstrats mit Ausnehmungen und Durchkontaktierungen in einer zweiten Ausführungsform, 2 is a horizontal sectional view of a glass substrate with recesses and plated-through holes in a second embodiment,

Fig. 3 eine Vertikal-Schnittdarstellung eines Glassubstrats mit Ausnehmungen und Fig. 3 is a vertical sectional view of a glass substrate with recesses and

Durchkontaktierungen in einer dritten Ausführungsform,  Vias in a third embodiment,

Fig. 4 (a-f) ein Ablaufschema bei der Durchführung des erfindungsgemäßen Verfahrens zur Integration von Halbleiter-W afern, 4 (a-f) a flow chart in the implementation of the method according to the invention for the integration of semiconductor W afern,

Fig. 5 (a-d) Vertikal-Schnittdarstellungen verschiedener Ausführungsformen einer Fig. 5 (a-d) vertical sectional views of various embodiments of a

integrierten Halbleiter-Wafer-Vorrichtung als Fertigungs-Zwischenprodukt,  integrated semiconductor wafer device as a manufacturing intermediate,

Fig. 6 (a-c) schematische Vertikal-Schnittdarstellungen verschiedener weiteren Fig. 6 (a-c) are schematic vertical sectional views of various others

Ausführungsformen einer integrierten Halbleiter-Wafer-Vorrichtung als Fertigungs-Zwischenprodukt, sowie  Embodiments of a semiconductor integrated wafer device as a fabrication intermediate, as well

Fig. 7 - 9 schematische, ausschnittsweise Draufsichten verschiedener weiterer Fig. 7 - 9 are schematic, partial plan views of various others

Ausführungsformen einer integrierten Halbleiter-Wafer-Vorrichtung.  Embodiments of a semiconductor integrated wafer device.

Fig. 1 zeigt stellvertretend für alle Ausführungsformen die wichtigsten Merkmale der erfindungsgemäßen Glassubstrate 1 . Ein Glassubstrat 1 der Dicke D ist mit mehreren Ausnehmungen 2 und einem Abstand b versehen. In den die Ausnehmungen 2 umgebenden Zwischenwänden 3 des Glassubstrates 1 sind Durchgangslöcher 4 - sogenannte„Through Glass Vias", abgekürzt TGV) - angelegt, in denen in üblicher Weise eine Metallisierung 5 eingebracht ist. Das Glassubstrat 1 besteht zumindest im Wesentlichen aus einem alkalifreien Glas, insbesondere einem Alumoborosilikatglas oder Borosilikatglas. 1 shows, as representative of all embodiments, the most important features of the glass substrates 1 according to the invention. A glass substrate 1 of thickness D is provided with a plurality of recesses 2 and a distance b. Through holes 4 - so-called "through glass vias" (abbreviated to TGV) - are placed in the intermediate walls 3 of the glass substrate 1 surrounding the recesses 2, in which a metallization 5 is introduced in a conventional manner. The glass substrate 1 consists at least essentially of an alkali-free glass , in particular an aluminoborosilicate glass or borosilicate glass.

In Figur 2 ist die Draufsicht eines ähnlichen Glassubstrates 1 dargestellt, das wiederum in Draufsicht rechteckige Ausnehmungen 2 aufweist. Im Bereich der Zwischenwände 3 sind beiderseits der in Figur 2 links dargestellten Ausnehmung 2 mit Abstand davon deren Schmalseiten 6, 7 flankierende Durchgangslöcher 4 eingebracht. Weitere solche FIG. 2 shows the plan view of a similar glass substrate 1, which in turn has rectangular recesses 2 in plan view. In the area of the intermediate walls 3, on both sides of the recess 2 shown on the left in FIG. 2 at a distance therefrom, the narrow sides 6, 7 flanking through-holes 4 are introduced. Other such

Durchgangslöcher 4 liegen in zwei Reihen parallel unterhalb der in Fig. 2 rechts dargestellten Ausnehmung 2. Die Ausnehmungen 2 können - wie in Figur 1 dargestellt ist - als durchgehende Öffnungen, aber auch als Sacklöcher ausgebildet sein. Through holes 4 are located in two rows parallel below the recess 2 shown on the right in FIG. The recesses 2 can - as shown in Figure 1 - be formed as a continuous openings, but also as blind holes.

Bei der Ausführungsform eines Glassubstrates 1 gemäß Fig. 3 sind wiederum In the embodiment of a glass substrate 1 according to FIG. 3 are again

Ausnehmungen 2 mit dazwischenliegenden Zwischenwänden 3 eingebracht. Dabei sind jedoch die gegenüberliegenden Seitenwandflächen 8 der Ausnehmungen 2 nicht - wie bei der Ausführungsform gemäß Fig. 1 - senkrecht zur Hauptebene des Glassubstrates 1 angeordnet, sondern öffnen sich V-förmig nach oben bezogen auf Fig. 3, in dem die Recesses 2 introduced with intermediate walls 3 between them. However, the opposite side wall surfaces 8 of the recesses 2 are not arranged - as in the embodiment of FIG. 1 - perpendicular to the main plane of the glass substrate 1, but open in a V-shape with respect to FIG. 3, in which the

Seitenwandflächen 8 einen Flankenwinkel a gegenüber der Flächennormalen F zu dem Glassubstrat 1 einnehmen, der bis zu 10°, insbesondere bis zu 8° oder 5° betragen kann. Die Seitenflächen 8 müssen nicht unbedingt eben sein, sie können auch einen Side wall surfaces 8 occupy a flank angle a relative to the surface normal to the glass substrate 1, which may be up to 10 °, in particular up to 8 ° or 5 °. The side surfaces 8 need not necessarily be flat, they can also be a

sanduhrförmigen Verlauf mit der gegenüberliegenden Seitenfläche 8 bilden. form hourglass-shaped course with the opposite side surface 8.

Die weiteren geometrischen Verhältnisse bei den Glassubstraten 1 gemäß den Fig. 1 bzw. 3 stellen sich wie folgt dar: seine Materialstärke D kann beispielsweise < 500 μηη, The further geometric relationships in the glass substrates 1 according to FIGS. 1 and 3 are as follows: its material thickness D can be, for example, <500 μm,

vorzugsweise < 300 μηη oder noch bevorzugter < 100 μηη betragen. Die Wandstärke b der Zwischenwände 3 liegt bei < 500 μηη, bevorzugte Abstufungen liegen bei < 300 μηη, < 200 μηη, < 100 μηη oder < 50 μηη und ist vorzugsweise geringer als die Materialstärke D des Glassubstrates 1 . Dementsprechend kann das Verhältnis b/D der maximalen verbleibenden Wandstärke b zwischen zwei Ausnehmungen 2 im Glassubstrat 1 zu dessen Materialstärke D <1 : 1 , vorzugsweise < 2:3, < 1 :3 oder < 1 :6 sein. preferably <300 μηη or even more preferably <100 μηη. The wall thickness b of the intermediate walls 3 is <500 μm, preferred gradations are <300 μm, <200 μm, <100 μm or <50 μm and is preferably less than the material thickness D of the glass substrate 1. Accordingly, the ratio b / D of the maximum remaining wall thickness b between two recesses 2 in the glass substrate 1 to its material thickness D <1: 1, preferably <2: 3, <1: 3 or <1: 6 be.

Die Größe der Ausnehmungen 2 im Glassubstrat 1 wird grundsätzlich so gewählt, dass Halbleiter-Bauelemente 9 mit möglichst geringem Abstand zu den Seitenwandflächen 8 darin aufgenommen werden können. Die Positionen der Ausnehmungen 2 werden so gewählt, dass sie der gewünschten späteren Positionierung der Halbleiter-Bauelemente 9 in einer integrierten Halbleiter-Bauelement-Anordnung - einen sogenannten„Chip package" oder „Fan out package" - entsprechen. The size of the recesses 2 in the glass substrate 1 is basically chosen so that semiconductor components 9 can be accommodated therein with the smallest possible distance to the side wall surfaces 8. The positions of the recesses 2 are chosen so that they correspond to the desired later positioning of the semiconductor components 9 in an integrated semiconductor component arrangement - a so-called "chip package" or "fan out package".

Fig. 4 a) bis f) zeigt nun schematisch, wie ein erfindungsgemäßes Glassubstrat 1 in der Herstellung eines Chip-Packages verwendet werden kann. Fig. 4 a) zeigt als Fig. 4 a) to f) shows schematically how an inventive glass substrate 1 can be used in the manufacture of a chip package. Fig. 4 a) shows as

Ausgangssituation ein Trägersubstrat 10, das mit einer Klebefolie 1 1 versehen ist, auf die die Halbleiter-Bauelemente 9 positioniert sind. In Fig. 4 b) wird das vorher bereitgestellt Initial situation, a carrier substrate 10 which is provided with an adhesive film 1 1, on which the semiconductor devices 9 are positioned. In Fig. 4 b) that is provided in advance

Glassubstrat 1 auf die Klebefolie 1 1 gesetzt, wobei der oben erwähnte geringe Abstand zwischen den Seitenwandflächen 8 der Zwischenwände 3 und den diesen Glass substrate 1 placed on the adhesive film 1 1, wherein the above-mentioned small distance between the side wall surfaces 8 of the intermediate walls 3 and the latter

gegenüberliegenden Seiten der Halbleiter-Bauelemente 12 bei < 30 μηη, vorzugsweise < 20 μηι, < 10 μηη oder < 5 μηη liegt. Anschließend wird in Schritt c) eine Vergussmasse 12 in die Ausnehmungen 2 gegossen, um die Halbleiter-Bauelemente 9 in ihrer Position innerhalb des Glassubstrates 1 zu fixieren. In Schritt d) wird die Klebefolie 1 1 mit dem Trägersubstrat 10 abgelöst. Damit liegt eine kompakte Einheit des Glassubstrates 1 , darin eingebrachten Durchgangslöchern 4 mit Metallisierung 5 und in die Vergussmasse 12 eingebetteten Halbleiter-Bauelemente 9 vor. Anschließend wird in Schritt e) eine Umverdrahtungsschicht - eine sogenannte„RDL" - 13 auf der Seite der Einheit aufgebracht, auf der die elektronischen Bauelemente 9 frei liegen - in der Figur 4 e) ist dies die Oberseite, nachdem die Einheit gewendet wurde. Schließlich werden, wie in Figur 4 f) erkennbar ist, an entsprechenden Anschlusspunkten (nicht dargestellt) der Umverdrahtungschicht 13 Lotkugeln 14 zur Kontaktierung der Halbleiter- Bauelemente aufgebracht. opposite sides of the semiconductor devices 12 at <30 μηη, preferably <20 μηι, <10 μηη or <5 μηη. Subsequently, a potting compound 12 is poured into the recesses 2 in step c) in order to fix the semiconductor components 9 in their position within the glass substrate 1. In step d), the adhesive film 1 1 is detached with the carrier substrate 10. This is a compact unit of the glass substrate 1, introduced therein through holes 4 with metallization 5 and embedded in the potting compound 12 semiconductor devices 9 before. Subsequently, in step e), a redistribution layer - a so-called "RDL" - 13 is deposited on the side of the unit on which the electronic components 9 are exposed - in Figure 4 e) this is the top after the unit has been turned are, as can be seen in Figure 4 f), applied at corresponding connection points (not shown) of the redistribution layer 13 solder balls 14 for contacting the semiconductor devices.

Fig. 5 zeigt verschiedene Ausführungsformen einer integrierten Halbleiter-Bauelement- Anordnung, die jeweils bis Schritt c) in Fig. 4 bearbeitet wurden. Damit ist ein Fertigungs- Zwischenprodukt mit Trägersubstrat 10, Klebefolie 1 1 und einem Glassubstrat 1 mit einem oder mehreren Halbleiter-Bauelementen 9 in entsprechenden Ausnehmungen 2 mittels der Vergussmasse 12 fixiert implementiert. Fig. 5 a) zeigt ein Glassubstrat 1 mit einem einzelnen Halbleiter-Bauelement 9, Fig. 5 b) mit mehreren Bauelementen 9. In Fig. 5 c) sind im FIG. 5 shows various embodiments of a semiconductor integrated-device arrangement, each of which has been processed up to step c) in FIG. 4. In order for a manufacturing intermediate with carrier substrate 10, adhesive film 1 1 and a glass substrate 1 with one or more semiconductor devices 9 is implemented fixed in corresponding recesses 2 by means of the potting compound 12. Fig. 5 a) shows a glass substrate 1 with a single semiconductor device 9, Fig. 5 b) with several components 9. In Fig. 5 c) are in

Randbereich zu den Ausnehmungen 2 Durchgangslöcher 4 erzeugt worden, die zum Teil mit einer Metallisierung 5 gefüllt sind. Edge region to the recesses 2 through holes 4 have been generated, which are partially filled with a metallization 5.

Fig. 5 d) zeigt die Verwendung einer transparenten Vergussmasse 12, wodurch eine optische Datenkommunikation 15 zwischen den Halbleiter-Bauelementen 9 durch das transmissive Glassubstrat 1 hindurch ermöglicht wird. FIG. 5 d) shows the use of a transparent encapsulant 12, which enables optical data communication 15 between the semiconductor components 9 through the transmissive glass substrate 1.

Bei der in Fig. 6a gezeigten Ausführungsform ist die Ausnehmung 2 im Glassubstrat 1 so eng geschnitten, dass das Halbleiter-Bauelement 9 quasi in direktem Kontakt mit der Zwischenwand 3 auf dem Trägersubstrat 10 in seiner Position in dieser Ebene vorfixiert ist. In the embodiment shown in FIG. 6a, the recess 2 in the glass substrate 1 is cut so closely that the semiconductor component 9 is virtually prefixed in direct contact with the intermediate wall 3 on the carrier substrate 10 in its position in this plane.

Die Fig. 6b greift die in Figur 3 dargestellte Konfiguration auf, bei der die Seitenwandflächen 8 des Glassubstrat des in einem Flankenwinkel schräg gestellt sind. Die offene Bodenfläche der Ausnehmung 2 ist dabei wiederum so bemessen, dass das Halbleiter-Bauelement 9 mit seinem Fußbereich an dem unteren Rand der schräggestellten Seitenwandfläche 8 anliegt und somit ebenfalls eine Positionsvorfixierung des Bauelements stattfindet. Derselbe Effekt wird bei der in Figur 6c dargestellten Ausführungsform dadurch erzielt, dass zwei gegenüberliegende Seitenwandflächen 8 etwa auf halber Höhe jeweils mit V-förmigen Vorsprüngen 16 versehen sind, an denen das Halbleiter-Bauelementen 9 anliegt. FIG. 6b takes up the configuration shown in FIG. 3, in which the side wall surfaces 8 of the glass substrate are inclined at a flank angle. The open bottom surface of the recess 2 is in turn dimensioned so that the semiconductor device 9 rests with its foot on the lower edge of the inclined side wall surface 8 and thus also takes place a position pre-fixing of the device. The same effect is achieved in the embodiment shown in Figure 6c, characterized in that two opposite side wall surfaces 8 are provided approximately at half the height respectively with V-shaped projections 16 on which the semiconductor devices 9 is applied.

Um bei der engen Einpassung von Halbleiter-Bauelementen 9 in jeweiligen Ausnehmungen 2 des Glassubstrates 1 einem Verkanten des Bauelementes 9 entgegenzuwirken, können - wie in den Fig. 7 - 9 dargestellt ist - in den Eckbereichen der jeweiligen Ausnehmung 2 Aussparungen 17 für die Ecken der Bauelemente 9 im Glassubstrat 1 angelegt sein. In order to counteract tilting of the component 9 in the close fitting of semiconductor components 9 in respective recesses 2 of the glass substrate 1, as shown in FIGS. 7 to 9, recesses 17 for the corners of the recesses can be made in the corner regions of the respective recess 2 Components 9 may be created in the glass substrate 1.

Bei der Ausführungsform gemäß Fig. 8 sind zusätzlich von der Seitenwandfläche 8 hervorragende Anschläge 18 am Glassubstrat 1 angeordnet, wodurch sogenannte „Überbestimmtheiten" bei der Positionsfixierung des Halbleiter-Bauelementes 9 in der Ausnehmung 2 vermieden werden. In the embodiment according to FIG. 8, outstanding stops 18 are additionally arranged on the glass substrate 1 by the side wall surface 8, whereby so-called "overdeterminations" in the position fixing of the semiconductor component 9 in the recess 2 are avoided.

In der letzten Ausführungsform gemäß Fig. 9 schließlich ist die Vorfixierung des Halbleiter- Bauelementes 9 schließlich noch zusätzlich durch zwei Federelemente 19 in den den Anschlägen 18 gegenüberliegenden Seitenwandflächen 8 das Glassubstrates 1 weiter optimiert. Es ist allerdings darauf hinzuweisen, dass die Konstruktionselemente Aussparung 17, Anschlag 18 und Federelement 19 auch getrennt, jeweils einzeln oder auch in unterschiedlichen Kombinationen in verschiedenen Ausnehmungen 2 einer integrierten Halbleiter-Wafer-Vorrichtung eingesetzt werden können. Finally, in the last embodiment according to FIG. 9, the prefixing of the semiconductor component 9 is finally additionally optimized by two spring elements 19 in the side wall surfaces 8 opposite the stops 18, the glass substrate 1 being further optimized. It should be noted, however, that the construction elements recess 17, stop 18 and spring element 19 can also be used separately, individually or in different combinations in different recesses 2 of an integrated semiconductor wafer device.

Claims

PATE N TA N SP RÜ C H E PATE N TA N SP RU CHE 1 . Verfahren zur Integration von Halbleiter-Wafern, insbesondere Halbleiter-Bauelementen (9) auf engem Raum, insbesondere zur 3D-lntegration, bei dem das oder die Halbleiter- Wafer, insbesondere -Bauelemente (9) nach der Positionierung relativ zu einem 1 . Method for integrating semiconductor wafers, in particular semiconductor components (9) in a small space, in particular for 3D integration, in which the semiconductor wafer or wafers, in particular components (9) after positioning relative to a semiconductor wafer Trägersubstrat (10) und/oder einer Umverdrahtungsschicht (Redistribution Layer RDL) (13) durch Einbringen einer Vergussmasse (12) geschützt und in ihrer relativen Position fixiert werden, dadurch gekennzeichnet, dass vor dem Einbringen der Vergussmasse (12) ein Glassubstrat (1 ) mit einer Vielzahl von durch Zwischenwände (3) getrennten Ausnehmungen (2) zur Aufnahme von jeweils mindestens einem Halbleiter-Wafer, insbesondere Halbleiter- Bauelement (9) derart positioniert wird, dass der zumindest eine Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9), durch die ihm zugewandten Seitenwandflächen (8) der jeweiligen Zwischenwände (3) des Glassubstrates (1 ) umschlossen ist. Carrier substrate (10) and / or a rewiring layer (Redistribution Layer RDL) (13) protected by introducing a potting compound (12) and fixed in their relative position, characterized in that prior to the introduction of the potting compound (12) a glass substrate (1) with a multiplicity of recesses (2) separated by partition walls (3) for accommodating in each case at least one semiconductor wafer, in particular semiconductor component (9), such that the at least one semiconductor wafer, in particular semiconductor component (9) , is surrounded by the side wall surfaces (8) facing it of the respective intermediate walls (3) of the glass substrate (1). 2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, dass die Ausnehmungen (2) als Durchgangslöcher oder Sacklöcher ausgeführt werden. 2. The method according to claim 1, characterized in that the recesses (2) are designed as through holes or blind holes. 3. Verfahren nach den Ansprüchen 1 oder 2, dadurch gekennzeichnet, dass in das3. Process according to claims 1 or 2, characterized in that in the Glassubstrat (1 ) Durchgangslöcher (4) eingebracht werden, von denen zumindest einzelne vor der Fixierung der relativen Position der Halbleiter-Bauelemente (9) in den Glass substrate (1) through holes (4) are introduced, of which at least some prior to fixing the relative position of the semiconductor devices (9) in the Ausnehmungen (2) mit einer Metallisierung (5) zur Durchkontaktierung versehen werden. Recesses (2) are provided with a metallization (5) for the via. 4. Verfahren nach zumindest einem der vorhergehenden Ansprüche, dadurch 4. The method according to at least one of the preceding claims, characterized gekennzeichnet, dass die Halbleiter-Bauelemente (9) vor dem Einbringen der characterized in that the semiconductor components (9) before the introduction of the Vergussmasse (12) in der jeweiligen Ausnehmung (2) fixiert werden. Potting compound (12) in the respective recess (2) are fixed. 5. Verfahren nach Anspruch 4, dadurch gekennzeichnet, dass die Halbleiter- Bauelemente (9) durch Kontakt mit mindestens einer Seitenwandfläche (8) fixiert werden. 5. The method according to claim 4, characterized in that the semiconductor components (9) are fixed by contact with at least one side wall surface (8). 6. Verfahren nach Anspruch 5, dadurch gekennzeichnet, dass an der jeweiligen 6. The method according to claim 5, characterized in that at the respective Seitenwandfläche (8) ein oder mehrere Vorsprünge (16) und/oder Federelemente (19) zur Fixierung der Halbleiter-Bauelemente (9) verwendet werden. Side wall surface (8) one or more projections (16) and / or spring elements (19) are used for fixing the semiconductor devices (9). 7. Verfahren nach einem der vorgenannten Ansprüche, dadurch gekennzeichnet, dass7. The method according to any one of the preceding claims, characterized in that Aussparungen (17), insbesondere in den Eckbereichen der Ausnehmungen (2) Recesses (17), in particular in the corner regions of the recesses (2) des Glassubstrates (1 ) eingebracht werden. of the glass substrate (1) are introduced. 8. Verfahren nach zumindest einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass als Vergussmasse (12) ein transparentes oder transmissives Polymer verwendet wird. 8. The method according to at least one of the preceding claims, characterized in that a transparent or transmissive polymer is used as potting compound (12). 9. Verfahren zur Integration von Halbleiter-Wafern, insbesondere Halbleiter-Bauelementen, auf engem Raum, insbesondere zur 3D-lntegration, zur Herstellung eines Fan-Out-Package, insbesondere nach einem der vorgenannten Ansprüche, gekennzeichnet durch folgende Verfahrensschritte: 9. A method for integrating semiconductor wafers, in particular semiconductor components, in a small space, in particular for 3D integration, for producing a fan-out package, in particular according to one of the preceding claims, characterized by the following method steps: Bereitstellen eines Trägersubstrates (10) mit mindestens einem darauf über eine Klebeschicht (1 1 ) befestigten Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9), Providing a carrier substrate (10) with at least one semiconductor wafer, in particular a semiconductor component (9) attached thereto via an adhesive layer (11), Bereitstellen eines Glassubstrates (1 ) mit mindestens einer Ausnehmung (2), Providing a glass substrate (1) with at least one recess (2), Positionieren des Glassubstrates (1 ) auf der Klebeschicht (1 1 ) des Trägersubstrats (10) derart, dass der mindestens eine Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9), in der mindestens einen Ausnehmung (2) angeordnet ist,  Positioning the glass substrate (1) on the adhesive layer (1 1) of the carrier substrate (10) in such a way that the at least one semiconductor wafer, in particular semiconductor component (9), is arranged in the at least one recess (2), Einbetten des mindestens einen Halbleiter-Wafers, insbesondere Halbleiter- Bauelements (9), in der mindestens einen Ausnehmung (2) mittels einer Vergussmasse (12), sowie  Embedding the at least one semiconductor wafer, in particular semiconductor component (9), in the at least one recess (2) by means of a potting compound (12), and Entfernen von Trägersubstrat (10) und Klebefolie (1 1 ) von der verbleibenden Packung aus Halbleiter-Wafer (9), Glassubstrat (1 ) und Vergussmasse (12).  Removing the carrier substrate (10) and adhesive film (1 1) from the remaining package of semiconductor wafer (9), glass substrate (1) and potting compound (12). 10. Verfahren nach Anspruch 9, dadurch gekennzeichnet, dass auf die Packung mit elektrischem Kontakt zu dem mindestens einen Halbleiter-Wafer, insbesondere Halbleiter- Bauelement (9), eine Umverdrahtungsschicht (13) und darauf Kontaktelemente, 10. The method according to claim 9, characterized in that on the package with electrical contact to the at least one semiconductor wafer, in particular semiconductor component (9), a rewiring layer (13) and thereon contact elements, insbesondere Lotkugeln (14), aufgebracht werden. in particular solder balls (14) are applied. 1 1 . Vorrichtung mit einem Glassubstrat (1 ) zur Anwendung bei dem Verfahren nach zumindest einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Materialstärke (D) des Glassubstrates (1 ) geringer ist als 500 μηη, vorzugsweise geringer als 300 m oder 100 μηι. 1 1. Device with a glass substrate (1) for use in the method according to at least one of the preceding claims, characterized in that the material thickness (D) of the glass substrate (1) is less than 500 μηη, preferably less than 300 m or 100 μηι. 12. Integrierte Halbleiter-Wafer-Vorrichtung, insbesondere integrierte Halbleiter-Bauelement- Anordnung, als Fertigungs-Zwischenprodukt vorzugsweise hergestellt nach einem Verfahren gemäß einem oder mehreren der vorhergehenden Ansprüche 1 bis 10, 12. Integrated semiconductor wafer device, in particular integrated semiconductor device arrangement, as a production intermediate preferably produced by a method according to one or more of the preceding claims 1 to 10, gekennzeichnet durch marked by ein Trägersubstrat (10),  a carrier substrate (10), eine darauf angeordnete Klebefolie (1 1 ), mindestens ein auf dieser Klebefolie (1 1 ) befestigter Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9), an adhesive film (1 1) arranged thereon, at least one semiconductor wafer mounted on this adhesive film (11), in particular a semiconductor component (9), ein auf der Klebefolie (1 1 ) befestigtes Glassubstrat (1 ) mit zwischen sich  a glass substrate (1) fastened on the adhesive film (1 1) between them Zwischenwände (3) bildenden Ausnehmungen (2), in denen jeweils ein oder mehrere der Halbleiter-Wafer, insbesondere Halbleiter-Bauelemente (9) mit einer Vergussmasse (12) eingebettet sind. Partitions (3) forming recesses (2), in each of which one or more of the semiconductor wafer, in particular semiconductor components (9) are embedded with a potting compound (12). 13. Integrierte Halbleiter-Wafer-Vorrichtung, insbesondere integrierte Halbleiter-Bauelement- Anordnung, als fertiges Endprodukt in Form einer Fan-Out-Package, vorzugsweise hergestellt nach einem Verfahren gemäß einem oder mehreren der vorhergehenden 13. Integrated semiconductor wafer device, in particular integrated semiconductor device arrangement, as a finished end product in the form of a fan-out package, preferably produced by a method according to one or more of the preceding Ansprüche 1 bis 10, Claims 1 to 10, gekennzeichnet durch marked by ein Glassubstrat (1 ) mit zwischen sich Zwischenwände (3) bildenden Ausnehmungen (2), in denen jeweils ein oder mehrere Halbleiter-Wafer, insbesondere Halbleiter- Bauelemente (9) mit einer Vergussmasse (12) eingebettet sind,  a glass substrate (1) with recesses (2) forming between intermediate walls (3), in each of which one or more semiconductor wafers, in particular semiconductor components (9) are embedded with a potting compound (12), eine Umverdrahtungsschicht (13) in elektrischem Kontakt mit dem einen oder mehreren Halbleiter-Wafern, insbesondere Halbleiter-Bauelementen (9), und  a redistribution layer (13) in electrical contact with the one or more semiconductor wafers, in particular semiconductor devices (9), and Kontaktelemente, insbesondere Lotkugeln (14), auf der Umverdrahtungsschicht (13).  Contact elements, in particular solder balls (14), on the redistribution layer (13). 14. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 13, dadurch gekennzeichnet, dass die Wandstärke (b) der Zwischenwände (3) geringer ist als 500 μηη, vorzugsweise geringer als 300 μηι, 200 μηι, 100 μηη oder 50 μηι. 14. The device according to at least one of the preceding claims 1 1 to 13, characterized in that the wall thickness (b) of the intermediate walls (3) is less than 500 μηη, preferably less than 300 μηι, 200 μηι, 100 μηη or 50 μηι. 15. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 14, dadurch gekennzeichnet, dass die Wandstärke (b) der Zwischenwände (3) geringer ist als die Materialstärke (D) des Glassubstrats (1 ). 15. The device according to at least one of the preceding claims 1 1 to 14, characterized in that the wall thickness (b) of the intermediate walls (3) is less than the material thickness (D) of the glass substrate (1). 16. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 12, dadurch gekennzeichnet, dass das Verhältnis (b/D) der maximalen verbleibenden Wandstärke (b) der Zwischenwände (3) zwischen zwei Ausnehmungen (2) im Glassubstrat (1 ) zu der Materialstärke (D) des Substrats kleiner ist als 1 :1 , 2:3, 1 :3 oder 1 :6. 16. The device according to at least one of the preceding claims 1 1 to 12, characterized in that the ratio (b / D) of the maximum remaining wall thickness (b) of the intermediate walls (3) between two recesses (2) in the glass substrate (1) to the Material thickness (D) of the substrate is less than 1: 1, 2: 3, 1: 3 or 1: 6. 17. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 16, dadurch gekennzeichnet, dass der Abstand zwischen einer Seitenwandfläche (8) einer 17. Device according to at least one of the preceding claims 1 1 to 16, characterized in that the distance between a side wall surface (8) of a Zwischenwand (3) und einem Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9) kleiner ist als 30 μηη, 20 μηη, 10 μηη oder 5 μηη. Intermediate wall (3) and a semiconductor wafer, in particular semiconductor device (9) is smaller than 30 μηη, 20 μηη, 10 μηη or 5 μηη. 18. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 16, dadurch gekennzeichnet, dass der Abstand zwischen einer Seitenwandfläche (8) einer 18. Device according to at least one of the preceding claims 1 1 to 16, characterized in that the distance between a side wall surface (8) of a Zwischenwand (3) und einem Halbleiter-Wafer, insbesondere Halbleiter-Bauelement (9) insbesondere im Bereich von Vorsprüngen (16) der Seitenwandfläche (8) null ist. Partial wall (3) and a semiconductor wafer, in particular semiconductor component (9), in particular in the region of projections (16) of the side wall surface (8) is zero. 19. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 18, dadurch gekennzeichnet, dass die Seitenwandflachen (8) der Zwischenwände (3) zwischen den Ausnehmungen (2) einen Flankenwinkel (a) gegenüber der Flächennormalen (F) zu dem Glassubstrat (1 ) zwischen 0° und 10°, insbesondere < 8° oder < 5° aufweisen. 19. The device according to at least one of the preceding claims 1 1 to 18, characterized in that the side wall surfaces (8) of the intermediate walls (3) between the recesses (2) has a flank angle (a) relative to the surface normal (F) to the glass substrate (1 ) between 0 ° and 10 °, in particular <8 ° or <5 °. 20. Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 19, dadurch gekennzeichnet, dass zwei gegenüberliegende Seitenwandflächen (8) der Zwischenwände (3) einen V-förmigen und/oder sanduhrförmigen Verlauf, insbesondere zur Bildung von Vorsprüngen (16) zur Fixierung der Halbleiter-Bauelemente (9) in der jeweiligen 20. The device according to at least one of the preceding claims 1 1 to 19, characterized in that two opposite side wall surfaces (8) of the intermediate walls (3) has a V-shaped and / or hourglass-shaped course, in particular for the formation of projections (16) for fixing the Semiconductor devices (9) in the respective Ausnehmung (2), bilden. Recess (2), forming. 21 . Vorrichtung nach zumindest einem der vorhergehenden Ansprüche 1 1 bis 20, dadurch gekennzeichnet, dass das Glassubstrat (1 ) zumindest im Wesentlichen aus einem alkalifreien Glas besteht, insbesondere einem Alumoborosilikatglas oder Borosilikatglas. 21. Device according to at least one of the preceding claims 1 1 to 20, characterized in that the glass substrate (1) consists at least substantially of an alkali-free glass, in particular an aluminoborosilicate glass or borosilicate glass. 22. Vorrichtung nach einem der Ansprüche 1 1 bis 21 , dadurch gekennzeichnet, dass an der jeweiligen Seitenwandfläche (8) ein oder mehrere Anschläge (18), Vorsprünge (16) und/oder Federelemente (19) zur Fixierung der Halbleiter-Bauelemente (9) angeordnet sind. 22. Device according to one of claims 1 1 to 21, characterized in that on the respective side wall surface (8) one or more stops (18), projections (16) and / or spring elements (19) for fixing the semiconductor components (9 ) are arranged. 23. Vorrichtung nach einem der vorgenannten Ansprüche 1 1 bis 22, dadurch 23. Device according to one of the preceding claims 1 1 to 22, characterized gekennzeichnet, dass Aussparungen (17), insbesondere in den Eckbereichen der in that recesses (17), in particular in the corners of the Ausnehmungen (2), des Glassubstrates (1 ) eingebracht sind. Recesses (2), the glass substrate (1) are introduced.
EP18792891.6A 2017-11-10 2018-10-17 Method and device for the integration of semiconductor wafers Pending EP3707972A1 (en)

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