EP3547302B1

EP3547302B1 - Increased pwm depth in digital driving of active matrix displays

Info

Publication number: EP3547302B1
Application number: EP18182989.6A
Authority: EP
Inventors: Jan Genoe; Wim VAN EESSEN
Original assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Current assignee: Interuniversitair Microelektronica Centrum vzw IMEC
Priority date: 2018-03-30
Filing date: 2018-07-11
Publication date: 2024-04-24
Anticipated expiration: 2038-07-11
Also published as: TW201942893A; WO2019185947A1; EP3547302A1

Description

Field of the invention

The present invention relates to the field of digital driving of displays. More specifically it relates to methods for digitally driving active matrix displays, for instance AMOLED (Active Matrix Organic Light Emitting Diode) displays, so as to obtain high color accuracy, and to digital driving circuitry for active matrix displays, for instance AMOLED displays, providing high color accuracy.

Background of the invention

Prior art backplanes for AMOLED displays use a pixel driver circuit for each OLED, each pixel driver circuit driving a predetermined current through the corresponding OLED. Multiple pixel driver circuit schematics are being implemented, which all comprise a drive transistor (such as M1 in FIG. 1) driving the predetermined current through the OLED.
In an analog driving method an amplitude modulation approach is used, wherein each OLED emits light during a full frame period with an intensity corresponding to the required gray level. The current through the OLED is determined in accordance with an analog data voltage on the floating gate of the drive transistor M1. As this transistor M1 preferably operates in saturation for accurate current control, the current through the OLED (and thus the OLED luminance) varies with the square of the M1 gate voltage. This introduces non-linearity in the display response, limits accuracy and makes the display sensitive to noise. An overall display architecture as schematically shown in FIG. 2 is currently used for analog driven displays. At one edge of the display, a select line driver integrated circuit is provided. The select lines are digitally driven, for instance by a running one, cycling at a rate corresponding to the frame rate. At another edge of the display, data line driver circuitry is provided for driving the data lines. The data lines are driven by an analog voltage, keeping the pixels at a constant luminance during an entire image frame.
In a digital driving method a Pulse Width Modulation approach can be used, wherein each OLED emits light during a portion of a frame period, at a single luminance. In this approach the portion of the frame period during which an OLED emits light has a duration corresponding to the required gray level. A pulse current having a duty ratio in accordance with the data voltage is supplied to each OLED. In such known approach, a frame is divided into n sub-frames, wherein n is the number of bits used for digitally representing the image data. These n sub-frames may have a different duration, there being a ratio 1:2:4:8:....:2^n-1 between the different sub-frame durations. In each sub-frame a pixel (OLED) is either ON or OFF. In this way 2ⁿ different gray levels can be created. A display architecture is used wherein select lines (for instance rows) are digitally driven by dedicated timing control circuitry and wherein data lines (for instance columns) are driven by a digital voltage, as schematically illustrated in FIG. 3.
FIG. 4 shows a comparison between a typical analog pixel driving method (dashed lines) and a digital pixel driving method (full lines). In an analog driven pixel, the pixel luminance is constant during each image frame period and it can be different from frame to frame. The pixel luminance can have 2ⁿ different levels. In a digital driven pixel, a pixel is at full luminance(ON) during part of a frame period and at zero luminance (OFF) during the remaining part of the frame period. FIG. 4 is only a schematic representation, not showing a division in sub-frames for the digital driving approach.
WO 2014/068017 describes a method and digital driving circuitry for digital driving of an active matrix display with a predetermined frame rate, by means of pulse width modulation (PWM). To obtain high color accuracy, both under low-light intensity and under high-light intensity; the width of the pulses needs to be controlled very accurately. The described method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital code. The image frame is divided into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row, and upon a second selection, a second digital code is written to the selected row. This alternation of driving between both lines causes that the line driven first is typically half a time unit longer active than the other line. One way to avoid this half time unit difference is to swap the sequence of both lines during the next image frame, such that on average they have equal length. However, this implementation is not preferred, because it again gives a variation at half the frame refresh rate, which leads to possible subharmonics (e.g. a 30 Hz signal component in a display driven at 60 Hz), which may lead to causing flickering and hence should be avoided.
Documents US 2010/188393 and US 2012/320005 are directed to driver circuits and methods that make use of erase circuitry for a sub-frame controlled shortening of the light emission period.

Summary of the invention

It is an object of embodiments of the present invention to provide good methods for digital driving of active matrix displays, such as for instance, but not limited thereto, AMOLED displays, based on Pulse Width Modulation, so as to obtain high color accuracy.
The above objective is accomplished by a method and device set out in the appended set of claims.
Particular objects and advantages of various aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary recites merely some examples and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the drawings

FIG. 1 schematically shows an example of a prior art AMOLED pixel driver circuit, wherein an analog voltage on the gate of the drive transistor M1 determines the OLED luminance.
FIG. 2 schematically shows a prior art AMOLED display architecture using an analog driving method.
FIG. 3 schematically shows a prior art AMOLED display architecture using a digital driving method.
FIG. 4 shows a comparison in OLED current output between an analog pixel driving method as in FIG. 2 (dashed lines) and a digital driving method as in FIG. 3 (full lines).
FIG. 5 schematically shows a digitally driven AMOLED display architecture as an example of an active matrix display architecture in accordance with embodiments of the present invention.
FIG. 6 is a schematic representation of a time delay determination circuit of a select line driving circuit that can be used in embodiments of the present invention.
FIG. 7 is a schematic representation of a time delay determination circuit of a select line driving circuit comprising Output Enable circuitry.
FIG. 8 illustrates a hardware implementation of a bit counter which may be used in a 12-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 9 illustrates a hardware implementation of an adder which may be used in a 12-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 10 illustrates a hardware implementation of a look-up table which may be used in a 12-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 11, FIG. 12 and FIG. 13 illustrate a hardware implementation of a bit counter, an adder and a look-up table, respectively, which may be used in a 9-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 14, FIG. 15 and FIG. 16 illustrate a hardware implementation of a bit counter, an adder and a look-up table, respectively, which may be used in a 13-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 17, FIG. 18 and FIG. 19a and 19b illustrate a hardware implementation of a bit counter, an adder and a look-up table, respectively, which may be used in a 14-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 20, FIG. 21 and FIG. 22a and 22b illustrate a hardware implementation of a bit counter, an adder and a look-up table, respectively, which may be used in a 15-bit coding table optimisation algorithm in accordance with embodiments of the present invention.
FIG. 23, FIG. 24 and FIG. 25a and 25b illustrate a hardware implementation of a bit counter, an adder and a look-up table, respectively, which may be used in a 16-bit coding table optimisation algorithm in accordance with embodiments of the present invention.

The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.
Any reference signs in the claims shall not be construed as limiting the scope.
In the different drawings, the same reference signs refer to the same or analogous elements.

Detailed Description of illustrative embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention and how it may be practiced in particular embodiments. However, it will be understood that embodiments of the present invention may be practiced without necessarily having all these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the disclosure. While the present invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure.
It is to be noticed that the term "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.
OLED displays are displays comprising an array of light-emitting diodes in which the emissive electroluminescent layer is a film of organic compound which emits light in response to an electric current. OLED displays can either use passive-matrix (PMOLED) or active-matrix (AMOLED) addressing schemes. In case of OLED displays, the present invention relates to AMOLED displays. The corresponding addressing scheme makes use of a thin-film transistor backplane to switch each individual OLED pixel on or off. AMOLED displays allow for higher resolution and larger display sizes than PMOLED displays.
The present invention, however, is not limited to AMOLED displays, but in a broader concept relates to active matrix displays. Any type of active matrix displays may use the concepts of embodiments of the present invention, although AMOLED displays are particularly advantageous in view of the current switching speeds of their pixel elements. It is advantageous if the pixel elements of the active matrix displays can switch faster, as this allows to obtain higher frame rates, hence less flickering images.
An active matrix display, e.g. an AMOLED display, according to embodiments of the present invention comprises a plurality of pixels, each comprising a pixel element, e.g. an OLED element. The pixel elements are arranged in an array, and are logically organised in rows and columns. Throughout the description of the present invention, the terms "horizontal" and "vertical" (related to the terms "row" of "line" and "column", respectively) are used to provide a co-ordinate system and for ease of explanation only. They do not need to, but may, refer to an actual physical direction of the device. Furthermore, the terms "column" and "row" or "line" are used to describe sets of array elements which are linked together. The linking can be in the form of a Cartesian array of lines and columns; however, the present invention is not limited thereto. As will be understood by those skilled in the art, columns and lines can be easily interchanged and it is intended in this disclosure that these terms be interchangeable. Also, non-Cartesian arrays may be constructed and are included within the scope of the invention. Accordingly the terms "row" or "line" and "column" should be interpreted widely. To facilitate in this wide interpretation, the claims refer to logically organised in rows and columns. By this is meant that sets of pixel elements are linked together in a topologically linear intersecting manner; however, that the physical or topographical arrangement need not be so. For example, the rows may be circles and the columns radii of these circles and the circles and radii are described in this invention as "logically organised" rows and columns. Also, specific names of the various lines, e.g. select line and data line, are intended to be generic names used to facilitate the explanation and to refer to a particular function and this specific choice of words is not intended to in any way limit the invention. It should be understood that all these terms are used only to facilitate a better understanding of the specific structure being described, and are in no way intended to limit the invention.
Where in embodiments of the present invention reference is made to "selection" in "first selection" and "second selection", reference is made to an action in the circuit that enables data to be introduced. This could be, for example, multiplying a bit from a data code by one in a logical implementation. Alternatively, it may be seen as running a one in a select line of a circuit, changing the state of a transistor to introduce data from a data line. Hence, a first selection followed by a second selection may comprise introducing data a first time, followed by introducing data a second time.
In the context of the present invention, a frame is a single picture or single image that is shown as part of a sequence of pictures. For example, many single images or frames can be provided in succession to produce a video or a movie. The frame rate or frame frequency is the rate or frequency at which consecutive images (frames) are formed and displayed. The frame period (fp) is a time interval equal to the reciprocal of the frame frequency. It corresponds to the display period of a single frame or image.
A frame can be divided into sub-frames. In the analog way of display driving, each pixel is addressed once each frame. When the display is driven digitally using pulse width modulation, different pulse with different lengths are needed to obtain the different grey scales. The different timing moments to drive a pixel are grouped into sub-frames. The sub-frames which together form a frame, each have a subframe duration which lasts for only part of the total frame period; the sum of these parts of all sub-frames together forming a frame being equal to one frame period. Pixels in the frame which are very bright, may give a lot of intensity in all sub-frames, while pixels which are less bright may give more intensity in some sub-frames, and less intensity in other sub-frames, and pixels which are very dark may give little intensity in all sub-frames. In embodiments of the present invention, the duration of each of the sub-frames of a frame may be, but does not have to be, substantially equal. In those embodiments in which each sub-frame duration is substantially equal, each frame, which has a duration of one frame period fp, may be divided in N sub-frames with a duration of fp/N. Nonetheless, the present invention is not limited by equal duration of the sub-frames.
In some embodiments, N may be an arbitrary number. In certain embodiments, N may be equal to the number of bits used per image colour for representing the image data (N = n, n bit gray scale). For instance, exemplary embodiments are described wherein the number of sub-frames N is equal to the number of bits n, which in the example described is 8. In this example, 8 bits are used for representing each colour, e.g. for use in a 24 bit RGB (Red Green Blue) display. However, the present invention is not limited thereto, and the number of sub-frames can be different, e.g. larger or smaller than 8.
In those cases in which the number of bits n is not a power of two (i.e., n is not 4, 8, 16, etc), then N may be chosen as the number of bits n, so N = n as before; alternatively, N may be chosen equal to the power of two higher than, but closest to, n. In this case, for instance, if n = 5, 6 or 7, then N = 8, and if n = 11, 12, 14, then N = 16.
In one aspect, the present invention relates to methods for digital driving of pixels of active matrix displays, for instance AMOLED displays, with a predetermined frame rate. The display comprises a plurality of pixels logically organized in a plurality of rows and columns.
The method comprises representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code, and dividing the image into a natural number N (>1) of sub-frames. Each sub-frame is further divided into time slots, and a number of time slots are assigned to each bit of the n-bit image code according to each bit's significance in the code.
The method further comprises selecting each of the plurality of rows one first time per sub-frame, and subsequently for at least one sub-frame, a second time. This implies that at least one sub-frame will be sequentially selected twice. Data code corresponding to pixel data of image pixels to be represented and, in some embodiments, dummy data or reset data (a zero) is introduced with each selection. In preferred embodiments of the present selection, this sequence of first selection and second selection takes place in at least 35% of the sub-frames, or in at least half of the sub-frames. In certain embodiments, at least 75%, 80% or even more than 90% of sub-frames are selected twice.
The first selection and the second selection are performed sequentially for at least one and preferably more of the sub-frames. This means that there is a time delay between the first selection and the second selection, and this time delay may be different for each sub-frame.
In embodiments where the number of sub-frames N equals the number of bits (N = n), the time delay in at least one of the sub-frames, e.g. the x^th sub-frame, may equal 1 more or 1 less than 1/2^N-x of the sub-frame duration. The data introduced in each sub-frame is the bits in order from the least significant bit LSB to the most significant bit MSB.
In the prior art method as disclosed in WO 2014/068017 , for driving n bits, a frame is divided into 2ⁿ time slots, from which only 2ⁿ-1 time slots are used for effective driving. There remains one time slot that is unused. The present invention will use that one unused time slot for improving the driving scheme.
This is now illustrated by means of an example first illustrating the method of WO 2014/068017 .

In case the number of bits of the digital image code n = 5 bits, and the number of subframes N = 8, it is possible to drive the data to the pixel during a first and second selection in each sub-frame, for a number of time slots according to the significance of each data bit. Firstly, each sub-frame may be considered with the same duration. Each sub-frame is divided in time slots, which may also have the same duration. The number of time slots can be 2ⁿ/N = 2⁵/8 = 4 time slots per sub-frame (or 32 time slots for the whole frame). Now, each bit is assigned to a number of time slots according to their position, so the m^th bit (1≤m≤n), the first bit being the LSB and the n-th bit being the MSB, will be assigned to 2^m-1 time slots. In a data code with 5 bits, B4 B3 B2 B1 B0, the MSB bit B4 will be assigned to 2⁴ = 16 time slots. Bit B3 will be assigned to 8 time slots, B2 will be assigned to 4, B1 will receive 2 time slots and B0 will be introduced in the pixel during 2° = 1 time slot. The introduction of the data is performed twice per sub-frame, for instance according to Table 1. Each of the first three sub-frames are run with two selections. The first sub-frame is run with a zero for one time slot, the rest of the sub-frame is run with data bit B4. The second sub-frame is run with two selections, one time slot for bit B0, and the remaining three time slots for B4. The third sub-frame is selected twice, the first 2 time slots for driving bit B1, the second 2 time slots for driving B4. The remainder of the sub-frames are selected only once, for the bits B2, B3 and B4, the second selection not being needed. This way, all bits are represented longer according to their significance in the data code, and this in a homogeneous way, and utilizing most of the time slots (most of the frame) for driving data in the pixel.

Table 1

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
1 (1,3)	0	B4
2 (1,3)	B0	B4
3 (2,2)	B1	B4
4 (4,/)	B2	/
5 (4,/)	B3	/
6 (4,/)	B3	/
7 (4,/)	B4	/
8 (4,/)	B4	/

A similar example can be given for an 11-bit image code (n=11) and the number of subframes N = 16 (power of two higher than, but closest to, n). It is possible to drive the data to the pixel during a first and second selection in each sub-frame, for a number of time slots according to the significance of each data bit. Firstly, each sub-frame may be considered with the same duration. Each sub-frame is divided in time slots, which may also have the same duration. The number of time slots can be 2ⁿ/N = 2¹¹/16 = 128 time slots per sub-frame (or 2048 time slots for the whole frame). Now, each bit is assigned to a number of time slots according to their position, so the m^th bit (1≤m≤n), the first bit being the LSB and the n-th bit being the MSB, will be assigned to 2^m-1 time slots. In a data code with 11 bits, B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, the MSB bit B10 will be assigned to 2¹⁰ = 1024 time slots, bit B9 will be assigned 512 time slots, B8 will be assigned 256 time slots, B7 will be assigned 128 time slots, B6 will be assigned 64 time slots, B5 will be assigned 32 time slots, B4 will be assigned 16 time slots, B3 will be assigned to 8 time slots, B2 will be assigned to 4, B1 will receive 2 and B0 will be introduced in the pixel during 2° = 1 time slot. The introduction of the data is performed twice per sub-frame, for instance according to Table 2.

Table 2

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
1 (1,127)	0	B10
2 (1,127)	B0	B10
3 (2,126)	B1	B10
4 (128,/)	B9	/
5 (8,120)	B3	B10
6 (16,112)	B4	B10
7 (32,96)	B5	B10
8 (64,64)	B6	B10
9 (128,/)	B7	/
10 (128,/)	B8	/
11 (128,/)	B8	/
12 (4,124)	B2	B10
13 (128,/)	B9	/
14 (128,/)	B9	/
15 (128,/)	B9	/
16 (128,/)	B10	/

The minimal driving speed required for 60 Hz frames, 16 subframes per frame, 128 time slots per frame, and 2 lines selected per time slot, would be f_data = 60 * 16 * 128 * 2 = 246 kHz.

Of course it is desired to have the image data encoded with as many bits as possible. However, compared to the above example, if the image data is coded by n = 12 bits and the number of subframes is still N = 16 (power of two equal or higher than, but closest to, n), the required data rate increases severely. Again, each sub-frame may be considered with the same duration. Each sub-frame is divided in time slots, which may also have the same duration. The number of time slots can be 2ⁿ/N = 2¹²/16 = 256 time slots per sub-frame (or 4096 time slots for the whole frame). Again, each bit is assigned to a number of time slots according to their position, so the m^th bit (1≤m≤n), the first bit being the LSB and the n-th bit being the MSB, will be assigned to 2^m-1 time slots. A data code with 12 bits may be represented as B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, the MSB bit B11 and LSB B0. The introduction of the data is performed twice per sub-frame, for instance according to Table 3.

Table 3

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
1 (1,255)	0	B11
2 (1,255)	B0	B11
3 (2,254)	B1	B11
4 (4,252)	B2	B11
5 (8,248)	B3	B11
6 (16,240)	B4	B11
7 (32,224)	B5	B11
8 (64,192)	B6	B11
9 (128,128)	B7	B11
10 (256,/)	B8	/
11 (256,/)	B9	/
12 (256,/)	B9	/
13 (256,/)	B10	/
14 (256,/)	B10	/
15 (256,/)	B10	/
16 (256,/)	B10	/

The minimal driving speed required for 60 Hz frames, 16 subframes per frame, 256 time slots per frame, and 2 lines selected per time slot, would be f_data = 60 * 16 * 256 * 2 = 492 kHz.
In summary, for the above type of driving method as disclosed in WO 2014/068017 , in case the number of sub-frames N equals the power of 2 closest and not smaller than the number of bits n, and the sub-frames have substantially the same duration, for n-bit image code and each sub-frame divided in 2ⁿ/N time slots, then 2^m-1 time slots may be assigned to the m^th bit of the n-bit image code. Then, the MSB would be assigned with 2^n-1 time slots, the second MSB with 2^n-2, and so on until the LSB is assigned with 2° time slots (one time slot). The introduction of data is performed with two selections per sub-frame.
It can be seen from the above that, according to WO 2014/068/017 , for driving n bits, a frame is divided into 2ⁿ (in the example given 2⁵ = 32) time slots, from which only 2ⁿ-1 (16+8+4+2+1 = 31 for the case of n = 5) time slots are used for effective driving. There always remains one time slot that is unused. This can also be seen from the values 0 shown in Table 2 and Table 3, at the first time slot of subframe 1.
The inventors of the present invention have now found that exactly this one unused time slot can advantageously be used for improving the driving scheme, by recoding the bits. This has the advantage that an additional bit of color depth may be obtained, without having to increase the data rate.
In the further description, the coding method according to embodiments of the present invention is explained in more detail. In such coding method, the remaining unused time slot is used as an additional minimal length block (length 1). This block is indicated CX in Table 4 below.
To build a given coding table, in accordance with embodiments of the present invention, again each of the bits will be assigned to a number of time slots according to their position, with bits closer to the LSB bit having less time slots assigned than bits closer to the MSB. A difference compared to the method described in WO 2014/068017 , however, is that the number of time slots assigned to a bit value now no longer is a power of 2, but deviates therefrom. In this embodiment, the most significant bits are implemented as in the prior art, with the number of time slots assigned being a power of 2 of the value of the position of that bit in the image code. The first least significant bit is assigned 1 time slot. The further least significant bits are assigned a number of time slots which is larger than the number of time slots (larger than 2^m-1 for the m^th bit) which would be assigned if a power of 2 of the value of the position of that bit in the image code would be taken, and the middle significant bits are assigned a number of time slots which is smaller than the number of time slots (smaller than 2^m-1 for the m^th bit) which would be assigned if a power of 2 of the value of the position of that bit in the image code would be taken.
For a 12-bit input code B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, for instance, with 16 subframes being used, each subframe comprises maximal (any multiple of) 128 lines. Each image comprises in this approach typically 128 lines. If the image consists of more than 128 lines, the lines are grouped in blocks. e.g. a display of 1000 lines will be driven with this code as 128 blocks of 8 lines.
Driving each subframe comprises driving maximum 2 pulses of in total 256 timeslots.

Time slots acc to prior art 1 2 4 8 16 32 64 128 256 512 1024 2048

Bit number B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

The number of time slots assigned to each bit value can be as follows:

Time slots acc to invention 1 3 5 11 15 31 63 127 255 512 1024 2048 1

Bit number C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 CX
This shows that, in this embodiment, the least significant bit B0 is assigned 1 time slot (indicated by C0), the second least significant bit B1 (indicated by C1) is assigned 3 time slots, where in the prior art it would have been 2^m-1=2, m being the position of the bit in the code, bit B2 (indicated by C2) is assigned 5 time slots, and bit B3 (indicated by C3) is assigned 11 time slots. In the example illustrated, bits C1 to C3 are the ones being assigned more time slots than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the least significant bits should always be uneven.
Correspondingly, the middle significant bits B4 to B8 each are assigned less time slots, for instance one time slot less, than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the middle significant bits can be uneven.
The most significant bits B9 to B11 are implemented just at their actual value according to their position in the code, if a power of 2 is taken. The MSB bit B11 will be assigned 2¹¹ = 2048 time slots (indicated by C11), B10 will be assigned to 2¹⁰ = 1024 time slots (indicated by C10), bit B9 will be assigned 512 time slots (indicated by C9).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for at least one of the least significant bits, less than 2^m-1 for at least one of the middle significant bits, and exactly 2^m-1 for the most significant bits, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 8 to FIG. 10. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C11, C10, C9, ..., C5, C4 are directly connected to the input bits B11, B10, B9, ..., B5, B4. The driving bits C8, C7, C6, C5, C4 are each one time slot short compared to the time slots that would be assigned in the prior art. Hence 5 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 8, the active bits in this range having 1 time slot short are counted, B3 B2 B1 B0 (input) covers [0 ... 15]. The needed range to be covered for compensating for the 5 time slots which are short in the middle significant bits is the sum of both, as illustrated in FIG.9, hence [0 ... 20]. C3 C2 C1 C0, including the extra CX covers [0 ... 21]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 10.

One implementation of a coding table for this example may be as illustrated in Table 4. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 4

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (128,/)	C10	/	2k=256
1 (0,128)	C0	C11	2k+1=1	2k-1=255
2 (1,127)	C1	C11	2k+1=3	2k-1=253
3 (128,/)	C9	/	2k=256
4 (5,123)	C3	C11	2k+1=11	2k-1=245
5 (112,16)	C11	C5	2k+1=225	2k-1=31
6 (128,/)	C10	/	2k=256
7 (31,97)	C6	C11	2k+1=63	2k-1=193
8 (64,64)	C11	C7	2k+1+129	2k-1=127
9 (128,/)	C10	/	2k=256
10 (7,121)	C4	C11	2k+1=15	2k-1=241
11 (128,/)	C9	/	2k=256
12 (2,126)	C2	C11	2k+1=5	2k-1=251
13 (128,/)	C10	/	2k=256
14 (127,1)	C8	CX	2k+1=255	2k-1=1
15 (128,/)	C11	/	2k=256

This table (Table 4) is assigned values as if the image code were 11 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2¹¹/16 = 128 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=128 time slots is proposed, in the actual implementation 256 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
For instance, in the example of Table 4, the proposed value for the first subframe is 128. This means that the bit C10 is run for 256 time slots upon the first selection, and that no second selection is required. In the second subframe, the proposed values are 0 for the first selection and 128 for the second selection. This means that the bit C0 is run for 1 time slot upon the first selection, and the bit C11 is run for 255 time slots upon the second selection.
It can be seen that the length of the pulses becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=11 bits.
When implementing the above example of Table 4, the minimal driving speed required for 60 Hz frames, 16 subframes per frame, 128 time slots per frame, and 2 lines selected per time slot, would be f_data = 60 * 16 * 128 * 2 = 246 kHz. It can thus be seen that advantageously an additional bit of color depth may be obtained, without having to increase the data rate. Or alternatively worded: the demanded driver speed is only half the prior art implementation for an equal color depth.
Similarly, other examples can be given.
For instance, a 9-bit input string may be coded as if it were an 8-bit input string. 8 subframes are used. Each subframe comprises maximal (any multiple of) 32 lines Each image comprises in this approach typically 32 lines. If the image consists of more than 32 lines, the lines are grouped in blocks. e.g. a display of 1000 lines will be driven with this code as 32 blocks of 32 lines, whereas the last 24 lines are virtual lines. Driving each subframe comprises driving maximum 2 pulses of in total 64 timeslots.
The 9-bit input code may have a binary representation B8 B7 B6 B5 B4 B3 B2 B1 B0.

Time slots acc to prior art 1 2 4 8 16 32 64 128 256

Bit number B0 B1 B2 B3 B4 B5 B6 B7 B8

the number of time slots assigned to each bit value can be as follows:

Time slots acc to invention 1 3 5 11 15 31 64 126 255 1

Bit number C0 C1 C2 C3 C4 C5 C6 C7 C8 CX
This shows that the least significant bit B0 is assigned 1 time slot (indicated by C0), the second least significant bit B1 (indicated by C1) is assigned 3 time slots, where in the prior art it would have been 2^m-1=2, m being the position of the bit in the code, bit B2 (indicated by C2) is assigned 5 time slots, and bit B3 (indicated by C3) is assigned 11 time slots. In the example illustrated, bits C1 to C3 are being assigned more time slots than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the least significant bits is uneven.
Correspondingly, other bits, the middle significant bits B4, B5 and the most significant bits B7, B8 each are assigned less time slots, for instance one time slot less for B4, B5 and B8 (indicated C4, C5 and C8), and 2 time slots less for B7 (indicated C7), than would have been the case in the prior art.
An intermediate significant bit between the middle significant bits and the most significant bit, B6 is implemented just at its actual value according to its position in the code, if a power of 2 is taken. The intermediate bit 6 will be assigned 2⁶ = 64 time slots (indicated by C6).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for at least one of the least significant bits, in this embodiment is less than 2^m-1 for at least one of the middle significant bits and for at least one of the most significant bits, and exactly 2^m-1 for an intermediate significant bits, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 11 to FIG. 13. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C8, C7, C6, C5, C4 are directly connected to the input bits B8, B7, B6, B5, B4. The driving bits C8, C5, C4 are each one time slot short compared to the time slots that would be assigned in the prior art, and C7 is two time slots short. Hence 5 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 12, the active bits in this range having time slots short are counted, B3 B2 B1 B0 (input) covers [0 ... 15]. The needed range to be covered for compensating for the 5 time slots which are short in the middle significant bits is the sum of both, as illustrated in FIG.9, hence [0 ... 20]. C3 C2 C1 C0, including the extra CX covers [0 ... 21]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 12.

One implementation of a coding table for this example may be as illustrated in Table 5. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 5

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (0,32)	C0	C7	2k+1=1	2k-1=63
1 (1,31)	C1	C8	2k+1=3	2k-1=61
2 (2,30)	C2	C8	2k+1=5	2k-1=59
3 (5,27)	C3	C8	2k+1=11	2k-1=53
4 (7,25)	C4	C8	2k+1=15	2k-1=49
5 (16,16)	C8	C5	2k+1=33	2k-1=31
6 (31,1)	C7	CX	2k+1=63	2k-1=1
7 (32,/)	C6	/	2k=64

This table (Table 5) is assigned values as if the image code were 8 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2⁸/8 = 32 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=32 time slots is proposed, in the actual implementation 64 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
For instance, in the example of Table 5, the proposed values for the first subframe are 0 for the first selection and 32 for the second selection. This means that the bit C0 is run for 1 time slot upon the first selection, and that during a second selection the bit C7 is run for 63 time slots. In the second subframe, the proposed values are 1 for the first selection and 31 for the second selection. This means that the bit C1 is run for 3 time slots upon the first selection, and the bit C8 is run for 61 time slots upon the second selection.
It can be seen that the length of the pulses becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=8 bits. Or in other words: if the separation between the driven lines corresponds to k lines, the block is driven 2k+1 or 2k-1 time slots.
When implementing the above example of Table 5, the minimal driving speed required for 60 Hz frames, 8 subframes per frame, 32 time slots per frame, and 2 lines selected per time slot, would be f_data = 60 * 8 * 32 * 2 = 31 kHz. It can thus be seen that advantageously an additional bit of color depth may be obtained, without having to increase the data rate. Or alternatively worded: the demanded driver speed is only half the prior art implementation for an equal color depth.
For a 13-bit input code B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, for instance, 16 subframes may be used. Each subframe comprises maximal (any multiple of) 256 lines. Each image comprises in this approach typically 256 lines. If there are less lines in the display, virtual lines are added up to 256 lines. In the timing they are considered to be present, but they are not actually driven. If the image consists of more than 256 lines, the lines are grouped in blocks. e.g. a display of 1000 lines will be driven with this code as 256 blocks of 4 lines. Driving each subframe comprises driving maximum 2 pulses of in total 512 timeslots.

Time slots acc to prior art 1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Bit number B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

The number of time slots assigned to each bit value can be as follows:

Time slots acc to invention 1 3 5 11 15 31 63 127 255 512 1024 2048 4096 1

Bit number C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 CX
This shows that the least significant bit B0 is assigned 1 time slot (indicated by C0), the second least significant bit B1 (indicated by C1) is assigned 3 time slots, where in the prior art it would have been 2^m-1=2, m being the position of the bit in the code, bit B2 (indicated by C2) is assigned 5 time slots, and bit B3 (indicated by C3) is assigned 11 time slots. In the example illustrated, bits C1 to C3 are the ones being assigned more time slots than would have been the case in the prior art. In accordance with this embodiment of the present invention, the number of time slots assigned to the least significant bits should always be uneven.
Correspondingly, the middle significant bits B4 to B8 each are assigned less time slots, for instance one time slot less, than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the middle significant bits in this embodiment can be uneven.
The most significant bits B9 to B12 are implemented just at their actual value according to their position in the code, if a power of 2 is taken. The MSB bit B12 will be assigned 2¹² = 4096 time slots (indicated C12), B11 will be assigned 2¹¹ = 2048 time slots (indicated by C11), B10 will be assigned to 2¹⁰ = 1024 time slots (indicated by C10), bit B9 will be assigned 512 time slots (indicated by C9).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for at least one of the least significant bits, less than 2^m-1 for at least one of the middle significant bits, and exactly 2^m-1 for the most significant bits, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 14 to FIG. 16. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C12, C11, C10, C9, ..., C5, C4 are directly connected to the input bits B12, B11, B10, B9, ..., B5, B4. The driving bits C8, C7, C6, C5, C4 are each one time slot short compared to the time slots that would be assigned in the prior art. Hence 5 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 14, the active bits in this range having 1 time slot short are counted, B3 B2 B1 B0 (input) covers [0 ... 15]. The needed range to be covered for compensating for the 5 time slots which are short in the middle significant bits is the sum of both, as illustrated in FIG.15, hence [0 ... 20]. C3 C2 C1 C0, including the extra CX covers [0 ... 21]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 16.

One implementation of a coding table for this example may be as illustrated in Table 6. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 6

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (0,256)	CX	C12	2k+1=1	2k-1=511
1 (0,256)	C0	C12	2k+1=1	2k-1=511
2 (1,255)	C1	C12	2k+1=3	2k-1=509
3 (2,254)	C2	C12	2k+1=5	2k-1=507
4 (5,251)	C3	C11	2k+1=11	2k-1=501
5 (7,249)	C4	C11	2k+1=15	2k-1=497
6 (13,243)	C11	C12	2k+1=27	2k-1=485
7 (256,/)	C10	/	2k=512
8 (15,241)	C5	C12	2k+1=31	2k-1=481
9 (31,225)	C6	C12	2k+1=63	2k-1=449
10 (63,193)	C7	C12	2k+1=127	2k-1=385
11 (127,129)	C8	C12	2k+1=255	2k-1=257
12 (255,1)	C11	C12	2k+1=511	2k-1=1
13 (256,/)	C9	/	2k=512
14 (256,/)	C11	/	2k=512
15 (256,/)	C10	/	2k=512

This table (Table 6) is assigned values as if the image code were 12 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2¹²/16 = 256 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=256 time slots is proposed, in the actual implementation 512 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
For instance, in the example of Table 6, the proposed values for the first subframe are 0 for the first selection and 256 for the second selection. This means that the bit CX is run for 1 time slot upon the first selection, and that during a second selection the bit C12 is run for 511 time slots. In the second subframe, the proposed values are again 0 for the first selection and 256 for the second selection. This means that the bit C0 is run for 1 time slot upon the first selection, and the bit C12 is run for 511 time slots upon the second selection. The proposed values for the third subframe are 1 for the first selection and 255 for the second selection. This means that the bit C1 is run for 3 time slots upon the first selection, and the bit C12 is run for 509 time slots upon the second selection.
It can be seen that the length of the pulses becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=12 bits (although it actually consists of 13 bits).
When implementing the above example of Table 6, the minimal driving speed required for 60 Hz frames, 16 subframes per frame, 512 time slots per frame, and 2 lines selected per time slot, would be f_data = 60 * 16 * 512 * 2 = 983 kHz. Advantageously an additional bit of color depth may be obtained, without having to increase the data rate. Or alternatively worded: the demanded driver speed is only half the prior art implementation for an equal color depth.
Similarly, but explained in less detail, for a 14-bit input code B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, for instance, 16 subframes may be used. Each subframe comprises maximal (any multiple of) 512 lines. Each image comprises in this approach typically 512 lines. If there are less lines in the display, virtual lines are added up to 512 lines. In the timing they are considered to be present, but they are not actually driven. If the image consists of more than 512 lines, the lines are grouped in blocks. e.g. a display of 1000 lines will be driven with this code as 512 blocks of 2 lines, whereas the last 24 lines are virtual lines. Driving each subframe comprises driving maximum 2 pulses of in total 1024 timeslots.

Time slots acc to prior art 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192

Bit number B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

The number of time slots assigned to each bit value can be as follows:

Time slots acc to invention 1 3 5 11 17 31 63 127 255 511

Bit number C0 C1 C2 C3 C4 C5 C6 C7 C8 C9

Time slots acc to invention 1024 2048 4096 8191 1

Bit number C10 C11 C12 C13 CX
This shows that the least significant bit B0 is assigned 1 time slot (indicated by C0). The bits B1, B2, B3, B4 are assigned 3, 5, 11, 17 time slots, respectively (indicated by C1, C2, C3, C4). In the example illustrated, bits C1 to C4 are the ones being assigned more time slots than would have been the case in the prior art. In accordance with this embodiment of the present invention, the number of time slots assigned to the least significant bits is uneven.
Correspondingly, the middle significant bits B5 to B9 and the most significant bit B13 each are assigned less time slots, for instance one time slot less, than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the middle significant bits and to the most significant bit in this embodiment is uneven.
The most significant bits B10 to B12 are implemented just at their actual value according to their position in the code, if a power of 2 is taken. The MSB bit B12 will be assigned 2¹² = 4096 time slots (indicated C12), B11 will be assigned 2¹¹ = 2048 time slots (indicated by C11), and B10 will be assigned to 2¹⁰ = 1024 time slots (indicated by C10).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for some of the bits, less than 2^m-1 for at least one of other bits, and exactly 2^m-1 for yet at least one other bit, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 17, FIG. 18, FIG. 19a and FIG. 19b. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C13, C12, C11, C10, C9, ..., C5 are directly connected to the input bits B13, B12, B11, B10, B9, ..., B5. The driving bits C13, C9, C8, C7, C6, C5 are each one time slot short compared to the time slots that would be assigned in the prior art. Hence 6 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 17, the active bits in this range having 1 time slot short are counted. B4 B3 B2 B1 B0 (input) covers [0 ... 31]. The needed range to be covered for compensating for the 6 time slots which are short in the middle significant bits is the sum of both, as illustrated in FIG.18, hence [0 ... 37]. C4 C3 C2 C1 C0, including the extra CX covers [0 ... 38]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 19a and FIG. 19b.

One implementation of a coding table for this example may be as illustrated in Table 7. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 7

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (0,512)	CX	C13	2k+1=1	2k-1=1023
1 (0,512)	C0	C13	2k+1=1	2k-1=1023
2 (1,511)	C1	C13	2k+1=3	2k-1=1021
3 (2,510)	C2	C13	2k+1=5	2k-1=1019
4 (5,507)	C3	C13	2k+1=11	2k-1=1013
5 (8,504)	C4	C13	2k+1=17	2k-1=1007
6 (15,497)	C5	C13	2k+1=31	2k-1=993
7 (31,481)	C6	C13	2k+1=63	2k-1=961
8 (63,449)	C7	C12	2k+1=127	2k-1=897
9 (66,446)	C12	C12	2k+1=133	2k-1=891
10 (127,385)	C8	C12	2k+1=255	2k-1=769
11 (255,257)	C9	C12	2k+1=511	2k-1=513
12 (446,66)	C12	C13	2k+1=893	2k-1=131
13 (512,/)	C11	/	2k=1024
14 (512,/)	C11	/	2k=1024
15 (512,/)	C10	/	2k=1024

This table (Table 7) is assigned values as if the image code were 13 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2¹³/16 = 512 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=512 time slots is proposed, in the actual implementation 1024 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
the length of the pulses becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=13 bits (although it actually consists of 14 bits).
As a further example, for a 15-bit input code B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, for instance, 16 subframes may be used. Each subframe comprises maximal (any multiple of) 1024 lines. Each image comprises in this approach typically 1024 lines. If there are less lines in the display, virtual lines are added up to 1024 lines. In the timing they are considered to be present, but they are not actually driven. If the image consists of more than 1024 lines, the lines are grouped in blocks. e.g. a display of 4000 lines will be driven with this code as 1024 blocks of 4 lines, whereas the last 96 lines are virtual lines. Driving each subframe comprises driving maximum 2 pulses of in total 2048 timeslots.

Time slots acc to prior art 1 2 4 8 16 32 64 128 256 512 1024

Bit number B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10

Time slots acc to prior art 2048 4096 8192 16384

Bit number B11 B12 B13 B14

The number of time slots assigned to each bit value can be as follows:

Time slots acc to invention	1	3	5	11	19	31	63	127	255	511	1023
Bit number	C0	C1	C2	C3	C4	C5	C6	C7	C8	C9	C10
Time slots acc to invention							2048	4096	8191	16383	1
Bit number							C11	C12	C13	C14	CX

This shows that the least significant bit B0 is assigned 1 time slot (indicated by C0). The bits B1, B2, B3, B4 are assigned 3, 5, 11, 19 time slots, respectively (indicated by C1, C2, C3, C4). In the example illustrated, bits C1 to C4 are the ones being assigned more time slots than would have been the case in the prior art. In accordance with this embodiment of the present invention, the number of time slots assigned to the least significant bits is uneven.
The middle significant bits B5 to B10 and the most significant bits B13 and B14 each are assigned less time slots, for instance one time slot less, than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the middle significant bits and to the most significant bits in this embodiment is uneven.
The intermediate significant bits B11 and B12 between the middle significant bits and the most significant bits are implemented just at their actual value according to their position in the code, if a power of 2 is taken. The intermediate significant bit B12 will be assigned 2¹² = 4096 time slots (indicated C12), and B11 will be assigned 2¹¹ = 2048 time slots (indicated by C11).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for some of the bits, less than 2^m-1 for at least one of other bits, and exactly 2^m-1 for yet at least one other bit, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 20, FIG. 21, FIG. 22a and FIG. 22b. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C14, C13, C10, C9, ..., C5 are directly connected to the input bits B14, B13, B10, B9, ..., B5. The driving bits C14, C13, C10, C9, C8, C7, C6, C5 are each one time slot short compared to the time slots that would be assigned in the prior art. Hence 8 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 20, the active bits in this range having 1 time slot short are counted. B4 B3 B2 B1 B0 (input) covers [0 ... 31]. The needed range to be covered for compensating for the 8 time slots which are short in the middle significant bits is the sum of both, as illustrated in FIG.21, hence [0 ... 39]. C4 C3 C2 C1 C0, including the extra CX covers [0 ... 40]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 21a and FIG. 21b.

One implementation of a coding table for this example may be as illustrated in Table 8. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 8

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (0,1024)	CX	C14	2k+1=1	2k-1=2047
1 (0,1024)	C0	C14	2k+1=1	2k-1=2047
2 (1,1023)	C1	C14	2k+1=3	2k-1=2045
3 (2,1022)	C2	C14	2k+1=5	2k-1=2043
4 (5,1019)	C3	C14	2k+1=11	2k-1=2037
5 (9,1015)	C4	C14	2k+1=19	2k-1=2029
6 (15,1009)	C5	C14	2k+1=31	2k-1=2017
7 (31,993)	C6	C14	2k+1=63	2k-1=1985
8 (63,961)	C7	C13	2k+1=127	2k-1=1921
9 (66,958)	C12	C13	2k+1=133	2k-1=1915
10 (127,897)	C8	C13	2k+1=255	2k-1=1793
11 (255,769)	C9	C13	2k+1=511	2k-1=1537
12 (511,513)	C10	C13	2k+1=1023	2k-1=1025
13 (957,67)	C12	C14	2k+1=1915	2k-1=133
14 (1024,/)	C12	/	2k=2048
15 (1024,/)	C11	/	2k=2048

This table (Table 8) is assigned values as if the image code were 14 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2¹⁴/16 = 1024 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=1024 time slots is proposed, in the actual implementation 2048 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
The length of the pulses thus becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=14 bits (although it actually consists of 15 bits).

As a last example, for a 16-bit input code B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0, for instance, 16 subframes may be used. Each subframe comprises maximal (any multiple of) 2048 lines. Each image comprises in this approach typically 2048 lines. If there are less lines in the display, virtual lines are added up to 2048 lines. In the timing they are considered to be present, but they are not actually driven. If the image consists of more than 2048 lines, the lines are grouped in blocks. e.g. a display of 4000 lines will be driven with this code as 2048 blocks of 2 lines, whereas the last 96 lines are virtual lines. Driving each subframe comprises driving maximum 2 pulses of in total 4096 timeslots.

Time slots acc to prior art	1	2	4	8	16	32	64	128	256	512	1024	2048
Bit number	B0	B1	B2	B3	B4	B5	B6	B7	B8	B9	B10	B11
Time slots acc to prior art									4096	8192	16384	32768
Bit number									B12	B13	B14	B15

The number of time slots assigned to each bit value can be as follows:

Time slots acc to invention	1	3	5	11	21	31	63	127	255	511	1023	2047
Bit number	C0	C1	C2	C3	C4	C5	C6	C7	C8	C9	C10	C11
Time slots acc to invention								4096	8191	16383	32767	1
Bit number								C12	C13	C14	C15	CX

This shows that the least significant bit B0 is assigned 1 time slot (indicated by C0). The bits B1, B2, B3, B4 are assigned 3, 5, 11, 21 time slots, respectively (indicated by C1, C2, C3, C4). In the example illustrated, bits C1 to C4 are the ones being assigned more time slots than would have been the case in the prior art. In accordance with this embodiment of the present invention, the number of time slots assigned to the least significant bits is uneven.
The middle significant bits B5 to B11 and the most significant bits B13 to B15 each are assigned less time slots, for instance each one time slot less, than would have been the case in the prior art. In accordance with embodiments of the present invention, the number of time slots assigned to the middle significant bits and to the most significant bits in this embodiment is uneven.
The intermediate significant bit B12 between the middle significant bits and the most significant bits is implemented just at its actual value according to its position in the code, if a power of 2 is taken. The intermediate significant bit B12 will be assigned 2¹² = 4096 time slots (indicated C12).
The assigning of the number of time slots to each of the bit values (e.g. more than 2^m-1 for some of the bits, less than 2^m-1 for at least one of other bits, and exactly 2^m-1 for yet at least one other bit, m being the position of the corresponding bit in the image code) must be such that all intensity values can be covered. In accordance with embodiments of the present invention, this can be done by assigning a value 1 to the otherwise unused time slot CX.
The coding table may be implemented as illustrated in FIG. 23, FIG. 24, FIG. 25a and FIG. 25b. The driving bits which code the same amount of time slots as if they would have been coded in a prior art power of 2 coding or less, i.e. in this embodiment C15, C14, C13, C10, C9, ..., C5 are directly connected to the input bits B15, B14, B13, B10, B9, ..., B5. The driving bits C15, C14, C13, C10, C9, C8, C7, C6, C5 are each one time slot short compared to the time slots that would be assigned in the prior art. Hence 10 time slots need to be compensated for in the least significant bits. As illustrated in FIG. 23, the active bits in this range having 1 time slot short are counted. B4 B3 B2 B1 B0 (input) covers [0 ... 31]. The needed range to be covered for compensating for the 10 time slots which are short in the middle significant bits and most significant bits is the sum of both, as illustrated in FIG.24, hence [0 ... 41]. C4 C3 C2 C1 C0, including the extra CX covers [0 ... 42]. Depending on the outcome of the addition, CX has a value 1 or 0, to be able to compensate for the lacking time slots, as illustrated in FIG. 25a and FIG. 25b.

One implementation of a coding table for this example may be as illustrated in Table 9. In this table, the first column gives the definition in old time slots, corresponding to the shifting of the line. The last two columns give the definition in terms of new time slots, taking into account the additional delay between driving the 1st line and the second line. The second and the third column give the value of the code driven in each of the blocks, respectively.

Table 9

Sub-Frame number (length code a, code b)	code driven after running one a	code driven after running one b
0 (0,2048)	CX	C14	2k+1=1	2k-1=4095
1 (0,2048)	C0	C14	2k+1=1	2k-1=4095
2 (1,2047)	C1	C14	2k+1=3	2k-1=4093
3 (2,2046)	C2	C14	2k+1=5	2k-1=4091
4 (4,2044)	C14	C15	2k+1=9	2k-1=4087
5 (5,2043)	C3	C15	2k+1=11	2k-1=4085
6 (10,2038)	C4	C15	2k+1=21	2k-1=4075
7 (15,2033)	C5	C15	2k+1=31	2k-1=4065
8 (31,2017)	C6	C15	2k+1=63	2k-1=4033
9 (63,1985)	C7	C15	2k+1=127	2k-1=3969
10 (127,1921)	C8	C15	2k+1=255	2k-1=3841
11 (255,1793)	C9	C15	2k+1=511	2k-1=3585
12 (511,1537)	C10	C13	2k+1=1023	2k-1=3073
13 (513,1535)	C15	C13	2k+1=1027	2k-1=3069
14 (1023,1025)	C11	C13	2k+1=2047	2k-1=2049
15 (2048,/)	C12	/	2k=4096

This table (Table 9) is assigned values as if the image code were 15 bits, hence 1 bit less than the actual input data, meaning that there would be 2ⁿ/N = 2¹⁵/16 = 2048 time slots per sub-frame. The recoding of the bits in accordance with the present invention, however, takes into account the amended number of time slots assigned. If, during the first selection, running a data bit during k=2048 time slots is proposed, in the actual implementation 4096 (2k) time slots are used for running that data bit, In such case, no second selection takes place. If, during the first selection, another value k is proposed for running the data bit, in the actual implementation 2k+1 time slots are used. During the subsequent second selection another value k is proposed for running another data bit, and in the actual implementation 2k-1 time slots are used.
The length of the pulses thus becomes 2k or 2k+1 for pulses in the first selection, and 2k-1 for pulses in the second selection, with k being the number of time slots proposed if the image code would consist of n=15 bits (although it actually consists of 16 bits).
FIG. 5 schematically shows a digital driven AMOLED display architecture 50, as a particular type of active matrix display, in accordance with an aspect of the present invention. This architecture 50 comprises an AMOLED display 55 comprising an array of OLED pixel elements (not illustrated in detail in FIG. 5) logically organised in rows and columns. The driving circuitry for driving these OLED pixel elements is based on digital select line (row) driving circuitry 51 using two select signals for at least one of the rows, for instance implemented by running ones, and digital data line (column) driving circuitry 52. Digital driving can be done for instance using Pulse Density Modulation methods, for instance Pulse Width Modulation. It is an advantage of this architecture as compared to existing digital driving architectures that switching of the transistors in the backplane of the display can be slower and that the driving circuitry can be less complex and less space consuming.
In a method for digital pixel driving according to an aspect of the present invention, the select line driving circuitry 51 provides two select signals, for instance two running ones, providing a first selection and a second selection, thereby sequentially selecting at least one, and preferably at least 35% of the plurality of rows, twice within each sub-frame. Within the sub-frames which are selected twice, the second select signal, for instance the second running one, has a fixed predetermined delay with respect to the first running one. This predetermined delay can be different for each sub-frame, thus enabling different digital output combinations, as further explained.
The method first and second selection of rows is as described in WO 2014/068017 , The only difference is the number of time slots assigned to the bit values, as explained above.
In the example shown in Table 4, in the first sub-frame, the fixed delay between the first running one and the second running one corresponds to the duration of 256 time slots. This means that no second selection will be made. In the 256 time slots of the first sub-frame, the pixel is driven by one of the most significant bits (C10). If C10 is a logical 1, the pixel is ON during these 256 time slots; if C10 is a logical 0, the pixel is OFF. In the second sub-frame the fixed delay between the first running one and the second running one corresponds to the duration of 1 time slot (i.e., 2k+1). In the first time slot of the second sub-frame the pixel has bit value C0 and in the remaining 255 time slots of the second sub-frame the most significant bit (C11) drives the pixel. If the most significant bit is a logical 1, the pixel is ON during these 255 time slots; if the most significant bit is a logical 0, the pixel is OFF. In the third sub-frame the fixed delay between the first running one and the second running one corresponds to the duration of 3 time slots (i.e., 2k+1). In the first three time slots of the third sub-frame one of the least significant bits (C1) drives the pixel, and in the remaining 253 time slots of the third sub-frame again the most significant bit (C11) drives the pixel. This continues similarly for the other subframes.
In another aspect, the present invention relates to digital driving circuitry for driving an active matrix display such as, but not limited thereto, an AMOLED display arranged with pixels, the display comprising, for instance, LED pixel elements or OLED pixel elements such as fluorescent OLEDs, phosphorescent OLEDs, or light-emitting polymers, or Quantum dot LEDs (QLEDs). The pixels can be logically arranged in rows and columns, so the display forms a matrix capable of displaying images in consecutive frames of a certain duration.
The digital driving circuitry may comprise digital select line driving circuitry 51 for sequentially selecting the plurality of rows and digital data line driving circuitry 52 for writing the digital image code, represented by an n-bit image code, to corresponding pixels in a selected row. The digital select line driving circuitry 51 is adapted for sequentially selecting, within one sub-frame, at least one of the plurality of rows twice, so as to, upon a first selection, write a first digital code to the selected row and, upon a second selection, write a second digital code to the selected row, there being a predetermined time delay between the second selection and the first selection.
FIG. 6 shows an exemplary select line driving circuit 90 that can be used for generating a first and a second select signal under the form of a first running one and a second running one. In the select line driving circuit 90 shown in FIG. 6, the first running one and the second running one are each generated using a linear array 91, 92 of D-flip-flops, each array 91, 92 comprising maximum a single logical one, which advances through the array of flip- flops 91, 92 by one position each clock pulse. The first running one advances row by row through the lines of the display 55, progressing one row at each clock pulse. The second running one also advances row by row through the lines of the display 55, progressing one row at each clock pulse, but with a delay corresponding to a predetermined number of clock pulses with respect to the first running one. The invention is not restricted to D-flip-flops; any other suitable implementation of a dynamic or static shift register can be used. An even more compact implementation of the time delay determination circuit is a transparent latch with, for instance, two or three clocks.
As can be seen from FIG. 6, in order not to provide the first and the second select signal to the same row at the same time, a number of selectors, e.g. multiplexers 93_i, are provided, having as input both the first and the second select signal, and as output any of the first or second select signal, depending on a control signal for controlling the selectors 93_i, which control signal may be emanating from a controller and may be generated taking into account the number of time slots the code needs to be applied.
Consider, for instance, a first and a second running one are cycling through the arrays 91, 92 of D flip-flops, the first running one for instance residing in flip-flop 91₂ and the second running one residing in flip-flop 92₁, there thus being a delay of 1 clock cycle between both. The control signal to the selectors 93_i may be such that during a first time period, equal to a first predetermined number of time slots, the first running one is applied to the rows, and during a second time period, equal to a second predetermined number of time slots, the second running one is applied to the rows. During the first time period, the first running one will be applied to the row corresponding and connected to selector 93₂, and image data present on and provided by the data line driving circuitry 52 will be put on this corresponding row. During the second time period, the second running one will be applied to the row corresponding and connected to selector 93₁, and image data present on and provided by the data line driving circuitry 52 will be put on this corresponding row. This way, data cannot be written to two rows simultaneously, despite the two select signals, e.g. two running ones, being present in the digital select line driving circuitry 51.
Alternatively to the embodiment illustrated in FIG. 6, a select line driving circuit 100 as illustrated in FIG. 7 can be used, in which the multiplexers 93_ihave been substituted by output enable circuitry 101, grouped in blocks according to the minimum delay between selections. An odd number of clocks may be provided for driving the output enable circuitry 101.

Claims

A method for digital driving of an active matrix display (55) comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, the display (55) being driven with a predetermined frame rate and row time, the method comprising:
- representing n-bit wide pixel data for each of the plurality of pixels of an image frame to be displayed by a corresponding binary codeword of bit length n+1, wherein a first one (CX) of the bits composing the codeword forms a first block and the remaining n bits (C0, ..., Cn-1) of the codeword form a second block;

- dividing the image frame into a natural number N of sub-frames, each sub-frame being further divided into time slots, each time slot having a duration equal to one half of said row time during said digital driving;

- assigning a number of said time slots to each bit of the codeword;

- within at least one sub-frame, sequentially selecting at least one of the plurality of rows twice, wherein upon a first selection a first bit of the codewords representative of pixels of the selected row is written to the pixels of the selected row and upon a second selection a second bit of the codewords representative of pixels of the selected row, different from the written first bit, is written to the pixels of the selected row, there being a predetermined time delay between the second selection and the first selection;
characterized in that
said step of assigning further includes assigning one time slot to the bit (CX) of the first block of the codeword and assigning one or more time slots to each bit (C0, ..., Cn-1) of the second block of the codeword in accordance with the bit position in the second block, wherein the number of time slots assigned to most significant bits of the second block are natural powers of two and the number of time slots assigned to least significant bits of the second block are odd positive integers; and

the time delay between the second selection and the first selection in at least one of the sub-frames, expressed in a number of time slots, deviates from a natural power of two.
A method according to claim 1, wherein the time delay between the second selection and the first selection in the at least one sub-frame is one time slot longer than the delay 2k needed for sequentially selecting k rows k being a non-negative integer.
A method according to claim 2, wherein upon the second selection in that at least one sub-frame, the second bit of the codewords is written to the respective pixels of the selected row during a number of time slots equal to one less than the delay 2k needed for sequentially selecting said k rows.
A method according to any of the previous claims, wherein dividing the image frame comprises dividing the image frame into sub-frames of substantially equal duration.
A method according to any of claims 1 to 4, n not being a natural power of two, wherein dividing the image frame into sub-frames comprises dividing the image frame into N sub-frames, wherein N is the power of 2 superior and closest to n.
A method according to claim 5, wherein each sub-frame is further divided into 2ⁿ/N time slots.
A method according to claim 6, further assigning more than 2^m-1 time slots, m≥0, to the m^th bit of the second block of the codeword, if the m^th bit belongs to the least significant bits of the second block.
A method according to any of claims 6 or 7, further assigning less than 2^m-1 time slots, m≥0, to the m^th bit of the second block of the codeword, if the m^th bit belongs to the middle significant bits of the second block.
A method according to any of claims 6 to 8, further assigning 2^m-1 time slots, m≥0, to the m^th bit of the second block of the codeword, if the m^th bit belongs to the most significant bits of the second block.
A method according to any of the previous claims, wherein writing the first bit of the codeword and writing the second bit of the codeword comprises using pulse-width modulation.
Digital driving circuitry for driving, with a predetermined frame rate and row time, an active matrix display (55) comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, so as to display subsequent sub-frames of an image frame to be displayed, the digital driving circuitry comprising:
- bit recoding hardware adapted for converting n-bit wide pixel data (B0, ..., Bn-1) of the image frame to be displayed into a corresponding binary codeword of bit length n+1, wherein a first one (CX) of the bits composing each codeword forms a first block and the remaining n bits (C0, ..., Cn-1) of each codeword form a second block,

- digital select line driving circuitry (51) for sequentially selecting the plurality of rows at intervals corresponding to one row time, said row time being subdivided into two time slots of equal duration,
the digital select line driving circuitry (51) being adapted for sequentially selecting, within one sub-frame, at least one of the plurality of rows twice, so as to, upon a first selection, write a first bit of the codeword to the selected row and, upon a second selection, write a second bit of the codeword, different than the first written bit, to the selected row, there being a predetermined time delay between the second selection and the first selection,

- digital data line driving circuitry (52) for writing the codewords to corresponding pixels in a selected row,
characterized in that
one time slot is associated with the bit (CX) of the first block of the codeword and one or more time slots are associated with each bit (C0, ..., Cn-1) of the second block of the codeword in accordance with the bit position in the second block, wherein an odd integer number of time slots is associated with each one of the least significant bits in the second block and 2^m time slots are associated with each one of the most significant bits of the second block, where m denotes the bit position in the second block,

the time delay between the second selection and the first selection in at least one of the sub-frames, expressed in a number of time slots, deviates from a natural power of two,

the bit recoding hardware is configured to relay most significant bits of the n-bit wide pixel data from respective input connectors of the bit recoding hardware to corresponding output connectors of the bit recoding hardware,

the bit recoding hardware comprises a bit counting circuit configured to determine active bits within the range of middle significant bits of the n-bit wide pixel data and count the differences in time slots between the 2^m time slots represented by the position m of each active bit in the pixel data and the number of time slots associated with the middle significant bit of the second block corresponding to the active bit,

the bit recoding hardware comprises an adder configured to add the counted differences in time slots to the binary number represented by the least significant bits of the n-bit wide pixel data, and

the bit recoding hardware comprises a look-up-table storing a corresponding codeword portion for each possible output from the adder, said codeword portion comprising the bit of the first block and the middle and least significant bits of the second block.
Digital driving circuitry according to claim 11, wherein the digital select line driving circuitry (51) comprises a time delay implementation circuit for implementing the predetermined time delay between the second selection and the first selection.
Active matrix display (55) comprising an array of light emitting elements arranged for being driven by a digital driving circuitry according to any of claims 11 or 12.
Active matrix display (55) according to claim 13, wherein the active matrix display is an AMLED display, an AMOLED display or an AMQLED display.
Active matrix display (55) according to claim 14, wherein the light emitting elements are any of crystalline semiconducting LEDs, fluorescent OLEDs, phosphorescent OLEDs, light emitting polymers, Quantum dot QLEDs.