EP3446328A1 - Multilayer photoreceptor device, layers of which have different lattice parameters - Google Patents

Abstract

The invention relates to a photoreceptor device, including at least: a first crystalline semiconductor (11) having a first lattice parameter; and a second crystalline semiconductor, deposited on the first semiconductor, and having a second lattice parameter that is different from the first lattice parameter. In particular: the device includes an interface layer (12) between the first and second semiconductors, said layer being made from an amorphous material and structured to include apertures that are regularly spaced in the plane of the layer; the second semiconductor includes protuberances that extend out of the apertures of the interface layer and that form separate crystal grains (10), each grain having a plurality of facets making at least one angle therebetween; the interface layer is made from an insulator and is of thickness smaller than 10 nm in order to form a tunnel junction between the first and second semiconductors.

Description

 Multilayer photoreceptor device with different mesh parameters

The present invention relates to the field of photoreceptor devices, in particular for photovoltaic applications, and the thin-film manufacturing methods of such devices.

The term "photoreceptor device" is understood here to mean any electronic device capable of converting a light reception, either into electrical energy such as photovoltaic devices, or into an electrical signal, such as photoresistances.

As a non-limiting example, at least two materials may be involved in the manufacture of such a device. This is for example:

a substrate of a first material, based on silicon (Si hereinafter), and

a thin layer based on gallium arsenide (GaAs hereinafter), or a ternary alloy comprising aluminum in addition to this binary material (AlGaAs), deposited on the silicon substrate.

The use of these two types of materials, one deposited on the other, may have an advantage in the photovoltaic field, particularly in the design of cells called "tandem", because of their bandgap widths (or " gap "hereafter), offering a yield close to the theoretical maximum expected in terms of photovoltaic conversion.

However, a difficulty of depositing such a material on the other, consists in that their respective crystallographic structures have different mesh parameters (different interatomic distances of the material Si, to the other GaAs).

With reference to FIG. 1, it actually appears that when the mesh parameters are different (respectively a for Si and b for GaAs), constraints and then dislocations (beyond a critical height of deposited material) can appear because of the interatomic misalignment between the two materials. This results in electrically active defects that can degrade the performance of the device.

On the other hand, it is interesting that the surface of the thin layer (intended to receive the light) is textured to trap the light, and hence to increase the photon-material interaction surfaces of the photoreceptor device. Currently, texturing the surface of a thin layer after its growth is delicate and time consuming to achieve performance remaining suboptimal. The present invention improves this situation.

It proposes for this purpose a photoreceptor device, comprising at least:

 a first crystalline semiconductor material comprising a first mesh parameter, and

a second semiconductor crystalline material deposited on the first material and comprising a second mesh parameter, different from the first mesh parameter.

 In particular :

 the device comprises an interface layer between the first and the second material, made of an amorphous material and structured to include regularly spaced openings in the plane of the layer,

the second material comprises protuberances emerging from the openings of the interface layer and forming disjoint crystal grains, each grain having a plurality of facets forming at least one angle between them.

With this arrangement, the openings formed in the amorphous layer can accompany the growth of the second material, initially forced and then relaxing without dislocation, to form crystalline grains having multiple facets to trap light effectively.

Thus, the method of the invention makes it possible to obtain a natural texturing of the thin layer of the second material during its growth, without requiring any additional step later.

In addition, the interface layer is made of an insulating material (for example an oxide, such as silica deposited on silicon as the first material). Nevertheless, the thickness of the interface layer is less than 10 nm (nanometers) to advantageously form a tunnel junction between the first and the second material. With such a small interface layer thickness, however, the formation of the aforementioned crystalline protuberances without dislocation was found.

It will thus be understood that the interface layer can play both the role of assisting the growth of the protuberances of the second material, but also tunneling junction between the first and the second material, which can then be used in a "Tandem" type photovoltaic cell with one of the first and second materials in the "top" cell and the other material in the "bottom" cell. An interface layer is known to assist the growth of such protuberances in the prior art as reflected in the documents Dl: US 2010/236617, D2: EP 2343731, D3: WO-2013/154485. However, in these documents, the interface layers are not as fine as that in the sense of the present invention, which further allows a tunnel junction between the two materials. For example, in document Dl: US 2010/236617, it is necessary to specifically proceed to the formation of this tunneling junction layer in several steps, including in particular a particularly heavy doping step (D1: [0042]). In the context of the present invention, these steps are no longer necessary, particularly advantageously. The openings of the interface layer may, for their part, have a width of, for example, between 10 and 100 nm, preferably of the order of 50 nm.

In one embodiment, the first crystalline material is preferably of [111] orientation, which makes it possible, as will be seen in more detail below, to avoid twin problems between regions of different crystalline orientations, when the second material is polar (such as gallium arsenide).

In one embodiment, the photoconductive device includes a tandem cell and the first material is used in a first "bottom" cell (bottom cell with respect to the incidence of light), while the second material is used in a first cell. second "top" cell (top cell).

The spaces between the crystalline grains obtained can then be filled by an insulating layer deposited on the second material (for example silica S102 as illustrated with reference to step S16 of FIG. 5).

This insulating layer and the grains may then be encapsulated in a conductive and transparent layer (for example of ΓΓΓΟ as shown in FIG. 5), deposited on the insulating layer (Si0 ₂ ).

The present invention also relates to a method for manufacturing a photoreceptor device of the above type, the method comprising in particular at least:

 a first step of forming the aforementioned interface layer, structured to present regularly spaced openings and opening onto the first material, and

a second step of depositing the second material on the first material at least at said openings, the interface layer being made of an insulating material and having a thickness of less than 10 nm (nanometers) in order to advantageously form a tunnel junction between the first and the second material. The method may further comprise an intermediate step, between said first and second stages, of depositing a seed of a third material in each of the openings, seed on which is deposited, during said second step, the second material. This seed may be of the same material as the second material, or not. The deposition steps are preferably carried out by epitaxy.

The method may comprise a prior step of arranging the regularly spaced openings in the interface layer, by applying a mask etched locally to form these openings. Such an embodiment will be described in detail with reference to FIG. 5, hereinafter.

In particular, this mask is partially etched to leave, at the openings, an interface layer thickness thinner than outside the openings (this thickness being 0.6 nm in an embodiment shown below). This thinner layer thickness makes it possible to avoid oxidation, in the open air, of the first underlying material. It is then removed before operating the second step or the intermediate step mentioned above.

Other advantages and characteristics of the invention will become apparent on reading the description of exemplary embodiments presented hereinafter and on examining the appended drawings, in which: FIG. 1 illustrates an example of growth-related dislocations. from one material to another, in disagreement with mesh,

 2 schematically shows the structure for depositing a thin layer 10 (formed of a multiplicity of protuberances), with mesh clash, on a substrate 11, and this via a regularly "perforated" interface layer 12,

 FIGS. 3a and 3b are transmission electron microscopy images of a protuberance of gallium arsenide, deposited on a silicon substrate oriented [001] through a silica interface layer, at an epitaxial deposition temperature (CBE for "Chemical Beam Epitaxy") of 575 ° C (Figure 3a) and 550 ° C (Figure 3b),

FIG. 4 is a microscopy image representing, on a scale, a protuberance, the interface layer, and the substrate, FIG. 5 illustrates the different steps of an exemplary method of manufacturing the aforementioned interface layer,

 FIG. 6 is a microscopy image showing several regularly spaced protuberances, obtained by the implementation of the method of FIG. 5, on a Si substrate of crystalline orientation [111].

With reference to FIG. 2, in the example described, gallium arsenide 10 is deposited by epitaxy on a silicon substrate 11 (or on a preparation layer, based on silicon). However, there is provided an interface layer 12 made of oxide (silica Si0 ₂ in the example described) between the substrate 11 and the deposited material 10. The thickness e of the interface layer is less than order of 2 nm (nanometers). This layer 12 of oxide is "perforated" in regular places to expose the substrate 11 to bare, in openings of diameter L of the order of 20 to 100 nm. The gallium arsenide 10 is deposited progressively on the silicon substrate 11 in the openings left by the interface layer 12. The deposited gallium arsenide is strongly constrained, but this stress gradually relaxes as the deposit and the gallium arsenide then forms 3D islands at the exit of the interface layer 12 (arrows of FIG. 2). Thus, by relaxing, the gallium arsenide forms a protuberance in the shape of a "mushroom" at each opening of the interface layer 12. Each of these protuberances 10 has facets forming angles between them, which depend on the epitaxial temperature (FIG. 3a and 3b), the crystalline orientation of the substrate, and possibly other parameters.

On the one hand, these protuberances grow without dislocations. On the other hand, all these facets effectively trap the light in a photoreceptor device comprising such an overall layer 10 (formed of the various protuberances) deposited in mesh disagreement on substrate 11. In addition, the diameter L of the openings is relatively small (less than 100 nm) compared to the dimensions of the protuberances (of the order of a few microns in width). Figure 4 illustrates these respective dimensions, to scale. Nevertheless, it has been observed that the carriers could transit by tunnel effect, without difficulty between the protuberance (GaAs) and the substrate (Si), because of the fineness of the interface layer (oxide) of a few nanometers.

Finally, in the case of gallium arsenide deposited on silicon for the manufacture of a photovoltaic cell, the respective gaps are such that records of photovoltaic efficiency can be achieved.

Nevertheless, in order not to have the protuberances touch each other and thus reduce the efficiency of the trapping of the light, the openings of the interface layer 12 must be arranged regularly in the plane of the layer 12 (in regular steps along the two axes x, y of the plane of the layer 12, the third axis z being perpendicular to the layer).

Reference is now made to FIG. 5 to describe a method, by way of example, of preparing the regular openings of such an interface layer 12. The first step S1 consists in preparing the surface of the Si substrate, by chemical cleaning . There is a thin layer of silica Si0 ₂ . Then, in step S2, silicon nitride SiN is deposited on the silica layer. In the next step S3, an HSQ-type resin (for "Hydrogen silsesquioxane") is used to re-wet the SiN surface.

The next step S4 consists in defining the mask by electronic lithography (definition of a chosen pattern, with regular steps in the two x, y directions of the plane of the HSQ mask). In the next step S5, the resin is "developed" (removed) to leave the SiN nitride on the surface, outside of the remaining HSQ polymerized regions. In the next step S6, the mask is transferred, with removal of the nitride, by RIE (for "reactive ion etching"). Then, a stack having more precisely the form illustrated in relation to the step S7 of FIG. 5, of localized SiN nitride and silica, on the Si substrate, after a post-etching cleaning, is obtained.

Then, in a first embodiment at high temperature (1050 ° C), step S8a can be carried out at a dry oxidation, increasing the thickness of the silica layer, followed at step S 10a, of deoxidation of the SiN nitride layer. In another embodiment at a lower temperature, step S8b can be carried out at a thick HSQ, followed by a conversion of the HSQ resin to silica at step S9b. Then, by etching in step S 10b, in this second embodiment, the remaining pads of nitride are released.

In steps SU and S 12 (in either of the two embodiments above), it is then possible to selectively etch the nitride, then to a chemical cleaning (Shiraki type for example) with passivation ( to HC1 for example), to finally obtain a silica layer less than or equal to 2 nm in thickness, on the Si substrate, and in particular, at future openings, a much thinner silica, of the order 0.6 nm (about two atomic planes of silica). This very fine layer of 0.6 nm of silica allows a release of the substrate thus prepared, while avoiding an uncontrolled oxidation of the silicon substrate.

In step S 13, the substrate bearing the silica layer may be placed in an epitaxial structure, in which the 0.6 nm of silica is first removed to form the openings, for example by application of thermal flashes (at about 1000 ° C) or previously by dipping in a bath of hydrofluoric acid (HF). In step S14, in the openings thus liberated, crystals GR of crystals are preferably initially deposited for nucleation. These germs can have dimensions of the order of a few tens of nanometers. It may be in an embodiment of gallium arsenide, already (at an epitaxial temperature of 430 ° C). Nevertheless, in one variant, it may be another nucleating material, for example germanium. Typically, germanium (elemental Ge) has good properties to occupy the pendant bonds of silicon and concretely cover the entire free surface of the silicon substrate, and at an epitaxial temperature of the order of 600 ° C. Thus, with the aid of such seeds, the crystal growth of the grains (protuberances 10) can be finely controlled, especially when the seeds protrude from the openings, thus avoiding the formation of defects. After the nucleation step S14, step S15 of growth by epitaxy of the protrusions forming the crystals 10 (GaAs in the example described) can then be carried out at a temperature of between 500 ° C. and 600 ° C., and more preferably between 550 and 600 ° C.

Depending on the epitaxial temperature for example (or depending on the V / III element ratio for GaAs), desired patterns of facets can be obtained. However, it has been observed that certain protrusion patterns 10, and in particular that illustrated in FIG. 3a and obtained at a temperature of 575 ° C., could have different crystallographic orientations in the sense of the same crystal grain when the silicon substrate had a classical crystalline orientation [100]. In the case of regions of different crystalline orientations meeting in an atomic plane, a "twin" is created in this plane when the material is polar, such as gallium arsenide (atoms of arsenic As in front of atoms). arsenic (instead of gallium Ga), and gallium Ga atoms in front of gallium atoms (instead of arsenic As)). Such twins are likely to deteriorate the mechanical and / or electronic properties of the material.

To overcome this difficulty, it is proposed in one embodiment to deposit the protuberances 10 on a substrate orientation [111]. The obtained crystal grains 10, as shown in Figure 6, advantageously have no twin in this embodiment. They are of cubic overall shape, still different from those observed in FIGS. 3 a and 3b.

It should be further noted that for a polar material such as gallium arsenide, if the grains were to grow further and touch to form a single GaAs global layer, antiphase domains, or other domains could be created. defects that may render the material electrically defective at "grain boundaries".

Once the grains have been obtained, after step S15, a layer of silica may be deposited on the grains 10 to fill the spaces between them, in a step S 16, then a transparent conductive oxide layer (for example tin-doped indium oxide (ΓΓΟ) to form a collecting layer forming a contact of the photoreceptor device to be manufactured (after the eventual deposition of a passivation layer under the conductive transparent layer ΓΓΌ). These other steps to fully fabricate the photoreceptor device, such as a tandem Si-GaAs photovoltaic cell, are not detailed here, facet grain formation being the particular goal sought in the present invention.

Of course, the present invention is not limited to the embodiments described above as examples; it extends to other variants.

Thus, the method of forming the openings in the silica layer, described above with reference to FIG. 5, can be different and admits numerous variants (for example an HSQ resin deposit directly forming the definitive patterns of the SiO layer ₂ ). In another example, if the constraint in terms of even spacing of the openings is relatively small, it may be initially provided a single layer of silica, then a silane etch epitaxial attack, this attack being light to produce openings sufficiently spaced between them to avoid a risk of contact of the grains 10 between them then. Moreover, in general, the materials presented by way of example above, are capable of variations. It may be for example deposition of germanium on silicon (in disagreement of mesh), or InP on GaAs, or others. Similarly, the interface layer (of silica above) may be formed in another oxide (titanium or other). Deposition temperatures, crystalline substrate orientations, etc., are susceptible to variations depending on shape, size, orientation, etc., desired for grains 10.

Claims

1. Photoreceptor device, comprising at least:  a first semiconductor crystalline material comprising a first mesh parameter and a second semiconductor crystalline material deposited on the first material and comprising a second mesh parameter different from the first mesh parameter, characterized in that what: the device comprises an interface layer between the first and the second material, made of an amorphous material and structured to include regularly spaced openings in the plane of the layer, the second material comprises protuberances emerging from the openings of the interface layer and forming disjoint crystal grains, each grain having a plurality of facets forming at least one angle between them, and in that the interface layer is made of an insulating material and less than 10 nm thick, to form a tunnel junction between the first and the second material. 2. Device according to claim 1, characterized in that the openings of the interface layer are of width between 10 and 100 nm, preferably of the order of 50 nm. 3. Device according to one of the preceding claims, characterized in that the first crystalline material is orientation [111]. 4. Device according to one of the preceding claims, characterized in that the second material is polar. 5. Device according to one of the preceding claims, characterized in that the second material is gallium arsenide. 6. Device according to one of the preceding claims, characterized in that the first material is silicon. 7. Device according to one of the preceding claims, characterized in that it comprises a tandem cell and in that the first material is used in a first bottom cell and the second material is used in a second top cell. 8. Device according to one of the preceding claims, characterized in that spaces between grains are filled by an insulating layer (S1O ₂ ) deposited on the second material. 9. Device according to claim 8, characterized in that the insulating layer and the grains are encapsulated in a conductive layer (ΠΌ), deposited on the insulating layer. 10. A method of manufacturing a device according to one of the preceding claims, characterized in that it comprises at least:  a first step of forming said interface layer, structured to present regularly spaced openings and opening onto the first material, and  a second step of depositing the second material on the first material at least at said openings, the interface layer being made of an insulating material and having a thickness of less than 10 nm, to form a tunnel junction between the first and the second material. 11. The method of claim 10, characterized in that it further comprises an intermediate step, between said first and second stages, depositing a seed of a third material in each of the openings, seed on which is deposited, during said second step, the second material. 12. Method according to one of claims 10 and 11, characterized in that said deposition steps are implemented by epitaxy. 13. Method according to one of claims 10 to 12, characterized in that it comprises a prior step of arranging regularly spaced openings in the interface layer, by applying a mask etched locally to form said openings. The method according to claim 13, characterized in that said mask is partially etched to leave, at the openings, a thinner interface layer thickness than outside the apertures, said thinner layer thickness being removed before to perform the second step or said intermediate step.