EP3143648A1

EP3143648A1 - Method of forming a light-emitting device

Info

Publication number: EP3143648A1
Application number: EP15792197.4A
Authority: EP
Inventors: Zhengang JU; Wei Liu; Xueliang ZHANG; Swee Tiam TAN; Yun JI; Zi-hui ZHANG; Hilmi Volkan Demir
Original assignee: Nanyang Technological University
Current assignee: Nanyang Technological University
Priority date: 2014-05-14
Filing date: 2015-05-07
Publication date: 2017-03-22
Also published as: CN106463596A; EP3143648A4; WO2015174924A1; CN106463596B; TW201547053A

Abstract

Various embodiments provide a method of forming a light-emitting device. The method may include providing a multi-layer structure, wherein the multi-layer structure includes a substrate, a first semiconductor layer of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type in sequence, and includes at least one metal contact formed on at least one of the first semiconductor layer and the second semiconductor layer. The method further includes forming at least one trench over the at least one metal contact, and forming at least one metal support in the at least one trenches.

Description

METHOD OF FORMING A LIGHT-EMITTING DEVICE

Cross-reference to Related Applications

[0001] The present application claims the benefit of the United States provisional patent application No. 61/996,662 filed on 14 May 2014, the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Embodiments relate generally to light-emitting devices and methods of forming the same.

Background

[0003] Light-emitting diodes (LEDs), for example, GaN (gallium nitride) based LEDs are deemed the choice of light source for the next generation solid state lighting and the research and development in this area have made tremendous progress in the past few decades. High brightness GaN LEDs have been applied in various applications, such as backlight of LCDs, traffic signals, and full color displays.

[0004] Nowadays, GaN LEDs start to enter the general lighting market. In order to accelerate the penetration into the general lighting market, the performance of GaN LEDs needs to be further improved. For instance, the power conversion efficiency of GaN LEDs at high power operation must be much superior, for example, higher than 50%, in order for them to replace current fluorescent lamps (with power conversion efficiency of about 20%) with the benefits of better consumer experience and cost effectiveness.

[0005] There is a technological limitation to further improve the efficiency with current sapphire substrate based LEDs. Due to the electrical insulating nature and poor thermal conductivity (W/m^»K), sapphire based LEDs are usually suffered from poor light extraction, poor thermal dissipation, high junction temperature (>100°C) and large efficiency droop (>40%) at high power operation. These drawbacks set serious bottlenecks for further improvement of the LED efficiency at high power operation conditions.

[0006] Inverted LED concepts have thus been proposed to address the issues. Inverted LEDs are architectures on the metal support with light extracting from the opposite side of the electrodes, representing the state of the art of the modern LEDs technologies have a lot of unparalleled merits, such as excellent heat conduction and light extraction, compared with conventional LEDs of lateral architectures. These promising LEDs have extremely high efficiency and long life time even being operated under high current density. The principle of the inverted LED is to remove the sapphire substrate and attach the LED to a substitute substrate with good electrical and thermal conductivities. The substitute substrate will serve both as an electrode to conduct current and an effective heat dissipation path. After sapphire removal, the exposed unintentional doped GaN (u-GaN) surface or n-type doped GaN (n-GaN) surface can be roughened or patterned to enhance the light extraction efficiency.

[0007] However, this technology is not simply straightforward to be realized and the key point lies in the process of the sapphire removal. A strong and conductive support layer should be realized first before the sapphire removal in order to sustain the free standing LED layer and prevent any damage during and after the sapphire removal. The support layer may be formed by a wafer bonding process, in which the Au soldering process called thermosonic flip bonding process is applied.

[0008] Fig. 1 illustrating a method to produce the LED 100 with inverted configuration. LED dies 110 are first fabricated with similar procedure of the lateral chips, e.g. including mesa etching, metal pad deposition, mirror contact deposition, die dicing, etc. The LED die 110 includes an n-GaN layer, a MQW (multi-quantum wells) layer, and a p-GaN layer formed in sequence on a sapphire substrate, and n-pad and p-pad (including a transparent ohmic contact and a reflective mirror) formed on the n-GaN layer and the p-GaN layer, respectively. The LED die 110 deposited with a S1O2 passivation layer is reversed, and the p-pad and the n-pad are soldered or bonded onto a submount 120 (such as a copper or silicon wafer) via solder bumps 122 (e.g. Au bumps) and metal contacts 124 using thermosonic flip bonding process. After the LED die 110 is bonded to the submount 120, the sapphire substrate, which may be a patterned substrate, is removed and roughened. An unintentional doped layer between the substrate and the the n-GaN layer or the n-GaN layer may also be exposed and roughened to enhance the light extraction efficiency. The p-pad and n-pad are formed in the same side, and therefore the light will not be blocked by any pads and wires, as shown by the light emitting paths indicated in Fig. 1.

[0009] However, the Au soldering process provides a small area of contact for heat dissipation, since the heat conduction route of the device to the submount is through one or several soldering bumps or Au studs (the diameter of an Au stud is about 50-200 μιη), which is much smaller compared to the whole device area. Moreover, the Au soldering and the submount fabrication significantly increase the overall cost of the LEDs. On the contrary, metal plating is a cheap way to achieve adhesive support template for the inverted LEDs. However, the electrodes of the inverted LED chips are standing on the same side, and they have to be isolated for the final chip. Moreover, for the metal plating process all the parts which need to be plated have to be conductive. This requirement hinders the application of the metal plating technique in the inverted LED fabrication process.

Summary

[0010] Various embodiments provide a method of forming a light-emitting device. The method may include providing a multi-layer structure, wherein the multilayer structure includes a substrate, a first semiconductor layer of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type in sequence, and includes at least one metal contact formed on at least one of the first semiconductor layer and the second semiconductor layer. The method further includes forming at least one trench over the at least one metal contact, and forming at least one metal support in the at least one trenches.

Brief Description of the Drawings

[0011] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

Fig. 1 illustrates a method to produce an LED with inverted configuration.

Fig. 2 shows a flowchart illustrating a method of forming a light-emitting device according to various embodiments.

Fig. 3 shows a schematic diagram illustrating the top view and the cross section view of a layer structure according to various embodiments.

Fig. 4 shows a schematic diagram illustrating the top view and the cross section view of the profile of the layer structure after mesa etching for inverted process according to various embodiments.

Fig. 5 shows a schematic diagram illustrating the top view and the cross section view of the profile of the layer structure after deep etching.

Fig. 6 shows a schematic diagram illustrating the top view and the cross section view of the profile of a multi-layer structure with metal contacts formed according to various embodiments.

Fig. 7 shows a schematic diagram illustrating the top view and the cross section view of the multi-layer structure with a first passivation structure deposited according to various embodiments.

Fig. 8 shows a schematic diagram illustrating the top view and the cross section view of the multi-layer structure with a seed layer deposited according to various embodiments.

Fig. 9 shows a schematic diagram illustrating the top view and the cross section view of the multi-layer structure with a second passivation structure formed according to various embodiments.

Fig. 10 shows a schematic diagram illustrating the top view and the cross section view of the multi-layer structure with at least one metal support formed according to various embodiments.

Fig. 11 shows a schematic diagram illustrating the top view and the cross section view of the removal process of sapphire substrate from the LED wafer according to various embodiments. Fig. 12 shows a schematic diagram illustrating the LED layer structure with the network islands as the support after the removal of the substrate.

Fig. 13 shows a schematic diagram illustrating a roughing process according to various embodiments.

Fig. 14 shows a schematic diagram illustrating separation of LED dies according to various embodiments.

Fig. 15 shows a schematic diagram illustrating the bottom view of the inverted dies of Fig. 14 with copper support attached on the blue tape according to various embodiments.

Fig. 16 shows a schematic diagram illustrating a light-emitting device according to various embodiments.

Detailed Description

[0012] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0013] Various embodiments provide a method of forming a light-emitting device, e.g., an inverted high power LED using the network metal plating technique. Compared to the conventional technology, various embodiments form metal supports (also referred to as network metal islands) as the support for the subsequent fabrication processes. When applying this method to the inverted fabrication, with the help of the patterning technique and network metal islands, p- and n- electrode supports may be plated at the same time. Much larger contact area of the metal supports with the metal contacts will allow much better heat dissipation than the conventional inverted technologies. Accordingly, various embodiments provide a method which is more cost effective and has great potential to improve the production yield and efficiency.

[0014] It should be understood that the terms "on", "over", "lateral", "top", "bottom" "under", etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of any device or structures or any part of any device or structure.

[0015] Fig. 2 shows a flowchart 200 illustrating a method of forming a light- emitting device according to various embodiments.

[0016] At 202, a multi-layer structure is provided. The multi-layer structure includes a substrate, a first semiconductor layer of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type in sequence, and includes at least one metal contact formed on at least one of the first semiconductor layer and the second semiconductor layer.

[0017] At 204, at least one trench is formed over the at least one metal contact.

[0018] At 206, at least one metal support is formed in the at least one trench.

[0019] According to various embodiments, the multilayer structure is an LED (light-emitting diode) structure. The first and the second semiconductor layers and the active layer along with at least one metal contact form an LED structure.

[0020] According to various embodiments, an area of the metal support is substantially close to an area of the metal contact under the metal support. The area of the metal support may refer to the area of the bottom surface of the metal support directly or indirectly contacting with the metal contact. The area of the metal contact may refer to the area of the top surface of the metal contact directly or indirectly contacting with the metal support.

[0021] In various embodiments, the at least one trench is formed, including forming a passivation structure over the multi-layer structure. The passivation structure includes passivation portions defining the at least one trench and/or connecting adjacent trenches. In exemplary embodiments, two adjacent passivation portions may define a trench inbetween. In exemplary embodiments, two adjacent trenches may be connected or isolated by a passivation portion inbetween. [0022] In various embodiments, the method may further include dicing or etching through one or more of the passivation portions to form at least one light-emitting device die.

[0023] In various embodiments, the passivation portions and the at least one metal support are coplanar. By way of illustration, the coplanar passivation portions and the at least one metal support form and serve as a substrate support when the multi-layer structure is reversed to have the substrate on the top.

[0024] In various embodiments, each of the passivation portions may have a width in the range of 20μιη to 2mm.

[0025] In various embodiments, forming the passivation structure may include depositing a photoresist layer on the multi-layer structure; and exposing and developing the photoresist layer such that portions of the photoresist layer on the at least one metal contact are removed to form the at least one trench.

[0026] In various embodiments, the photoresist layer may be deposited with a thickness in the range of ΙΟμιη to 500μιη.

[0027] In various embodiments, after forming the at least one metal support, the passivation structure may be removed, and insulating material may be deposited into the region of the removed passivation structure.

[0028] In various embodiments, the at least one trench is formed with a depth or a thickness in the range of ΙΟμιη to 500μιη.

[0029] In various embodiments, the trench formed over the metal contact on the first semiconductor layer has a larger depth than the trench formed over the metal contact on the second semiconductor layer, such that the metal support formed over the metal contact on the first semiconductor layer has a larger thickness than the metal support formed over the metal contact on the second semiconductor layer.

[0030] In various embodiments, the at least one metal support is formed with a thickness much larger than the thickness of the at least one metal contact, such that the sufficiently thick metal support may serve as a metal substrate support for the LED structure. In various embodiments, the at least one metal support is formed with a thickness in the range of ΙΟμιη to 500μιη. [0031] In various embodiments, the at least one metal support includes copper or silver.

[0032] In various embodiments, the at least one metal support may be formed using one of electroplating, electron beam evaporation, thermal evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputter deposition.

[0033] In various embodiments, the method may further include forming a seed layer on the at least one metal contact before forming the trench.

[0034] In various embodiments, the seed layer is formed to enhance the adhesion strength for the subsequent metal support deposition. The seed layer may include a material selected from Cu (copper), Ni (nickel), W (tungsten), Au (gold), TaN (tantalum nitride), Ti (titanium), Pt (platinum), TiN (titanium nitride), Sn (tin) and any other suitable metals. The thickness of the seed layer 324 may be in the range of 10 nm to 500 nm.

[0035] The seed layer may be deposited using electron beam deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), ion beam deposition, electro-chemical deposition or any other suitable deposition methods.

[0036] In various embodiments, before forming the trench, the method may further include forming a further passivation structure over the multi-layer structure such that the at least one metal contact is substantially exposed; and forming the seed layer on the exposed metal contact.

[0037] In various embodiments, forming the further passivation structure may include depositing a passivation layer on the multi-layer structure, and etching the passivation layer to substantially expose the at least one metal contacts. For example, the entire top surface of the at least one metal contacts may be exposed.

[0038] In various embodiments, the at least one metal contact may include a light reflecting layer. The light reflecting layer, also referred to as a mirror layer, has a high reflectance of 90% and above in the visible spectrum. The mirror layer may include Al (aluminum), Ag (silver), Ti (titanium), Pt (platinum), Cr(chromium), Pd (palladium) or other metals with high reflectance. [0039] In various embodiments, the at least one metal contact on the first semiconductor layer may include one or more of surface layouts comprising dots, cross lines, or inter-digit fingers.

[0040] In various embodiments, the thickness of the at least one metal contact may be in the range of 3nm to 2000nm.

[0041] In various embodiments, the at least one metal contact may be formed using one of electron beam deposition, sputtering, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, ion beam deposition, electro-chemical deposition, or any other suitable deposition methods.

[0042] In various embodiments, the method may further include etching the second semiconductor layer and the active layer such that at least one first portion of the first semiconductor layer is exposed and at least one second portion of the first semiconductor layer remains covered by the active layer and the second semiconductor layer.

[0043] In various embodiments, the at least one metal contact is formed on the at least one first portion of the first semiconductor layer. The at least one metal contact on the first portion of the first semiconductor layer may be referred to as the metal contact of the first conductivity type. The metal contact of the first conductivity type may include or may be made of Ti, Al, Pt, Pd, Cr, Au, ITO (indium tin oxide) or any other suitable metals, or conductive metal oxides.

[0044] In various embodiments, the at least one metal contact is formed on the second semiconductor layer. The metal contact formed on the second semiconductor layer may be referred to as the metal contact of the second conductivity type. The metal contact of the second conductivity type may include or may be made of at least one of Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo (molybdenum), Ta (tantalum), TaN, a refractory metal, a metal alloy, ITO (indium tin oxide) and any other suitable metals, or a composite of any of these materials.

[0045] In various embodiments, at least one trench is formed over the at least one metal contact of the first conductivity type, and at least one trench is formed over the at least one metal contact of the second conductivity type. The trench over the metal contact of the first conductivity type and the trench over the metal contact of the second conductivity type may be formed simultaneously or separately. The trench over the metal contact of the first conductivity type may have a larger depth than the trench over the metal contact of the second conductivity type.

[0046] In various embodiments, at least one metal support of the first conductivity type is formed in the at least one trench over the metal contact of the first conductivity type, and at least one metal support of the second conductivity type is formed in the at least one trench over the metal contact of the second conductivity type. The metal support of the first conductivity type and the metal support of the second conductivity type may be formed simultaneously or separately. The metal support of the first conductivity type may have a larger thickness than the metal support of the second conductivity type.

[0047] In various embodiments, after etching the second semiconductor layer and the active layer to expose the at least one first portion of the first semiconductor layer, at least one isolation trench extending through the at least one first portion of the first semiconductor layer may be formed.

[0048] In various embodiments, the isolation trench may be formed by etching the first portion of the first semiconductor layer until the substrate is exposed.

[0049] In various embodiments, the isolation trench may be filled with a passivation layer.

[0050] In various embodiments, the method may further include dicing or etching the multi-layer structure along the at least one isolation trench to form at least one light-emitting device die.

[0051] In various embodiments, the method may further include removing the substrate using one of laser liftoff, lapping or chemical etching.

[0052] In various embodiments, the multi-layer structure may be formed by forming the first semiconductor layer of the first conductivity type on the substrate, forming the active layer on the first semiconductor layer; and forming the second semiconductor layer of the second conductivity type on the active layer.

[0053] In various embodiments, one or more of the first semiconductor layer, the active layer and the second semiconductor layer may be grown on the substrate using metal organic chemical vapor deposition or molecular beam epitaxy. [0054] In various embodiments, the substrate may be selected from a group consisting of sapphire (AI2O3), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (A1N), and gallium arsenide (GaAs). In various embodiments, the substrate may be a c-plane substrate, also referred as (0001) substrate. In various embodiments, the substrate may be coated with a nucleation layer, for example, a GaN or AlGaN (aluminum gallium nitride) nucleation layer, to relieve the lattice mismatch between the substrate and subsequently deposited nitride layers.

[0055] In various embodiments, an unintentionally doped layer is grown on the substrate, and is sandwiched between the substrate and the first semiconductor layer. The substrate may be removed to expose the unintentionally doped layer. In various embodiments, the exposed unintentionally doped layer may be roughened.

[0056] In various embodiments, the unintentionally doped layer may include an unintentionally doped gallium nitride (u-GaN) layer, for relieving the lattice mismatch between the substrate and subsequently deposited nitride layers.

[0057] In various embodiments, the first semiconductor layer of the first conductivity type may include an n-type doped gallium nitride (n-GaN) layer, or may include other suitable material, such as an n-type doped aluminum gallium nitride (n- AlGaN) layer, an n-type doped indium gallium nitride (n-InGaN) layer, or an n-type doped aluminum gallium indium nitride (n-AlGalnN) layer. The n-type dopants may be Si (silicon) or Ge (germanium).

[0058] In various embodiments, the second semiconductor layer of the second conductivity type may include a p-type doped gallium nitride (p-GaN) layer, or may include other suitable material, such as a p-type doped aluminum gallium nitride (p- AlGaN) layer, a p-type doped indium gallium nitride (p-InGaN) layer, or a p-type doped aluminum gallium indium nitride (p-AlGalnN) layer. The p-type dopants may be Mg (magnesium), Be (beryllium) or Zn (Zinc).

[0059] In various embodiments, the active layer may include one or more quantum well layers sandwiched by quantum barrier layers. In various embodiments, the active layer may include a single quantum well layer sandwiched by quantum barrier layers, referred to as a single quantum well (SQW) structure, or may include multiple quantum well layers each of which being sandwiched by quantum barrier layers, referred to as a multiple quantum well (MQW) structure. The quantum well layer and the quantum barrier layer may be formed in alternate order.

[0060] In various embodiments, the one or more quantum well layers may include indium gallium nitride. The indium composition in the quantum well layers may be varied depending on the desired emission wavelength. The quantum well layers may be unintentionally doped.

[0061] In various embodiments, the quantum barrier layers may include gallium nitride. The quantum barrier layers may be unintentionally doped or may be doped with n-type dopants, such as Si or Ge.

[0062] According to various embodiments, n- and p- metal supports may be plated at one time, and n- and p- metal contacts have fully contact with the metal supports. Unlike most of the plating process in which only one pad was plated at one time, with the help of the network pattern provided by the passivation structure, p- and n- metal supports may be connected during the plating process, so that they can be plated at one time. This makes the LED layer structure in full contact with the metal support, and therefore provides better heat dissipation.

[0063] Unlike the conventional technology in which metal substrate deposition is done on whole wafer level or completely separated die level, the metal support deposition/plating of various embodiments may be conducted at die level with passivation portions of the passivation structure arranged between die and die for connecting the dies together.

[0064] Unlike the conventional technology in which the separated dies are usually obtained by dicing the whole copper wafer, only the passivation portions of the passivation structure need to be diced or etched in the method of various embodiments, thereby achieving a simple die separation process with low workload and high throughput.

[0065] Unlike the conventional technology in which the separated dies are assembled through a temporary substrate, the passivation portions of the passivation structure provided in various embodiments may be used as the support and hold all dies together, which provides a self-support assembling for the fabrication process. Accordingly, the method of various embodiments simplifies the process, reduces the cost and improves the yield.

[0066] Various embodiments of the process for forming the light-emitting device are described with regard to Figs. 3 to 14 below.

[0067] Fig. 3 shows a schematic diagram 300 illustrating the top view and the cross section view of a layer structure according to various embodiments.

[0068] Various embodiments described above are valid for the embodiments described with regard to Figs. 3 to 16 below, and vice versa.

[0069] As shown in Fig. 3, a substrate 302, a first semiconductor layer 304 of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type 306 formed in sequence is shown. The active layer and the second semiconductor layer is shown and labeled as one layer 306 for illustrating purposes, but it is understood that the active layer is formed and sandwiched between the first semiconductor layer 304 and the second semiconductor layer 306. The layer sequence in Fig. 3 may also be referred to as an LED epilayer structure, or an LED wafer.

[0070] In various embodiments, the LED epilayer structure may be formed by sequentially growing the first semiconductor layer 304, the active layer and the second semiconductor layer 306 on the substrate 302 using metal organic chemical vapor deposition or molecular beam epitaxy.

[0071] In the exemplary embodiments described below, the substrate 302 may be a sapphire substrate. The first semiconductor layer 304 may be a n-type doped layer, e.g. a n-GaN layer. The active layer 306 may be an InGaN/GaN active layer. The second semiconductor layer 306 may be a p-type doped layer, e.g. a p-GaN layer. It is understood that various other suitable materials may be used for the respective layers.

[0072] Fig. 4 shows a schematic diagram 400 illustrating the top view and the cross section view of the profile of the layer structure after mesa etching for inverted process according to various embodiments.

[0073] As shown in Fig. 4, for the inverted process, mesa etching may be conducted until the n-GaN layer 304 is exposed. [0074] In various embodiments, the p-GaN layer and the active layer 306 may be etched such that at least one first portion 308 of the n-GaN layer 304 is exposed and at least one second portion 310 of the n-GaN layer 304 remains covered by the active layer and the p-GaN layer 306. The mesa etching may form at least one mesa structure, which may include the first portion 308 of the n-GaN layer 304 and the adjacent p-GaN layer and active layer 306.

[0075] Fig. 5 shows a schematic diagram 500 illustrating the top view and the cross section view of the profile of the layer structure after deep etching.

[0076] As shown in Fig. 5, deep etching may be performed until the sapphire substrate 302 is exposed. In various embodiments, the at least one first portion 308 of the n-GaN layer 304 may be etched until the substrate 302 is exposed to form at least one isolation trench 312. In various embodiments, the isolation trench 312 extends through the at least one first portion 308 of the n-GaN layer 304, and is formed for die isolation and for die separation in subsequent processes.

[0077] Fig. 6 shows a schematic diagram 600 illustrating the top view and the cross section view of the profile of a multi-layer structure with p-metal contact and n- metal contact formed according to various embodiments.

[0078] As shown in Fig. 6, at least one p-metal contact 314 may be deposited onto the p-GaN layer 306. At least one n-metal contact 316 may be deposited onto the n- GaN layer 304, e.g. on the first portion 308 of the n-GaN layer 304. Accordingly, the p-metal contact 314 and the n-metal contact 316 are formed at the same side relative to the n-GaN layer 304 and the substrate 302.

[0079] The p-metal contact 314 may include an ohmic contact layer and a light reflecting layer (also referred to as a mirror layer), and may be referred to as a p-metal mirror contact layer 314. The p-metal mirror contact layer may have a high reflectance of 90% or above. The p-metal mirror contact layer 314 may include at least one of Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo, Ta, TaN, a refractory metal, a metal alloy, ITO (indium tin oxide) and any other suitable metals, or composite of these materials. The thickness of the p-metal contact layer 314 may be in the range of 3nm to 2000nm. The deposition of the p-metal contact layer 314 may be performed using electron beam deposition, sputtering, physical vapour deposition, chemical vapour deposition, plasma-enhanced CVD, ion beam deposition, electro-chemical deposition or any other suitable deposition methods.

[0080] The n-metal contact 316 may include or may be made of Ti, Al, Pt, Pd, Cr, Ti, Au, ITO or any other suitable metals, or conductive metal oxides. The n-metal contact 316 may also include a mirror layer, and may be referred to as an n-metal mirror contact layer 316. The n-metal mirror contact layer may have a high reflectance of 90% or above. The thickness of the n-metal contact 316 may be in the range of 3nm to 2000nm. The n-metal contact 316 may be deposited using electron beam deposition, sputtering, physical vapour deposition, chemical vapour deposition, plasma-enhanced CVD, ion beam deposition, electro-chemical deposition or any other suitable deposition methods.

[0081] The n-metal mirror contact layer 316 may be designed into various layouts, such as dots, cross lines, and inter-digit fingers, etc., or a combination thereof. The rule of thumb of the design is to best spread the current with minimum area, which leads to the largest area of the light emitting. In light of the same side configuration of the p-contact 314 and the n-contact 316, the n-metal mirror contact layer 316 is provided and formed to enhance the reflectance of the light reaching the n-contact area. Therefore, light blocking problem is suppressed compared with the conventional lateral chip design.

[0082] The structure including the substrate 302, the n-GaN layer 304, the active layer and the p-GaN layer 306, and the p-metal contacts 314 and n-metal contacts 316 may be referred to as the multi-layer structure 320 described in the embodiments above, or may be referred to as a LED structure 320.

[0083] In various embodiments, a short annealing around 5 minutes at about 300- 600°C in air or N2/O2 mixture may be performed to achieve better ohmic contact.

[0084] Fig. 7 shows a schematic diagram 700 illustrating the top view and the cross section view of the multi-layer structure with a first passivation structure deposited according to various embodiments.

[0085] As shown in Fig. 7, a first passivation structure 322 may be formed over the multi-layer structure 320. In various embodiments, the first passivation structure 322 is formed and patterned such that the at least one metal contact is substantially exposed. For example, the top surface of the p-metal contact 314 and/or the n-metal contact 316 may be substantially exposed and free of the first passivation structure. The exposed area of the p-metal contact 314 and/or the n-metal contact 316 may be substantially close to the area of the top surface of the p-metal contact 314 and/or the n-metal contact 316, respectively. This may allow the metal support subsequently formed over the metal contact 314, 316 to have a sufficiently large contact area with the metal contact.

[0086] In various embodiments, the first passivation structure 322 may be formed by depositing a passivation layer 322 on the multi-layer structure 320, and etching the passivation layer 322 to substantially expose the at least one metal contacts 314, 316.

[0087] In various embodiments, the passivation layer 322 may be formed to fill in the isolation trench 312.

[0088] In various embodiments, the passivation layer 322 may be deposited on the sidewalls of respective mesa structures, e.g., on the sidewalls of the isolation trench 312, the side walls of the metal contacts 314, 316, the side walls of the p-GaN layer and active layer 306, etc.

[0089] Fig. 8 shows a schematic diagram 800 illustrating the top view and the cross section view of the multi-layer structure with a seed layer deposited according to various embodiments.

[0090] As shown in Fig. 8, a seed layer 324 may be deposited on at least one of the metal contacts 314, 316, e.g., for enhancing the adhesion strength for the subsequent metal deposition. The seed layer 324 may include a material selected from Cu, Ni, W, Au, TaN, Ti, Pt, TiN, Sn and any other suitable metals. The thickness of the seed layer 324 may be in the range of 10 nm to 500 nm. The seed layer 324 may be deposited using electron beam deposition, sputtering, physical vapour deposition, chemical vapour deposition, plasma-enhanced CVD, ion beam deposition, electrochemical deposition, or any other suitable deposition methods.

[0091] In various embodiments, a thin photoresist may be employed to form a network island pattern for the seed layer deposition. Accordingly, the seed layer 324 with a pattern of network is formed on top of at least one metal contacts 314, 316 using photoresist patterning material. The pattern of the network may have a lot of varieties, like different number of the network connections between two islands (e.g. the seed layer portion deposited on the metal contacts 314, 316) and different width of the network connections (e.g. the passivation layer 322 inbetween the respective structures 304, 306, 314, 316).

[0092] Fig. 9 shows a schematic diagram 900 illustrating the top view and the cross section view of the multi-layer structure with a second passivation structure formed according to various embodiments.

[0093] As shown in Fig. 9, the second passivation structure 330 is formed over the multi-layer structure 320, e.g. on the first passivation structure 322 formed on the multi-layer structure 320. The second passivation structure 330 may include passivation portions 332 which define at least one trench 334 over the at least one metal contact 314, 316 and/or connects adjacent trenches, as shown in Fig. 9.

[0094] In various embodiments, the second passivation structure 330 may be formed by depositing a photoresist layer 336 on the multi-layer structure 320, and exposing and developing the photoresist layer 336 such that portions of the photoresist layer on the at least one metal contact 314, 316 and the seed layer 324 are removed to form the at least one trench 334. Illustratively, a thick patterning material layer 336, such as SU8 or 125nXT, may be spin-coated onto the surface of the first passivation structure 322 and the seed layer 324. The patterning material layer 336 may have a thickness in the range of ΙΟμιη to 500μιη. After exposure, the patterning material layer 336 is subjected to developments, which may be different according to the different baking processes. After the development, the patterning structure 330 is formed with the trenches 334 free of patterning material.

[0095] In various embodiments, the patterning material layer may include photoresist, oxides, nitrides, or other suitable dielectric materials.

[0096] The second passivation structure 330 is shown as a patterning structure on the surface of the first passivation structure 322. The thickness of the patterning material wall may be in the range of ΙΟμιη to 500μιη. The trench 334, also referred to as network island area which forms a network island when metal is subsequently plated in the trench, is exposed without patterning material. The size, e.g. the width, of the trench/network island area 334 may be in the range of ΙΟΟμιη to 2mm. The depth of the trench 334 or the thickness of the island area may be in the range of ΙΟμηι to 500μηι. The width of each of the passivation portions 332, also referred to as network connection portions, may be in the range from 20 μιη to 2mm. The thickness of the passivation portion/network connection 332 may be in the range of ΙΟμιη to

[0097] In various embodiments, the trench 334 formed over the n-metal contact 316 has a larger depth or thickness than the trench 334 formed over the p-metal contact 314, as shown in Fig. 9. Accordingly, metal support subsequently formed over the n-metal contact 316 has a larger thickness than metal support subsequently formed over the p-metal contact 314.

[0098] In various embodiments, the area of the trench 334 (e.g. the area of the bottom surface of the trench 334 contacting the seed layer 324 or the n-metal contact 316) formed over the n-metal contact 316 is substantially close to the area of the n- metal contact 316 (e.g. the area of the top surface of the n-metal contact 316 contacting the seed layer 324 or the trench 334). The area of the trench 334 (e.g. the area of the bottom surface of the trench 334 contacting the seed layer 324 or the p- metal contact 314) formed over the p-metal contact 314 is substantially close to the area of the p-metal contact 314 (e.g. the area of the top surface of the p-metal contact 314 contacting the seed layer 324 or the trench 334).

[0099] Fig. 10 shows a schematic diagram 1000 illustrating the top view and the cross section view of the multi-layer structure with at least one metal support formed according to various embodiments.

[00100] As shown in Fig. 10, after the formation of the second passivation structure 330 in Fig. 9 to form the trench/network island area 334, at least one metal support 344, 346 are formed in the at least trench 334.

[00101] Illustratively, the metal support 344, 346, also referred to as metal network islands, are plated to fill the trenches 334 defined by the second passivation pattern 330. The metal support 344 formed for the p-metal contact 314 may be referred to as p-metal support 344 or p-electrode 344. The metal support 346 formed for the n- metal contact 316 may be referred to as n-metal support 346 or n-electrode 346. The p-metal support 344 and the n-metal support 346 are connected and isolated by the passivation portion/network connection 332. [00102] In various embodiments, the metal support 344, 346 may be formed with a thickness in the range of ΙΟμιη to 500μιη. In various embodiments, the n-metal support 346 may have a larger thickness than the p-metal support 344. In various embodiments, the thickness of the metal supports 344, 346 is much larger than the thickness of the metal contacts 314, 316, so that the thick metal supports 344, 346 may serve as a metal substrate support for the LED structure.

[00103] In various embodiments, the area of p-metal support 344 (e.g. the area of the bottom surface of the p-metal support 344 contacting the seed layer 324 or the p- metal contact 314) may be substantially close to the area of the p-metal contact 314 (e.g. the area of the top surface of the p-metal contact 314 contacting the seed layer 324 or the p-metal support 344), and the area of n-metal support 346 (e.g. the area of the bottom surface of the n-metal support 346 contacting the seed layer 324 or the n- metal contact 316) may be substantially close to the area of the n-metal contact 316 (e.g. the area of the top surface of the n-metal contact 316 contacting the seed layer 324 or the n-metal support 346), so as to form sufficiently large contact area between the metal support 344, 346 and the metal contact 314, 316.

[00104] In various embodiments, the metal support/network islands 344, 346 may possess the properties of excellent thermal conductivity and excellent electrical conductivity. Copper, silver, or other suitable metals possessing these properties may be used as the material for the metal support/network islands 344, 346.

[00105] In exemplary embodiments, copper electroplating may be used to plate copper into the trench/network island area 334, wherein copper has superior electrical conductivity and thermal conductivity (401W/m^»K). Copper sulfate pentahydrate of 99% purity may be used as the electrolyte, and additives such as 320C from Enthone Chemistry may be used as the additive to enhance the plating quality of copper. The plating current density may be set to be in the range of 2A/dm² ~20A/dm². The corresponding plating rate may be in the range of 50μητ/η to 200μιη/η. The thickness of the copper layer 344, 346 may be in the range of ΙΟμιη to 500μιη. The metal support 344, 346 may also be deposited using other metal deposition methods, such as electron beam evaporation, thermal evaporation, PVD, CVD, or sputtering deposition.

[00106] In various embodiments, the metal support 344, 346 and the passivation portions 332 of the second passivation structure 330 may be coplanar, as shown in Fig. 10, so as to serve as a support or a metal substrate, e.g. when the multi-layer structure is inverted to face downwardly.

[00107] The metal support/network islands 344, 346 formed according to various embodiments may serve several purposes. In a first aspect, the metal support/network islands 344 and 346 may serve as the electrodes for the light-emitting device. In a second aspect, the metal support/network island 344, 346 may serve as the heat sink and final support. The p-metal support 344 may have a larger area than the n-metal support 346, and may be used to dissipate heat more efficiently. In a third aspect, the metal support/network islands 344, 346 and the trench/network connection 332 may serve as connection and support to hold all dies together for the subsequent processes.

[00108] According to various embodiments, the metal support 344, 346 may be formed directly on the metal contact 314, 316 to be in physical contact with the metal contact 314, 316, in the absence of formation of the seed layer 324.

[00109] In various embodiments, after the metal support deposition, the second passivation structure 330 may be kept as isolation material and additional support material. In various embodiments, the second passivation structure 330 may be removed using acetone as solvent, for example, if the photoresist material used for the second passivation structure 330 is not suitable for isolation and support. Insulating material, such as strong adhesive and isolating material, may be deposited into the region of the removed second passivation structure 330, so as to filled in the areas between metal supports 344, 346.

[00110] Fig. 11 shows a schematic diagram 1100 illustrating the top view and the cross section view of the removal process of sapphire substrate from the LED wafer according to various embodiments.

[00111] As shown in Fig. 11, the LED layer structure of Fig. 10 is inverted to make the substrate 302 face upwardly. The substrate 302 may be removed using laser lift off, lapping, or chemical etching method.

[00112] Fig. 12 shows a schematic diagram 1200 illustrating the LED layer structure with the network islands 344, 346 as the support after the removal of sapphire substrate 302. [00113] In various embodiments, buffer and coalescence layers, e.g., an unintentionally doped GaN (u-GaN) layer (not shown) may be deposited and sandwiched inbetween the substrate and the n-GaN layer 304. Accordingly, after removal of the substrate 302, the u-GaN layer may be exposed. The n-GaN layer 304 may not need to be exposed by etching, as the n-contact 316 may be formed at the other side of the n-GaN layer 304.

[00114] Fig. 13 shows a schematic diagram 1300 illustrating a roughing process according to various embodiments.

[00115] In order to improve the light extraction efficiency, the exposed u-GaN layer surface may be roughened through wet etching, or other patterning techniques such as photolithography, nano-imprinting and nano-sphere lithography.

[00116] In various embodiments, the n-GaN layer 302 may be exposed after substrate removal and the surface of the exposed n-GaN layer 302 may be roughened in a similar manner.

[00117] The exposed surface may be roughened with a pattern 350 including various shapes, such as cones, pyramids, pillars, and domes, and with the dimensions for pitch, diameter and height in the range of lOOnm ~ 5μιη.

[00118] Fig. 14 shows a schematic diagram 1400 illustrating separation of LED dies according to various embodiments.

[00119] After the roughening and/or patterning of the u-GaN layer surface, the LED dies with metal supports 344, 346 as the metal substrate may be attached or put on a blue tape 352, and may be separated by dicing machine or chemical etching as shown in Fig. 14.

[00120] In various embodiments, dicing or etching may be performed through one or more of the passivation portions/network connections 332 of the second passivation structure 330 to form one or more LED dies. In various embodiments, dicing or etching may be performed along the at least one isolation trench 312 to form one or more LED dies. [00121] In various embodiments, part of the first passivation structure 322 filled in the isolation trench 312 may be patterned and removed to expose the passivation portions/network connections 332 of the second passivation structure 330. The passivation portions/network connections 332 may be cut or etched to separate the LED dies.

[00122] Fig. 15 shows a schematic diagram 1500 illustrating the bottom view of the inverted dies of Fig. 14 with copper support attached on the blue tape according to various embodiments.

[00123] As shown in Fig. 15, a plurality of LED dies are attached on the blue tape 352, which may be separated into single chips after removal of the blue tape 352, as shown in Fig. 16.

[00124] A light-emitting device die or chip 1600 according to various embodiments is shown in Fig. 16. The light-emitting device 1600 includes a multilayer structure 1620, including a first semiconductor layer 304 of a first conductivity type (e.g. an n-type doped layer), an active layer and a second semiconductor layer of a second conductivity type (e.g. a p-type doped layer) 306 in sequence, and having at least one metal contact (e.g. p-metal contact 314 and n-metal contact 316) formed on at least one of the first semiconductor layer 304 and the second semiconductor layer 306. The light-emitting device 1600 further include at least one metal support (e.g. p- metal support 344 and n-metal support 346) formed in at least one trench over the at least one metal contact 314, 316.

[00125] A seed layer 324 may be optionally deposited between the metal contact 314, 316 and the metal support 344, 346.

[00126] The metal contact 314, 316 may be insulated and connected by a passivation layer 322. The metal support 344, 346 may be insulated and connected by a further passivation layer 336.

[00127] The area of the p-metal support 344 contacting the p-metal contact 314 or the optional seed layer 324 may be substantially close to the area of the p-metal contact 314 contacting the p-metal support 344 or the optional seed layer 324. The area of the n-metal support 346 contacting the n-metal contact 316 or the optional seed layer 324 may be substantially close to the area of the n-metal contact 316 contacting the n-metal support 346 or the optional seed layer 324.

[00128] The various embodiments described in Figs. 3 to 15 above illustrates more than one LED dies. It is understood that the method including the trench and the metal support formation according to various embodiments above may also be performed for a single die.

[00129] The method disclosed in various embodiments above may be applied in the fabrication of optoelectronic devices, such as high power LEDs, photodetectors, laser diodes and microelectronics such as bipolar transistors.

[00130] According to various embodiments above, a network plating technique is provided for the fabrication of inverted high power LEDs on metal substrate. Accordingly, p-electrodes and n-electrodes may be plated at the same time so that the contact area of the p-contact and n-contact of the chip with the metal support is almost the same to the chip size. The network metal plating with p- and n- metal supports connected during plating process and separated easily by scribing or etching the network connection part in the final chip fabrication process, increases the heat conduction area to almost the whole device size. This will allow much better heat dissipation than the conventional inverted technology. Furthermore, since the plated metal support may be used as the contact, support and submount at the same time, which can significantly reduce the cost.

[00131] Therefore, the method of various embodiments improves the heat dissipation efficiency, increase the yield and lower the cost significantly and is very promising for mass production of high power inverted LEDs.

[00132] According to various embodiments, the sapphire substrate is removed and the exposed GaN surface is roughened or patterned to enhance light extraction efficiency. A highly reflective mirror may be applied inbetween the metal contacts formed on the LED layer structure and the metal support substrate, which may also help to enhance the light extraction efficiency. For inverted LED process, both n- electrode and p-electrode may be formed on the same side relative to the substrate and the n-GaN layer. Accordingly, light will not be blocked by any pads and wires. The etching of u-GaN is not necessary for this process, and then much thicker GaN layer is favour of better light extraction. [00133] The sapphire substrate is poor in thermal conduction (thermal conductivity of about 41.9W/m^»K), and the LEDs suffer from serious efficiency droop due to the junction temperature increase caused by large heat resistance of sapphire substrate. According to various embodiments, by using metal support with high thermal conductivity such as copper metal support (thermal conductivity of about 401W/m^»K), the heat generated in LEDs can be effectively dissipated out and the high efficiency of the LEDs can be preserved. Compared with conventional inverted process, the area of the contact between p-GaN and the submount is much larger, which allows better heat dissipation.

[00134] In the conventional technology, the whole wafer-level metal substrate deposition and metal substrate dicing processes are necessary. Stress and bowing may be generated in LED wafers, which will cause cracks and damages in LED films after the sapphire substrate removal. This will cause instant or potential failure of LEDs and lower the yield and reliability of LEDs. Further, metal particles are easy to be generated during the metal substrate dicing process, which are serious contaminants for LED devices and can cause current leakage and short-circuit issue. These factors may lower the yield and cause reliability issues.

[00135] According to various embodiments, the metal network island deposition is conducted at die-level with network connection, which effectively suppresses the generation of stress and bow. For the separation of the dies the simple cutting process only cuts the network connection part, which will greatly reduce the metal particle contamination issues, thereby improving yield and reliability for the inverted processes.

[00136] According to various embodiments, network connected metal supports may serve as both the support and the p- and n- electrodes at the same time, which saves the cost of the additional temporary support wafer during the fabrication process and thus reduces the cost. For inverted process, both p- and n- electrode pads were plated as self-supported layer which avoids the soldering process and save the cost for the Au stud metal and the submount. In return, the cost of the fabrication may be reduced by 10-20% compared with the flip chip process. Therefore the method of various embodiments is cost effective and material/process efficient. [00137] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

Claims What is claimed is:

1. A method of forming a light-emitting device, the method comprising: providing a multi-layer structure, the multi-layer structure comprising a substrate, a first semiconductor layer of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type in sequence, and having at least one metal contact formed on at least one of the first semiconductor layer and the second semiconductor layer, forming at least one trench over the at least one metal contact; and forming at least one metal support in the at least one trench.

2. The method according to claim 1, wherein an area of the metal support is substantially close to an area of the metal contact under the metal support.

3. The method according to claim 1 or 2, wherein forming the at least one trench comprises: forming a passivation structure over the multi-layer structure, the passivation structure comprising passivation portions defining the at least one trench and/or connecting adjacent trenches.

4. The method according to claim 3, further comprising: dicing or etching through one or more of the passivation portions to form at least one light-emitting device die.

5. The method according to claim 3 or 4, wherein the passivation portions and the at least one metal support are coplanar.

6. The method according to any one of claims 3 to 5, wherein each of the passivation portions has a width in the range of 20μιη to 2mm.

7. The method according to any one of claims 3 to 6, wherein forming the passivation structure comprises: depositing a photoresist layer on the multi-layer structure; and exposing and developing the photoresist layer such that portions of the photoresist layer on the at least one metal contact are removed to form the at least one trench.

8. The method according to claim 7, wherein the photoresist layer is deposited with a thickness in the range of ΙΟμιη to 500μιη.

9. The method according to any one of claims 3 to 8, further comprising: after forming the at least one metal support, removing the passivation structure; and depositing insulating material into the region of the removed passivation structure.

10. The method according to any one of claims 1 to 9, wherein the at least one trench is formed with a depth in the range of ΙΟμιη to

11. The method according to any one of claims 1 to 10, wherein the trench formed over the metal contact on the first semiconductor layer has a larger depth than the trench formed over the metal contact on the second semiconductor layer, such that the metal support formed over the metal contact on the first semiconductor layer has a larger thickness than the metal support formed over the metal contact on the second semiconductor layer.

12. The method according to any one of claims 1 to 11, wherein the at least one metal support is formed with a thickness in the range of ΙΟμιη to 500μιη.

13. The method according to any one of claims 1 to 12, wherein the at least one metal support comprises copper or silver.

14. The method according to any one of claims 1 to 13, further comprising: forming the at least one metal support using one of electroplating, electron beam evaporation, thermal evaporation, physical vapor deposition, chemical vapor deposition, or sputter deposition.

15. The method according to any one of claims 1 to 14, further comprising: forming a seed layer on the at least one metal contact before forming the trench.

16. The method according to claim 15, further comprising: before forming the trench, forming a further passivation structure over the multi-layer structure such that the at least one metal contact is substantially exposed; and forming the seed layer on the exposed metal contact.

17. The method according to claim 16, wherein forming the further passivation structure comprises: depositing a passivation layer on the multi-layer structure, and etching the passivation layer to substantially expose the at least one metal contacts.

18. The method according to any one of claims 1 to 17, wherein the at least one metal contact comprise a light reflecting layer.

19. The method according to any one of claims 1 to 18, wherein the at least one metal contact on the first semiconductor layer comprises one or more of surface layouts comprising dots, cross lines, or inter- digit fingers.

20. The method according to any one of claims 1 to 19, further comprising: forming the at least one metal contact using one of electron beam deposition, sputtering, physical vapor deposition, chemical vapor deposition, plasma- enhanced chemical vapor deposition, ion beam deposition, or electro-chemical deposition.

21. The method according to any one of claims 1 to 20, further comprising: etching the second semiconductor layer and the active layer such that at least one first portion of the first semiconductor layer is exposed and at least one second portion of the first semiconductor layer remains covered by the active layer and the second semiconductor layer.

22. The method according to claim 21, further comprising: forming the at least one metal contact on the at least one first portion of the first semiconductor layer.

23. The method according to claim 21 or 22, further comprising: forming the at least one metal contact on the second semiconductor layer.

24. The method according to any one of claims 21 to 23, further comprising: after etching the second semiconductor layer and the active layer to expose the at least one first portion of the first semiconductor layer, forming at least one isolation trench extending through the at least one first portion of the first semiconductor layer.

25. The method according to claim 24, wherein the isolation trench is formed by etching the first portion of the first semiconductor layer until the substrate is exposed.

26. The method according to claim 24 or 25, wherein the isolation trench is filled with a passivation layer.

27. The method according to claim 26, further comprising: dicing or etching the multi-layer structure along the at least one isolation trench to form at least one light-emitting device die.

28. The method according to any one of claims 1 to 27, further comprising: removing the substrate using one of laser liftoff, lapping or chemical etching.

29. The method according to claim 28, wherein an unintentionally doped layer is sandwiched between the substrate and the first semiconductor layer; wherein the substrate is removed to expose the unintentionally doped layer.

30. The method according to claim 29, further comprising: roughening the exposed unintentionally doped layer.

31. The method according to claim 29 or 30, wherein the unintentionally doped layer comprises an unintentionally doped gallium nitride layer.

32. The method according to any one of claims 1 to 31, wherein the first semiconductor layer comprises an n-type doped gallium nitride layer, an n-type doped aluminum gallium nitride layer, an n-type doped indium gallium nitride layer, or an n-type doped aluminum gallium indium nitride layer.

33. The method according to any one of claims 1 to 32, wherein the second semiconductor layer comprises a p-type doped gallium nitride layer, a p-type doped aluminum gallium nitride layer, a p-type doped indium gallium nitride layer, or a p-type doped aluminum gallium indium nitride layer.

34. The method according to any one of claims 1 to 33, wherein the active layer comprises one or more quantum well layers sandwiched by quantum barrier layers.