EP2936714B1 - Method for scrambling a communication system by inserting dummy patterns into a data stream to be transmitted - Google Patents

Description

The invention relates to the field of interference in which an objective consists in neutralizing a communication system by disturbing the signal transmitted by a transmitter of the system and to a receiver of the system.

The communication systems use, during the generation of the signal to be transmitted, particular sequences, inserted in the signal, which are used to synchronize the transmitter and receiver equipment with each other. These synchronization sequences are fixed once and for all by the communication protocol or the system implementation standard and are inserted in the signal to be transmitted with the modulated information sequences.

The invention relates to a method for jamming a communication system that aims to transmit a signal respecting the same standard as that of said system but having several dummy synchronization patterns inserted in order to make it more difficult for a receiver to synchronization with a transmitter.

The invention also aims to transform a standard transmitter of the communication system to scramble jammer without changing the transmission channel of this equipment. The dummy synchronization pattern (s) are introduced into the transmitted signal by generating a suitable bit sequence directly in the binary data sequence to be transmitted. The invention thus does not require any modification of the transmitter equipment because it intervenes upstream of the transmission chain.

The technical problem addressed by the present invention is to neutralize a communications system from one or more terminals of said system transformed into scrambler (s). By reusing one or more terminals of the communication system that one wishes to neutralize, one obtains one or more jammers at low costs and which can adapt to a wide variety of standardized communication networks. The invention thus aims to design a scrambling solution that does not require scrambling equipment dedicated for this purpose alone.

The documents FR 2,858,742 , US 8,055,184 and US 2010/302956 describe scrambling systems of synchronization.

Known scrambling systems are generally based on specific scrambling devices that have the following disadvantages.

The energy consumption in a scrambler is generally very high because the scrambling waveform used is not optimized to effectively neutralize a communication system.

In order to limit the energy consumption and to guarantee the effectiveness of the neutralization, the interference waveform must, on the contrary, be as coherent as possible with the signals whose reception is to be disturbed.

Moreover, the usual scrambling waveforms that are known are generally of low combinatorial and complex and therefore easily detectable (this is particularly the case with the so-called jamming waveforms, which make these devices very intrusive), or very complex, when the scrambler aims, for example, to implement the exact waveform of the telecommunication system to neutralize to achieve decoy effects or access saturation.

In addition, many known scrambling systems most often suffer from a lack of scalability, adaptability or flexibility mainly related to the choice of hardware and software architectures.

Finally, the known scrambling systems which have a significant range are also of a cost, a size and a high energy consumption.

The invention aims to solve the aforementioned problems and to eliminate the limitations of the solutions of the prior art by proposing a method of jamming a communications system from a modification of the useful data produced at the input of a terminal of said system. The invention consists in particular in performing a specific coding of the useful data transmitted by a compatible terminal of the system to be neutralized so as to indirectly generate in the signal transmitted in fine, one or more dummy synchronization patterns with stationary characteristics, which are easily interpretable by the receivers of the targeted communication system, and whose recurrence and placement in the transmitted frame are chosen to optimize the effects of decoy and saturation of the target reception chain. In this way, a receiver of the system to be neutralized can no longer synchronize properly. The implementation of the method according to the invention at the level of the useful data to be transmitted and not at the level of the transmission channel makes it possible to provide a low-cost solution that does not require modifying the transmitter equipment to transform it into a transmission system. scrambler. In addition, the use of several modified terminals makes it possible to form a network of cooperative jammers whose neutralization performance is increased compared to the use of a single modified terminal. Indeed, the low transmission power of a terminal is compensated by a mesh of the space to be covered and by the use of several terminals that emit simultaneous jamming signals. When the method according to the invention is applied to a plurality of transmitters, the invention makes it possible to reproduce, with said transmitters, the topology of the communications system to be scrambled. The invention also makes it possible to increase the overall coverage in unfavorable propagation environment for the transmitter network implementing the invention. The invention also increases the effects of decoy but also the effects of saturation access. More generally, the invention makes it possible to induce effects which neutralize the communication system to be scrambled but which are difficult to diagnose or to interpret, insofar as these effects reproduce cases encountered in the engineering of difficult or pathological radiocommunication networks. but not exceptional.

The scope of the present invention is limited by the appended claims.

• La figure 1a, un schéma illustrant la synchronisation entre un récepteur et un émetteur compatibles d'un même système de télécommunication,
• La figure 1b, un schéma illustrant, l'effet obtenu par application du procédé de brouillage selon l'invention,
• La figure 2, un schéma illustrant la transformation opérée par la chaine d'émission d'un terminal émetteur pour convertir les données utiles à émettre en symboles modulés prêt à être émis par voie radio,
• La figure 3, un schéma illustrant la génération, selon l'invention, de bits factices au sein des données utiles en entrée de la chaine d'émission d'un terminal émetteur,
• La figure 4, un schéma bloc des différentes fonctions successivement mises en oeuvre par un terminal émetteur,
• La figure 5, un schéma des registres à décalage d'un code convolutif de rendement ½,
• La figure 6, une représentation, pour l'exemple de code convolutif associé à la figure 5, de la matrice génératrice d'un tel code,
• La figure 7, une illustration de la condition nécessaire et suffisante pour imposer, en sortie du code convolutif défini aux figures 5 et 6, les valeurs d'une séquence de bits consécutifs,
• La figure 8, une illustration des relations de parité d'un code poinçonné.

Other features and advantages of the present invention will appear better on reading the description which follows in relation to the appended drawings which represent:

• The figure 1a , a diagram illustrating the synchronization between a receiver and a compatible transmitter of the same telecommunication system,
• The figure 1b , a diagram illustrating, the effect obtained by applying the scrambling method according to the invention,
• The figure 2 a diagram illustrating the transformation effected by the transmission channel of a transmitting terminal for converting the useful data to be transmitted into modulated symbols ready to be transmitted by radio,
• The figure 3 , a diagram illustrating the generation, according to the invention, of dummy bits within the input user data of the transmission channel of a transmitting terminal,
• The figure 4 , a block diagram of the various functions successively implemented by a transmitting terminal,
• The figure 5 , a diagram of the shift registers of a convolutional code of output ½,
• The figure 6 , a representation, for the convolutional code example associated with the figure 5 , of the matrix generating such a code,
• The figure 7 , an illustration of the necessary and sufficient condition to impose, at the output of the convolutionary code defined in figures 5 and 6 , the values of a sequence of consecutive bits,
• The figure 8 , an illustration of the parity relationships of a punched code.

In the rest of the description, the expression "useful data", "useful bits", "useful information" is used to designate the binary data to be transmitted between the application executed by a transmitter and the corresponding application executed by a receiver. as opposed to the binary data present in the transmitted frames but which are not intended for the application executed by the receiver but are used for signaling purposes, synchronization or any other function necessary for the proper functioning of the communication system.

The figure 1 illustrates, in two diagrams, the principle of synchronization between a receiver and a compatible transmitter of the same telecommunication system.

On the top of the figure 1 a is shown a wireless communication system in the form of an emitter EM which communicates with a receiver REC by radio wave. The transformation of the binary data to be transmitted into a radio signal S can be specified by a standard or a telecommunications standard. This specification defines, in particular, the insertion, within the signal to be transmitted, of synchronization sequences SYNC. Such sequences consist of symbols known from the system equipment and positioned periodically or in a time pattern also known from both the EM transmitter and the REC receiver that implement the same telecommunications standard.

On the bottom of the figure 1 a is represented, on an amplitude / time diagram, the result obtained by correlating the known synchronization sequence with the received signal. The peak amplitude of the correlation result gives an estimate of the timing position of the synchronization sequence in the received signal. By performing such correlation operation, the receiver REC can synchronize temporally with the emitter EM by detecting for example the beginning, the middle or the end of a frame, indicated by the presence of said sequence, within the emitted signal. An object of the invention is to neutralize the EM, REC communications system by disrupting the synchronization of transmitting and receiving equipment.

The figure 1b illustrates, in two diagrams, the scrambling method according to the invention.

On the top of the figure 1b is represented a set of transmitters EM_B1, EM_B2, ..., EM_BN (with N = 3 in the illustrative but nonlimiting example of the figure 1b , the emitters being EM_B1, EM_B2, EM_B3), which are compatible with the same telecommunications standard as the EM transmitter and the REC receiver that one wishes to neutralize. These emitters EM_B1, EM_B2, ..., EM_BN (with always N = 3 in the example of the Figure 1 (b) are modified, according to the invention, to generate a scrambling signal S _B to the receiver REC. They constitute a co-operative jamming system, also called cooperative scrambler network. The interference signal S _B is of the same nature as the signal S transmitted by an emitter EM of the communications system to be neutralized with the difference ready that it comprises at least one fake synchronization sequence SYNC _F. On the figure 1b is represented the scrambling signal S _B consisting of the superposition of the scrambling signals respectively emitted by N adapted emitters EM_B1, EM_B2, ..., EM_BN. Each of the N jamming signals comprises at least one dummy synchronization sequence with the stationary characteristics SYNC _F1 , SYNC _F2 ,..., SYNC _FN , placed in the frame according to recurrences adapted to the time windowing of the targeted receivers. These sequences are therefore both plausible for the target receiver and sufficiently frequent to be regularly present in the processing windows of said receivers. Advantageously, the dummy sequences may comprise the same symbols as the sequence of SYNC actual synchronization but be transmitted at times and / or on different frequencies, and with multiple frame recurrences that SYNC real synchronization pattern. In an alternative embodiment, each of the N jamming signals originating from the emitters EM_B1, EM_B2,..., EM_BN comprises the N dummy timing sequences SYNC _F1 , SYNC _F2 ,..., SYNC _FN positioned at different time instants in the emitted frame. This variant has the advantage of increasing the overall performance of the jamming signal in the face of communication networks exploiting a non-trivial combination of synchronization sequences SYNC.

In another variant embodiment, each of the N scrambling transmitters EM_B1, EM_B2,..., EM_BN respectively emits a significant number of copies of each of the fake synchronization sequences (respectively k ₁ SYNC _F1 sequences, k ₂ SYNC _F2 sequences). , ..., k _N SYNC sequences _FN ) positioned at different time instants in each transmitted frame. This variant again has the advantage of increasing the overall performance of the scrambling signal against target receivers whose precise timing is not known jammers EM_B1, EM_B2, ..., EM_BN.

The transmission of jamming signals comprising dummy synchronization sequences positioned at random locations in the transmitted frames has the effect of making it difficult or impossible to synchronize the REC receiver which will not be able to discriminate the actual synchronization pattern of the dummy synchronization patterns.

This effect is illustrated in the diagram shown at the bottom of the figure 1b which gives the result of the correlation operation performed by the receiver REC in the presence of the emitted interference signals. The amplitude peak of the correlation result corresponding to the actual SYNC synchronization sequence is strongly polluted by a plurality of peaks of amplitudes of correlation results 11, 12, 13, 14 corresponding to the presence of dummy timing sequences.

One of the objectives of the invention is to allow the insertion of dummy synchronization patterns in the signal transmitted by a terminal of the communications system to be scrambled without modifying the elements of the transmit channel of the transmitter but on the contrary by acting only on the binary data used at the input of the transmission channel.

The figure 2 schematically illustrates the transformation undergone by a sequence of useful binary data Du to be transmitted to obtain a sequence of modulated symbols S _T , ready to be transmitted by way of a radio signal. The transformation executed corresponds to the transfer function F of the transmission chain of the transmitter. The sequence of modulated symbols S _T is constituted on the one hand by useful symbols S _U resulting from the transformation of the useful binary data Du and on the other hand by at least one synchronization sequence SYNC or an equivalent sequence composed of symbols known from all the equipment of the communication system.

The figure 3 illustrates the implementation of the method according to the invention, on a compatible terminal of the communication system to be scrambled or on any other type of transmitter capable of producing compatible signals of the communication system to scramble.

Firstly, the generated SYNC _F dummy synchronization sequences are positioned in an empty dummy frame T _F of the same size as a real modulated sequence of symbols S _T , at the selected time positions, different from the temporal position of a sequence actual synchronization.

In a second step, it is estimated the value and the position of the dummy bits B _F to be inserted in the data sequence to be transmitted at the input of the transmission channel so as to obtain, at the output of the transmission channel, the value and the predefined temporal position of the symbols of said fake sequences SYNC _F. This operation can be performed by calculating the inverse transfer function F ^-1 of the transfer function F implemented by the transmission chain and then applying the inverse transfer function F ^-1 to the dummy frame T _F to obtain a frame modulated D _F comprising the dummy bits B _F.

The dummy bits B _F are then inserted into the actual data sequence to be transmitted from the input of the transmission chain by punching the relative positions of the dummy bits of the dummy frame D _F in a real data sequence. The sequence of modulated symbols obtained at the output of the transmission chain comprises both the useful data symbols S _U , the actual SYNC synchronization pattern and the SYNC _F fake synchronization patterns.

The dummy bits can be introduced directly into the useful data stream to be transmitted without modifying or intruding into the transmission chain of the transmitting equipment.

For example, it is possible to use fully programmable useful content data transmission modes (eg messaging services) and to construct completely deterministic messages containing the dummy bits outputting the desired SYNC _F patterns.

It is also possible to use transmission modes corresponding to applications, for example to intervene on a useful stream coming from an audio or video source coder. For this, for example, the application binary data is intercepted before entering the transmission chain at the level of the physical layer of a modem. This interception can also be done at an intermediate layer, for example at the network layer. In both cases it is necessary to take into account, according to the procedures described below, neighboring useful information bits which are random and variable.

The figure 4 represents a block diagram of the various functions successively implemented by a transmitter of a communication system for transmitting a signal containing data to be transmitted. The main functions traditionally used are represented, it being understood that the diagram of the figure 4 is given as an illustration and not a limitation. In particular, some functions may be omitted and the order of some functions may be changed. The transfer function F of the transmission chain is equal to the composition of the transfer functions of each functional block independent of the chain, it being understood that the blocks are connected in series. The inverse transfer function F ^-1 is, when it exists, equal to the composition, in reverse order, of the inverse transfer functions of each block. In other words, if f ₁ , f ₂ , ... f _N are the transfer functions of each functional block of the chain, then the global transfer function F is equal to F = f ₁ of _{2 O ... O} f _N and the inverse transfer function F ^-1 is equal to F ^-1 = f _N ^-1 of _N-1 ^-1 _{O ... O} f ₁ ^-1 .

To estimate the global inverse transfer function F ^-1 , it is therefore necessary to determine the inverse transfer function of each unit block.

The direct transfer function F of the transmission channel may be known when the invention is implemented by the designer of the communications system or when said system respects a known standard. It can also be estimated by testing the sending equipment, for example by injecting test signals at its input and by analyzing the signals obtained at the output.

The transformations applied in the transmission channel on the bitstream are generally reversible, that is to say that it is possible from the bitstream output to find the input bitstream.

However, certain functions implemented by the transmission channel of a communications system may not always be surjective. In other words, it may happen that a TBC encoded bitstream, which one would like to force the values, at the output of a module of the transmission chain does not correspond to any series of TBU useful bits at the input of said module. By for example, the channel coding or framing operations transform a useful bitstream of length Lu into a coded bitstream of length Lc. Because of the framing operations necessary to ensure the synchronization of the receiver, and the error correction coding necessary to compensate for the effect of the propagation channel, Lc> Lu is still practically always used. This means that among the 2 ^{L vs} sequences of Lc coded bits, only 2 ^{L u} sequences can be obtained by coding. Coding is therefore never surjective.

In such a case, it is not possible to determine the inverse transfer function F ^-1 of the overall transmission chain, but only the inverse F ^-1 of the transmission channel on the restricted image F ( {TBU}) of the {TBU} set of useful bitstreams at the input of the transmission channel.

It is therefore sought to determine to what extent it is possible to force the value of some of the bits of the coded signal. In particular, it is sought to determine the number of bits whose value can be imposed and to what extent it is possible to choose not only the value but also the position of these bits. In the case of a channel coder, it is sought to impose the value of a series of consecutive coded bits so as to obtain coded patterns which resemble synchronization patterns.

The practical implementation consists in successively analyzing the various transformations of the bit stream, starting with the transformation that occurs last in the transmission chain. For each transformation, the inputs to be applied are determined to output the desired coded bitstream.

In this view, the elementary transformations of the bit stream and their invertibility are analyzed case by case in the following description.

The transmission channel 400 shown in FIG. figure 4 comprises an application 401 capable of generating or transforming a data sequence binary to emit. The data to be transmitted can be text, audio, video or any other information. The application 401 may also include a source coding function, for example an audio, image or video coder able to suppress or reduce the redundancy of information or to reduce the noise affecting the sequence. The application 401 outputs a useful bit sequence T to be transmitted. The invention is advantageously implemented at the output of the application 401 by modifying the useful binary sequence T to insert dummy bits therein so as to obtain at the output of the transmission channel a sequence of modulated symbols F (T) (t). ) to be transmitted comprising at least one dummy synchronization pattern.

The transmission channel 400 may also include a correction coding module 402.

The objective of a corrective coding function is to transform the binary sequence of useful data received at the output of the application 401 into a protected bit sequence so that the impact of the errors due to the transmission channel is as small as possible. . To make the payload bit sequence more robust to the imperfections of the transmission channel, the corrective encoding function adds redundancy to this bit sequence.

The determination of the inverse transfer function of a correction coding module is equivalent to finding the bit sequence to be produced at the input of the correction coder in order to obtain an encoded sequence in which the value and the position of a predetermined number of bits are imposed.

There are different types of correcting codes including linear block codes, convolutional codes or turbo codes and LDPC low density codes.

Subsequently, the determination of the reverse transfer function of a correction coder is described for different types of correction codes, the block linear codes, convolutional codes, as well as turbo codes and LDPC codes.

Linear codes in blocks

A k / n efficiency linear block corrector code transforms a binary sequence comprising k symbols into a protected bit sequence comprising n symbols with n strictly greater than k. Such a code thus introduces nk redundancy symbols. The symbols may be bits or consist of several concatenated bits. The block coding operation is a one-to-one transformation of a word of the message i = (i ₀ , ..., i _k-1 ) into a code word c = (c ₀ , ..., _{Cn -1)} defined by the following system of linear equations (where "+" denotes the addition modulo 2 "." denotes multiplication modulo 2) and _g are valued coefficients in the body of Welsh GF (2) , stored in a matrix of size nxk: $${\mathrm{vs}}_{\mathrm{not}}={\displaystyle \underset{e=0}{\overset{k}{\Sigma }}}{\mathit{boy\; Wut}}_{\mathit{in}}\mathrm{.}{i}_e,\mathrm{for}0\le \mathrm{i}\le \mathrm{not}-\mathrm{1}$$

Of the 2 ⁿ binary sequences with n bits that exist, only 2 ^k can be generated. The correcting coding operation therefore limits the possibility of generating any desired bit sequence.

The block coding consists in producing the product of an input information vector of k bits by a binary matrix, of full rank, of size k * n, called generator matrix, to obtain an encoded vector of n bits. Often the code is said systematically on the left, respectively on the right, when the first k, respectively the last k, bits of the encoded vector of n bits correspond to the k bits of the input information vector. The encoding operation can be illustrated by the following relation, where i ₀ , ... i _k-1 are the bits of the input useful sequence, c ₀ , ... c _n-1 are the bits of the sequence coded and m _{i, j} are the coefficients of the generator matrix of the code. $$\left[\begin{array}{ccc}{\mathrm{vs}}_0& \mathrm{...}& {\mathrm{vs}}_{\mathrm{not}-1}\end{array}\right]=\left[\begin{array}{ccc}{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">i</figure-callout>}}_0& \mathrm{...}& i_{k-1}\end{array}\right]<figure-callout\; id="0"\; label="\cdot \; m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">\cdot \; </figure-callout>\left[\begin{array}{c}{m}_{}\end{array}\right]\left[\begin{array}{ccccc}{}_{0,0}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}"><figure-callout\; id="2"\; label="m"\; filenames="imgf0007.png"\; state="\{\{state\}\}">m</figure-callout></figure-callout>}}_{0,2}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,\mathrm{not}-1}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,0}& m_{k-1,1}& m_{k-1,2}& \mathrm{...}& m_{k-1,\mathrm{not}-1}\end{array}\right]$$

Systematic block code case

In the case where the code is systematic on the left, the coded sequence is written [ i ₀ ... i _{k -1} c _k ... c _n-1 ]. The inverse transform of the coding operation is to analyze the received word to determine if it is a possible code word. If it is not a possible code word, it must be replaced by the codeword at a minimum distance from the received code word. Then, as the code is systematic, the information is obtained by removing the last nk bits of the word. In other words, it is possible to impose, by the choice of the input sequence, the output value of the first k bits of the codeword. The values of the remaining nk bits are then deduced from the values chosen for the k bits that were forced. It is exactly the same for a systematic block code on the right.

Block coding cases from cyclic codes

Bulk codes commonly used are cyclic block codes or are derived from cyclic block codes by punching or shortening.
In the case of a cyclic block code, if [ c ₀ ... c _{n -1} ] is a code word, any circular permutation of the word [ c _i c _{i + 1} ... c _n -1 c ₀ ... c _{i -1} ] is also a code word.
By writing in polynomial form the words of code c ( x ) = c ₀ + c1 · x + c ₂ · x ² + ... + c _{n -1} · x ^{n -1} , all the code words appear as multiples of the same polynomial g ( x ) = g ₀ + g ₁ · x + g ₂ · x ² + ... + g _nk · x ^nk , of degree nk, called generator polynomial of the code.
An information word [ i ₀ ... i _{k -1} ] can also be written in polynomial form i ( x ) = i ₀ + i ₁ x + i ₂ · x ² + ... + i _{k - 1} · x ^{k -1} . It is always possible to write the encoding operation in systematic form on the right. This encoding operation consists of calculating the division of i ( x ) · x ^nk by g ( x ). The remainder of the division is v ( x ) (of degree less than or equal to nk-1) and the quotient of the division is k ( x ). So we have i ( x ) · x ^nk = k ( x ) · g ( x ) + v ( x ), and c ( x ) = i ( x ) · x ^nk + v ( x ) = k ( x ) · g ( x ).
Since v ( x ) is of degree less than or equal to nk-1, the values of the coefficients of c ( x ) for degrees greater than or equal to nk are the coefficients of i ( x ) shifted by nk.

It is therefore always possible to write the cyclic block codes in systematic form on the right, and thus to impose the value of the k last bits that are equal to the information bits. Since the code is cyclic, and therefore any circular permutation of a code word is also a codeword, it means that it is also possible, for cyclic codes, to impose the value of any group of k consecutive bits of a codeword.

Moreover, the dependence between the values of the input bits of the encoder and the bits at the output of the encoder is linear. The values of the bits that must be forced into the encoder input linearly depend on the values of the other encoder input bits and the forced bit values at the encoder output.

General case of bulk codes

est de rang plein, c'est-à-dire de rang égal à d.In the more general case where the code is not systematic nor derived from cyclic codes, a sufficient condition to be able to impose the value of a group of d bits at the output of the encoder, with d less than or equal to k, is that set of the positions p ₁ , p ₂ , ... p _d , bits in the coded sequence must be such that the sub-matrix of the matrix generating the code: $$\left[\begin{array}{ccccc}{\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_2}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]$$

is of full rank, that is to say of rank equal to d.

où [C_P1... C_Pd] sont les bits ou symboles dont la valeur est fixée dans la séquence codée, les indices p₁,P₂,...p_d, désignant les positions des bits ou symboles dans la séquence de n bits ou symboles.Indeed, when this condition is fulfilled, it is possible to determine the sequence [ i ₀ ... i _{k -1} ] at the input of the encoder which makes it possible to fix the values of d bits or symbols in the coded sequence by solving the system. following equations: $$\left[\begin{array}{ccc}{i}_0& \mathrm{...}& i_{k-1}\end{array}\right]=\left[\begin{array}{ccc}{\mathrm{vs}}_{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">p</figure-callout>}}_1}& \mathrm{...}& {\mathrm{vs}}_{p_d}\end{array}\right]\cdot {\left[\begin{array}{ccccc}{\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_2}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]}^{-1}$$

where [C _P1 ... C _Pd ] are the bits or symbols whose value is fixed in the coded sequence, the indices p ₁ , P ₂ , ... p _d , designating the positions of the bits or symbols in the sequence of n bits or symbols.

Thus, for all the usual block codes, which are systematic, or cyclic, or built from cyclic codes, that is to say for most of the usual codes, it is possible to impose, by the choice of the inputs of the encoder, any group of k consecutive bits out of the n bits of the encoded vector. Moreover, in the case of two successive codewords, by imposing the k last bits of the ^1st code word and the first k bits of the 2 ^nd code word, it is possible to impose the value of a group of 2k successive bits on a binary sequence comprising at least two codewords.

In the most general case, the sub-matrix of the generator matrix of the block code corresponding to the positions of the bits or symbols to be fixed is of full rank. However, in some cases, some submatrices of the generator matrix may not be of full rank. Such a case is illustrated in a nonlimiting example of a Hamming code (7.4) whose generator matrix M (7.4) is given by $$\mathrm{<figure-callout\; id="7"\; label="M"\; filenames="imgf0007.png"\; state="\{\{state\}\}">M</figure-callout>}\left(7,4\right)=\left[\begin{array}{ccccccc}1& 1& 0& 1& 0& 0& 0\\ 0& 1& 1& 0& 1& 0& 0\\ 1& 1& 1& 0& 0& 1& 0\\ 1& 0& 1& 0& 0& 0& 1\end{array}\right]$$

• [c ₀ c ₁ c ₂ m ₀ m1 m ₂ m ₃], il suffit de coder le vecteur d'information i(x)=[m ₀ m ₁ m ₂ m ₃].

The generating polynomial of this code is g ( x ) = 1 + x + x ³ . For this code it is possible to impose the last 4 bits (m ₀ to m ₃ ) of the code word because the coding is systematic right. To get the following code word:

• [ c ₀ c ₁ c ₂ m ₀ m 1 m ₂ m ₃ ], it suffices to code the information vector i ( x ) = [ m ₀ m ₁ m ₂ m ₃ ].

• c_sys,droite (x)=i(x)·x^n-k +v(x)=k_sys,droite (x)·g(x), où k_sys,droite (x) est le vecteur à coder et c_sys,droite (x) est le mot de code obtenu.

The encoding operation is represented by the following relation:

• c _{sys, right} ( x ) = i (x) · x ^nk + v ( x ) = k _{sys, right} ( x ) · g ( x ), where k _{sys, right} ( x ) is the vector to code and c _{sys , right} ( x ) is the obtained code word.

It is also possible to impose, for example, the first 4 bits of the code word to the values of the information vector [ m ₀ m ₁ m ₂ m ₃ ]. For that we have to find the information vector which, once coded, gives the following code word: $$k_{\mathit{sys},\mathit{left}}\left(x\right)\cdot \mathrm{boy\; Wut}\left(x\right)\cdot ={\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_0+{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">m</figure-callout>}}_1\cdot x+{\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="imgf0007.png"\; state="\{\{state\}\}">m</figure-callout>}}_2\cdot x^2+{\mathrm{<figure-callout\; id="3"\; label="m"\; filenames="imgf0007.png"\; state="\{\{state\}\}">m</figure-callout>}}_3\cdot x^3+\mathrm{vs}{\text{'}}_4\cdot x^4+\mathrm{vs}{\text{'}}_5\cdot x^5+\mathrm{vs}{\text{'}}_6\cdot x^6\mathrm{.}$$

To compute this vector of information k _{sys, left} ( x ), one uses the property that the code is invariant by circular permutation. We move from a systematic coding on the right to a systematic coding on the left by 4 circular permutations to the right. Therefore, the code word [ c ₀ c ₁ c ₂ m ₀ m ₁ m ₂ m ₃ ] becomes the codeword [ m ₀ m ₁ m ₂ m ₃ c ₀ c ₁ c ₂ ] by performing these 4 circular permutations. The code word [ m ₀ m ₁ m ₂ m ₃ c ₀ c ₁ c ₂ ] is obtained by encoding the information vector i '( x ) = [ m ₃ c ₀ c ₁ c ₂ ] (because the code is systematic right).

On the other hand, one can notice that if one considers the second, the fourth, the fifth and the sixth column of the generating matrix of the code M (7,4), one obtains the following sub-matrix which is not of full rank , the coefficients of its last line being equal to 0: $$\left[\begin{array}{cccc}1& 1& 0& 0\\ 1& 0& 1& 0\\ 1& 0& 0& 1\\ 0& 0& 0& 0\end{array}\right]$$

In fact, the rank of a matrix corresponds to the number of independent columns of the matrix or equivalently to the number of independent rows of the matrix.
It is therefore not possible to force the values of these 4 bits (the second, fourth, fifth and sixth) of the coded word: if the value of 3 of these bits is forced, the value of the fourth bit is deduced. values imposed on the three forced bits.

It is therefore not possible, for any code ( n, k ) of yield k / n, to force the value of any group of k bits. On the other hand, for the codes used most frequently, it is possible to force the value of any group of consecutive nk bits when the sub-matrix of the matrix generating the code associated with the positions of the bits to be set is of full rank.

• Si on souhaite imposer la valeur d'un nombre limité l, inférieur à k, de bits en sortie du codeur, il suffit d'imposer la valeur de l bits en entrée du codeur.
• Par contre, la valeur de ces bits dépend non seulement de la valeur du motif généré en sortie du codeur mais aussi des valeurs des autres bits en entrée du codeur (que l'on peut le cas échéant forcer aussi dans le cadre de la mise en oeuvre de la présente invention).

Here, the dependencies between the values of the input bits of the encoder and the values of the bits at the output of the encoder are specified.

• If it is desired to impose the value of a limited number l, less than k, of bits at the output of the encoder, it suffices to impose the value of 1 bits at the input of the encoder.
• On the other hand, the value of these bits depends not only on the value of the pattern generated at the output of the encoder but also on the values of the other bits at the input of the encoder (which may also be forced also in the context of the implementation of the encoder). of the present invention).

si l'on veut forcer la valeur des 2 premiers bits codés, c₀ et c₁, on peut choisir un vecteur d'information i(x)=[f ₀ f ₁ i₀ i₁], où i₀ et i₁ sont des bits d'information laissés libres et f₀ et f₁ des bits forcés pour obtenir le motif voulu. Les valeurs qu'il faut choisir pour f₀ et f₁ afin d'obtenir les valeurs voulues de c₀ et c₁ sont données par les relations : $${\mathrm{f}}_{\mathrm{0}}={\mathrm{c}}_{\mathrm{0}}+{\mathrm{i}}_{\mathrm{1}}+{\mathrm{i}}_{\mathrm{2}}$$

$${\mathrm{f}}_1={\mathrm{c}}_{\mathrm{0}}+{\mathrm{c}}_{\mathrm{1}}+{\mathrm{i}}_{\mathrm{2}}$$

Using the example of the coding matrix $$M$$$$\left(7,4\right)=\left[\begin{array}{ccccccc}1& 1& 0& 1& 0& 0& 0\\ 0& 1& 1& 0& 1& 0& 0\\ 1& 1& 1& 0& 0& 1& 0\\ 1& 0& 1& 0& 0& 0& 1\end{array}\right],$$

if we want to force the value of the first 2 coded bits, c ₀ and c ₁ , we can choose an information vector i ( x ) = [ f ₀ f ₁ i ₀ i ₁ ], where i ₀ and i ₁ are bits of information left free and f ₀ and f ₁ forced bits to obtain the desired pattern. The values to be chosen for f ₀ and f _{1 in} order to obtain the desired values of c ₀ and c ₁ are given by the relations: $${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">f</figure-callout>}}_{\mathrm{0}}={\mathrm{<figure-callout\; id="0"\; label="vs"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">vs</figure-callout>}}_{\mathrm{0}}+{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">i</figure-callout>}}_{\mathrm{1}}+{\mathrm{i}}_{\mathrm{2}}$$

$${\mathrm{<figure-callout\; id="1"\; label="f"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">f</figure-callout>}}_1={\mathrm{<figure-callout\; id="0"\; label="vs"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">vs</figure-callout>}}_{\mathrm{0}}+{\mathrm{<figure-callout\; id="1"\; label="vs"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">vs</figure-callout>}}_{\mathrm{1}}+{\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="imgf0007.png"\; state="\{\{state\}\}">i</figure-callout>}}_{\mathrm{2}}$$

This illustrates that the values of the bits forced into the input of the encoder (f ₀ and f ₁ ) depend linearly on the values of the bits of the pattern at the output of the encoder (c ₀ and c ₁ ) and the values of the other bits at the input of the encoder .

Convolutional codes

Convolutional codes are the second major family of error-correcting codes. While linear block codes are used to split the message into blocks of k symbols, the convolutional codes apply a sliding window of k * ( m + 1) symbols to the message and produce a continuous sequence of encoded symbols.
In general, the symbols are binary (ie at value 0 or 1 in the Welsh GF (2) body, "+" means the modulo 2 addition and "." Means the modulo 2) multiplication. Most often convolutional codes have for parameter k = 1 and the code yield is thus of the form 1 / n . Let a _{j be} an information symbol, the parity symbols b _j associated with a _j are defined by the following convolution relation, where g _{e, j, i} are the coefficients of n * k polynomials of degree m with coefficients and values in the body of Welsh GF (2) (the code is entirely defined by the set of coefficients g _{e, j,} i, e = 0, ..., m , j = 0 ... k -1, i = 0 ... n -1): $$b_{p\cdot \mathrm{not}+i}={\displaystyle \underset{e=0}{\overset{m}{\Sigma }}}{\displaystyle \underset{j=0}{\overset{k-1}{\Sigma }}}{\mathrm{boy\; Wut}}_{e,j,i}\cdot {\mathrm{at}}_{p\cdot k+j-e\cdot k},\mathrm{for}\mathit{i}=\mathrm{0\; ...}\mathrm{not}-1,\forall p$$

The n symbols at the output of the encoder depend linearly on the k * ( m +1) last symbols at the input of the encoder.

From a yield code 1 / n, so-called "derivative" codes, corresponding to k > 1, can be constructed by punching (most often k = n -1 after punching).

More generally, when the code efficiency is equal to k / n, the convolutional coding is a periodic k- bit period coding on the input binary signal. For each new group of k bits, n coded bits are calculated. The n coded bits are bit combinations relating to the (m + 1) last groups of k bits. m is the constraint length of the code.

The step of the method according to the invention, which consists in inverting the transfer function of a convolutional code, that is to say, determining the sequence of bits to be produced at the input to obtain an output of a signal, is illustrated in a nonlimiting example. encoded sequence in which the value and the position of a predetermined number of bits are set.

Non-limiting example of a ½ yield convolutional code

We consider a usual convolutional binary code whose registers are represented on the figure 5 , of output 1/2 and of length m + 1 = 7 defined by two polynomials of degrees 6 defined in octal notation by (171, 133). These two polynomials are written G ₁ (X) = 1 + X + X ² + X ³ + X ⁶ and G ₂ (X) = 1 + X ² + X ³ + X ⁵ + X ⁶ and correspond to the recurrence relations b _2n = a _n + a _n-1 + a _n-2 + a _n-3 + a _n-6 and b _{2n + 1} = a _n + a _n-2 + a _n-3 + a _n-5 + a _n-6 in Galois GF2 ("+" refers to the addition of modulo 2). The polynomials G ₁ and G ₂ are applied to the input bits to respectively form the even index output bits and the odd index output bits then interleaved in pairs b _2n b _{2n + 1} to form a bit stream of size equal to a multiple The following illustrates the possibility of choosing the input bitstream to generate desired patterns after coding.

For this code, at each period, for a bit produced at the input of the encoder, two bits are generated at the output. Depending on the state of the encoder registers, the two bits (b _2n , b _{2n + 1} ) at the output are to be chosen from either (0,0) or (1,1), or (0,1) or (1, 0). Indeed, the last bit that enters the encoder is used for the calculation of each of the two outputs of the encoder: by changing this bit, the values of the two outputs are changed. This means that, for a state of the given register, the two possible output bits are to be chosen from two complementary groups. It is therefore always possible to choose the input bit so as to force the value of one of the two output bits. It is therefore easy with this code to force every other bit at the output of the encoder.

In practice, for the most efficient codes used in a modem, the outgoing bit groups, for a state of the encoder, are chosen so as to be at maximum distance from each other. For these codes, the last bit that enters the encoder is used for the calculation of each of the two outputs of the encoder. It is therefore possible, for all the usual 1/2 output codes, to force the value of one bit out of two at the output of the encoder.

It is now demonstrated that it is also possible to choose a series of bits at the input of the encoder so as to obtain at the coder output an encoded sequence comprising a series of consecutive bits of fixed value. We consider again the previous example of the coder r = k / n = 1/2, (171, 133) of length m + 1 = 7. For this encoder, the impulse response, that is to say the response of the coder to an input bit sequence comprising a bit of value 1 preceded and followed by bits all having the value 0, is given by the sequence 11101111000111, of length 14 = 2m + 2.
The encoding operation can be written in matrix form, represented in figure 6 , where the lines of the generator matrix of the code correspond to the impulse response of the encoder, shifted by 2 bits from one line to the other (because n = 2), or more generally shifted by n bits from one line to the other. other when the code is 1 / n.

A formalism identical to that used for the linear block codes is then obtained, that is to say that the coded sequence is obtained by carrying out the matrix product of the information sequence with the generating matrix defined above.

The same rule previously enacted concerning the codes in linear blocks can thus be applied to the convolutional codes, that is to say that it is possible to impose the value and the position of a set of bits at the output of the encoder if and only if the submatrix M corresponding to the columns of the output bits is of full rank, as illustrated by figure 7

It can thus be seen that for this convolutional code, it is possible to force the value of 14 consecutive bits at the output of the encoder, from the inputs. This result can also be interpreted from the point of view of parity relations between coded bits. These deterministic relationships characterize in a one-to-one way the dependencies verified by the coded bit groups. In other words, the values of the coded bits corresponding to a parity relation are interdependent. The values of the coded bits that do not correspond to a parity relation can be set independently of one another. The code previously considered has parity relations of length 14 and spaced by 2 bits. It is therefore possible to choose 14 consecutive coded bits corresponding to no whole parity relation, which means that their values can be set independently.

est de rang plein, avec m_i,j les coefficients de la matrice génératrice et p₁,p₂,...p_d, l'ensemble des positions des bits dont la valeur est fixée dans la séquence codée.More generally it is possible to impose the value and the position of a set of bits at the output of the encoder if and only if the sub-matrix $$\left[\begin{array}{c}{m}_{}\end{array}\right]$$$$\left[\begin{array}{ccccc}{}_{0,p1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_2}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]$$

is of full rank, with m _{i, j} the coefficients of the generator matrix and p ₁ , p ₂ , ... p _d , the set of positions of the bits whose value is fixed in the coded sequence.

Finally, in the case of a performance code ½, the maximum number of successive bits whose value can be set is equal to the length of the impulse response of the code, ie 2m + 2 where m is the constraint length of the code.

Non-limiting example of a convolutional code punched from a convolutional code of output ½

For punched codes, which have lower redundancy, it is possible to force a larger number of consecutive bits out of the encoder. For example, the code defined by the preceding polynomials (171, 133) may be punched to obtain a 3/4 yield code. The parity relationships of this code have a length of 26 (11111101011011001010011111) and are spaced 4 bits apart. This example is illustrated in figure 8 on which are represented the indices 800 of the bits at the output of the encoder, a portion P ₂₈ of 28 consecutive bits having no relation of complete parity and 3 relations of parities R1, R2, R2 linked to said code, of length equal to 26 bits. Parity relationships are checked for all 26-bit sequences starting on an index shifted by 4 bits for each new sequence.

By direct analogy with the above, it is therefore possible to choose the values taken by a group of 4 (6 + 1) = 28 bits.

General case of usual convolutional codes

For the more general case of a convolutional code of efficiency (n-1) / n, and of constraint length m , the parity relations are generally of length n · m +2 (in the case of the preceding example, we had m = 6 and n = 4 after punching, the parity relations were 26). In this case, and by analogy with the above, it is possible to choose the input bits of the encoder so as to force the value of n · ( m + 1) consecutive bits at the output of the encoder.

It can thus be seen that with convolutional codes, it is possible, as for block codes, to force the value of certain coded bits, possibly consecutive and sometimes in large numbers. The condition for this operation to be possible is that the matrix formed by the columns of the coding matrix corresponding to the forced bits is of full rank.

In particular, it is possible to force the value of consecutive bit sequences of significant length, particularly when the code efficiency is close to 1 and when the memory m of the code is important.

As for block codes, the dependence between the encoder input bit values and the encoder output bits is linear. The values of the bits that must be forced into the encoder input linearly depend on the values of the other encoder input bits and the forced bit values at the encoder output.

Turbo-Codes Product

The invention also applies to turbo-code type correction codes produced.

Turbo-codes are correcting codes that combine at least two simple codes by interleaving the entries so that each of the simple codes sees a different set of information on the one hand, and the information specific to each bit, block or message is spread over his neighbors on the other hand. As a result, even if part of the bits, blocks or messages is corrupted during transmission, the corresponding information still exists more or less on bits, blocks or neighboring messages. The decoding procedure is iterative and collaborative between each simple code. It involves a notion of trust on each bit, block or message decoded and differs the final decision on their values ("soft decision" or "soft decision" in English). Each of the decoders transmits to the others the information resulting from its own decoding (called extrinsic information) which is multiplexed with the input information of the other coders. The bit, block or message thus transmitted is decoded a second time by the other simple coders, and the corresponding information is re-transmitted to the other coders, etc. (hence the name "turbo" which is related to the decoding procedure and not to the code itself).

Simple employable codes are multiple.
It is possible to use convolutional codes. Recursive and systematic convolutional codes are in practice particularly suitable. The codes can be placed in series or in parallel. The clever management of the interleaving and the iterative detection / correction of data by each simple code makes it possible to increase the detector and corrector power of the overall process while limiting the number of iterations and the complexity.

est construit à partir de deux codes élémentaires C ₁ et C ₂ de rendement $\frac{k_1}{n_1}$

et $\frac{k_2}{n_2}\mathrm{.}$

Les codes élémentaires utilisés sont des codes en bloc très simples (typiquement des codes de parité, des codes de Hamming ou bien des codes de Hamming étendus). Les n _1· n ₂ bits successifs apparaissent comme une suite de n ₂ mots de code C ₁, En considérant le train binaire décimé d'un facteur n ₁, on obtient des mots du code C ₂.Another turbo coding structure corresponds to product codes. In the simplest version corresponding to two-dimensional product codes, the product yield code $\frac{k_{}}{}$$\frac{{}_1\cdot {\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="imgf0007.png"\; state="\{\{state\}\}">k</figure-callout>}}_2}{{\mathrm{not}}_1\cdot {\mathrm{not}}_2}$

is constructed from two elementary codes C ₁ and C ₂ of output $\frac{k_{}}{}$$\frac{{}_1}{{\mathrm{not}}_1}$

and $\frac{{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="imgf0007.png"\; state="\{\{state\}\}">k</figure-callout>}}_2}{{\mathrm{not}}_2}\mathrm{.}$

The elementary codes used are very simple block codes (typically parity codes, Hamming codes or extended Hamming codes). The n _{1 ·} n ₂ successive bits appear as a sequence of n ₂ codewords C ₁ , Considering the decimated bitstream by a factor n ₁ , we obtain words of the code C ₂ .

The turbo codes produced, built from several block codes, are like block codes when it comes to determining whether it is possible to generate the desired pattern. Indeed, the encoding operation can be broken down into coding and interleaving operations.

et $\frac{k_2}{n_2}\mathrm{.}$

We will illustrate the decomposition of a code produced into several coding and interleaving operations from a simple and non-limiting example. We consider a product code constructed from two yielding C ₁ and C ₂ codes $\frac{k_1}{{\mathrm{not}}_1}$

and $\frac{{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="imgf0007.png"\; state="\{\{state\}\}">k</figure-callout>}}_2}{{\mathrm{not}}_2}\mathrm{.}$

• Un codage avec le code C ₁ du train binaire : le codage transforme k ₂ groupes de k ₁ bits en k ₂ groupes de n ₁ bits.
• Un entrelacement ligne/colonne simple : les bits sont écrits ligne par ligne dans une matrice de taille k ₂ lignes et n ₁ colonnes. Les bits sont ensuite lus colonnes par colonne.
• Un codage avec le code C ₂ du train binaire : le codage transforme n ₁ groupes de k ₂ bits en n ₁ groupes de n ₂ bits.
• Un entrelacement ligne/colonne simple : les bits sont écrits ligne par ligne dans une matrice de taille n ₁ lignes et n ₂ colonnes. Les bits sont ensuite lus colonnes par colonne.

The operation of coding a k ₁ · k ₂ bit block can be decomposed as follows:

• An encoding with the code C ₁ of the bitstream: the coding transforms k ₂ groups of k ₁ bits into k ₂ groups of n ₁ bits.
• A simple line / column interleaving: the bits are written line by line in a matrix of size k ₂ lines and n ₁ columns. The bits are then read column by column.
• Encoding with the C ₂ code of the bitstream: the coding transforms n ₁ groups of k ₂ bits into n ₁ groups of n ₂ bits.
• A simple row / column interleaving: the bits are written line by line in a matrix of size n ₁ rows and n ₂ columns. The bits are then read column by column.

In practice, if we consider a limited portion of consecutive bits of a block of n ₁ · n ₂ coded bits (a portion of length n.k 'substantially smaller than n ₁ · k ₂ ), the constraints of the code C ₂ do not affect this portion because there is no parity relationship related to the code C ₂ that is contained entirely in this portion of bits. Consequently, if we consider a portion of consecutive bits smaller than n ₁ · k ₂ , everything happens as if there was only the code C ₁ when it comes to determining the reasons that it is possible to force. Like block codes, it is therefore possible, in particular, to generate consecutive bit patterns of size 2 · k ₁ .

Low Density Parity Check (LDPC) Codes

LDPC codes are specific block codes that are constructed in such a way that the parity bits are computed using a low weight parity relationship. This is in practice systematic (but not cyclic) block codes and the analysis made on block codes applies by analogy to the description made previously.

LDPC codes are usually very large. As has been established for block codes, the LPDC codes thus make it possible, in particular, to generate selected patterns with series of consecutive bits of great length.

est de rang plein, avec m_i,j des coefficients de la matrice génératrice et p₁,p₂,...p_d, l'ensemble des positions des bits dont la valeur est fixée dans la séquence codée. Une matrice de rang plein est une matrice dont toutes les colonnes sont indépendantes. Si cela est le cas, il suffit de résoudre le système d'équations $$\left[\begin{array}{ccc}{i}_0& \mathrm{...}& i_{k-1}\end{array}\right]=\left[\begin{array}{ccc}{c}_{p_1}& \mathrm{...}& c_{p_d}\end{array}\right]\cdot {\left[\begin{array}{ccccc}{m}_{0,p1}& m_{0,p_2}& m_{0,p_3}& \mathrm{...}& m_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,p_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]}^{-1}$$

où [C_P1...Cp_d] sont les bits ou symboles dont la valeur est fixée dans la séquence codée et i₁,...i_k sont les inconnues du système à fournir en entrée du codeur.In summary, for any correction code for which the coding operation can be performed by multiplying the information sequence by a generator matrix to obtain the coded sequence, it is possible to set the value and the position of a set of bits. of the coded sequence by imposing a particular input binary sequence. However, this possibility only exists if the sub-matrix of the generator matrix defined by $$\left[\begin{array}{ccccc}{\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_2}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]$$

is of full rank, with m _{i, j} coefficients of the generator matrix and p ₁ , p ₂ , ... p _d , the set of positions of the bits whose value is fixed in the coded sequence. A matrix of full rank is a matrix of which all the columns are independent. If this is the case, just solve the system of equations $$\left[\begin{array}{ccc}{i}_0& \mathrm{...}& i_{k-1}\end{array}\right]=\left[\begin{array}{ccc}{\mathrm{vs}}_{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="imgf0003.png,imgf0004.png"\; state="\{\{state\}\}">p</figure-callout>}}_1}& \mathrm{...}& {\mathrm{vs}}_{p_d}\end{array}\right]\cdot {\left[\begin{array}{ccccc}{\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p1}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_2}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& {\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="imgf0005.png,imgf0006.png"\; state="\{\{state\}\}">m</figure-callout>}}_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,{\mathrm{<figure-callout\; id="3"\; label="p"\; filenames="imgf0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]}^{-1}$$

where [C _P1 ... Cp _d ] are the bits or symbols whose value is fixed in the coded sequence and i ₁ , ... i _k are the unknowns of the system to be inputted to the encoder.

The transmission channel 400 may also include a scrambling module 403, also called brewing.

The brewing, or scrambling, is used to make the binary sequence to emit as random as possible, in order to improve the symbol synchronization but also to contribute to the protection of the contents of the brewed messages. Its purpose is to remove long sequences of bits equal to 0 or 1 that prevent a correct recovery of the symbol rate. There are several types of brewers including synchronous brewers requiring a prior time reference or self-synchronizing brewers.

This transformation is invertible, the scrambling operation consists in transforming a group of L bits into another group of L bits and the operation of inverting the transformation of the bitstream is an operation performed by a receiver. Thus, the reverse transfer function of a brewer or scrambler is easily deductible from its direct transfer function.

Case of a synchronous scrambler

In the case of a synchronous scrambler, a pseudo-random sequence is added modulo 2 to the binary signal to be scrambled. The binary series {..., e _k , e _{k + 1} , ...} representing the scrambling sequence is periodic, with a long period L. The most common sequences used for scrambling are sequences of maximum length, constructed from a shift register. These sequences are generated by a shift register looped according to a primitive polynomial E (X) = 1 + c ₁ X + ... + c _P X ^P of degree P. We obtain a sequence of period L = 2 ^P -1. However, the sequences used for scrambling can be truncated. The k-th output e _k of the shift register satisfies the recursion relation e _k = c _1. e _k-1 + ... + c _P. e _kP , with c ₁ , ..., c _P constant coefficients in the Galois GF2 body independent of input data and scrambled data, "+" always denotes the modulo 2 addition in GF2. For an input binary series denoted {..., b _k , b _{k + 1} , ...}, the transformation F operated by a synchronous scrambler can be written F ({..., b _k , b _{k + 1,} ...}) = {..., b _'k, b' _{k + 1,} ...} with b _'k = b _k + e _k. The transformation F is perfectly invertible. Indeed, this transformation F is equal to its inverse F ^-1 = F since b _k = b ' _k + e _k and knowing that e _k + e _k = 0 in the Galois field GF2. The operation F consists of a new addition modulo 2 of the value of the bits scrambled by the outputs of the same shift register as the transmission to produce a descrambled sequence of identical length. In order to be able to force the bitstream out of a synchronous scrambler, it is enough to be correctly synchronized with the scrambling operation. In other words, the positions of the indices k or beginning of period must coincide before applying the transformation F ^-1 = F to the scrambled bits. In the case of a synchronous scrambler, the dependence between the value i of an input bit of the scrambler and the c value of the output bit of the scrambler is affine. Depending on the position of the bit considered, the dependence is either c = i or c = i + 1.

Case of a self-synchronizing scrambler

In the case of a self-synchronizing scrambler, the states of the register are filled with a finite number of scrambled data. The output of the register is added modulo 2 to the input data bit to form the new scrambled bit.

The transformation F, performed by a self-synchronizing scrambler, is defined by a primitive polynomial shift register E (X) = 1 + c _1. X + ... + c _P. X ^P of degree P of period L = 2 ^P -1 and is written for an input binary series denoted {..., b _k , b _{k + 1} , ...} in the form: F ( {..., b _k , b _{k + 1} , ...}) = {..., b ' _k , b' _{k + 1} , ...} with b ' _k = b _k + c _1. b ' _k-1 + ... + c _P. b' _kP '+' always denotes modulo 2 addition in GF2). This makes it possible to perform descrambling on reception in a simple manner and without having to synchronize beforehand. In reception, the scrambled bits b ' _k-1 ,..., B' _kP are injected in the same register as on transmission in order to reconstitute the output b _k = b ' _k + c ₁ . b ' _k-1 + ... + c _P. b' _kP .

The difficulty in forcing the output bits here arises from the fact that the expression of the register states as a function of the input data b _k (non-scrambled data) involves an unlimited number of said input data. In other words, all the inputs b _k since the startup of the scrambler are involved in the value of the states of the register.

In order to force the value of the scrambled data it is essential to have synchronous access to the scrambled data in order to adapt the input data dynamically. This condition is necessary for the application of the invention if the transmission chain comprises a self-synchronizing scrambler.

The transmission channel 400 may also include an interleaving module 404.

Interleaving is widely used on transmission channels where the occurrences of errors are grouped into packets. Its function is to distribute these errors as uniformly as possible. In reception, the errors are, after deinterleaving, placed in such a way that they impact different codewords. These errors can then be considered as decorrelated, and the correcting power of the decoders makes it possible to minimize their impact. Interleaving also appears as a means of introducing time diversity into the transmission chain and thereby helps to protect it from fading, interference and potential interference. Many interleavers are constituted by a table, the input bits are then arranged by rows in the table, and the output bits are produced by reading in a column of the table.
The transformation performed by an interleaver is also an invertible operation. Its inverse transfer function is deductible from its direct transfer function. Indeed, it is a transformation that transforms a block of L bits into another block of L bits, simply by swapping the order of the bits. In order to obtain a desired block of bits after interleaving B '= b' _k , ... b ' _{k + L-1} , it suffices to be synchronized on the block and to apply on this bit stream B' the permutation inverse, which corresponds to the de-interleaving operation performed conventionally by a receiver. We then obtain a block of bits B = b _k , ... b _{k + L-1} , which once interleaved, is strictly equal to bit stream B.

The transmission channel 400 may also include a framing module 405. The framing 405 enables the receiver to synchronize itself on the transformations of the bitstream such as the interleaving or decoding operations, and then to retrieve structured data. in the form of a multiplexing of several streams or data in the form of words or bytes. For this, once the structured data in the form of frames corresponding to periodic scheduling reasons, the synchronization of the receiver on the frames is carried out using synchronous periodic patterns of the frames. Each frame is thus preceded, and / or followed, and / or contains a specific synchronization word used to synchronize the receiver on the received frames. Several frames can also be grouped to form a multi-frame or a hyper-frame. The synchronization patterns used for the framing are repeated in the transmitted sequence and can be detected and scrambled as previously explained.

The framing limits the possibility of forcing the desired modulated signal since some bits take values imposed at regular intervals, and that it is necessary to keep these bits for the proper functioning of the receiver in connection with the transmitter. This transformation is therefore not surjective for data blocks whose output size exceeds that of a block of useful data per frame.
However, the framing occupies only a very limited (and temporally well-defined) part of the total bit rate (example: start frame pattern using only a few symbols, etc.) and does not prevent generating the desired coded signal within a frame.

This point is not a particular pitfall for the implementation of the invention.

The transmission channel 400 may also include a binary signal coding module 406.

Binary signal coding is used to adapt the signal to the transmission channel. It transforms the digital message into a baseband electrical signal or a low frequency signal. There are two major classes of signal binary codes, NRZ (Non-Reset) transcoding codes and alphabetic codes.

The transformation carried out by a signal binary coder is an invertible operation. Its inverse transfer function is therefore deductible from its direct transfer function.

Finally, the transmission channel 400 comprises a modulator 407 that transforms the binary sequence into a sequence of modulated symbols. Symbols are taken from a complex set called constellation. A symbol can group several bits. For example, digital phase or PSK (Phase Shift Keying) modulations or digital amplitude modulation or QAM (Quadrature Amplitude Modulation) modulations may be mentioned.

The transformation operated by a modulator is an invertible operation. Its inverse transfer function is therefore deductible from its direct transfer function.

From the foregoing, the transformations applied in the transmission channel on the bit stream are reversible, that is to say that it is possible from the output bit stream to recover the input bitstream. In practice, redundancy is even added so as to be able to recover the original binary signal in the presence of errors on the coded bitstream.

However, still according to the above, certain functions implemented by the transmission channel of a communications system may not always be surjective or invertible. It may happen that a TBC encoded bitstream that we would like to force at the module output does not correspond to any "useful" TBU bits at the module input. This is the case in particular of a block or convolutional corrective coding function that does not comply with the criteria previously mentioned or any other non-bijective coding operation. In such a case, it is not possible to determine the inverse transfer function F ^-1 of the overall transmission chain.

To circumvent this difficulty, two embodiments of the invention are envisaged.

A first variant consists in searching among the set F ({TBU}) of modulated sequences that can be obtained at the output of the transmission channel from the set {TBU} of the possible input bit sequences of the transmission channel, the binary sequence T 'which minimizes the distance between the modulated transformation at the output F (T') of the sequence T 'and the desired modulated sequence D which contains at least one dummy synchronization pattern positioned at the desired location. The distance considered can, for example, be a distance in the least squares sense calculated by integrating the difference between a sequence possible F (T), T belonging to the set {TBU}, and the desired sequence D over a fixed time interval. A possible criterion can be calculated using the following relation: $$\forall T\in \left\{\mathit{TBU}\right\};\mathrm{VS}\left(T,D\right)={\Vert F\left(T\right)-D\Vert }_{{\mathrm{The}}^2}=\int {\left|F\left(T\right)\left(t\right)-\mathrm{<figure-callout\; id="2"\; label="D\; t"\; filenames="imgf0007.png"\; state="\{\{state\}\}">D\; </figure-callout>}\left(t\right)\left(\right)\right|}^2\mathit{dt}$$

We then search for the input sequence T '∈ {TBU} of the transmission chain which minimizes the criterion C: $$\mathrm{T}\text{'}=\underset{T\in \left\{\mathit{TBU}\right\}}{\mathrm{argmin}}\left[\mathrm{VS}\left(T,D\right)\right]$$

However, the practical implementation of this variant must take into account two main constraints.

On the one hand, for reasons of complexity, it is not practically possible to obtain the F {TBU} image of the modulated signals at the output of the transmission channel corresponding to all of the useful bitstreams. possible (in other words, corresponding to the entirety of the {TBU} set), but only a small subset of this image.

On the other hand, it is possible to simplify the implementation of the invention based on the temporal supports mainly related to interleaving, coding and framing operations. Indeed, it is not useful in practice for the implementation of the invention to consider binary streams T useful in the set {TBU} whose modulated signals F (T) output (after coding and interlace including ) would be scattered over too long time intervals, or too many outgoing frames, or whose distribution of symbol positions would be too small.

In practice therefore, this variant of the invention can be implemented by restricting the set {TBU} to a subset {TBU '} which comprises only useful bit sequences T whose lengths and positions after passing through the transmission chain (and in particular after passing through the coding and interleaving modules) correspond to dummy SYNC ' _{F units} , if necessary suboptimal with respect to the interference of the communication network, but compatible with the setting standard implemented telecommunication system in terms of positions, recurrence and frame periodicity, and therefore easy to generate and insert in the frames of useful data.

The time / frequency structure and / or the choice of the positions, lengths and recurrences of the dummy signals SYNC ' _F approaching, in the sense of the criteria mentioned above, the dummy patterns SYNC _F desired at the output, are fixed based on the frame periodicities.

The restricted set {TBU '} is then pre-determined by inverting, for the SYNC' _{F units} , analytically or by simulation, the modules of the transmission chain and in particular the interleaving modules and the coding modules.

This makes it possible in particular to simplify the implementation of the invention by concentrating the search for the binary sequences T in the inverse image (in particular by the coding and interleaving transformations) of a restricted set of fake patterns SYNC ' _F in output, approaching the desired sequence SYNC _F in the sense of the criterion mentioned above, and corresponding at most to the duration of a frame at the output of the transmission chain (and / or to the duration of a useful information frame in input of said transmission channel). The bit sequences T 'thus obtained are periodized by useful information frame to generate, at the output, also periodic and indexed patterns indexed on that of the frame of the output signal.

The calculation of the bit positions in the bit sequence T 'to obtain a dummy pattern at the output of the transmission channel can then be achieved once and for all.

If one constructs the binary sequence T 'in a completely artificial way by exploiting a mode of messaging which authorizes a complete programming of the content of the messages, the calculation of the bit values of the binary sequence T 'can also be achieved once and for all.

If one constructs the binary sequence T 'from an application of audio or video encoder type producing a variable and random content, the calculation of (deterministic) relations giving the values of the bits of the binary sequence T' (in function the desired SYNC ' _F dummy pattern and neighboring information bits) can also be realized once and for all.

• les positions que prennent ces bits factices forcés sont déterminées en partant de la position et des valeurs des séquences factices SYNC'_F et en remontant les transformations du train binaire une par une,
• les valeurs que prennent ces bits factices ou les relations donnant les valeurs des bits factices selon les bits d'information voisins sont déterminées elles-aussi en remontant les transformations du train binaire une par une.

In practice, in order to generate said binary sequences T, the value of certain useful bits, called dummy bits (situated at the input of the channel coding) must therefore be forced to precise positions. The transformation applied consists in first determining a partitioning the useful data frame by inverting the interleaving coding modules: this determines precise positions, on which the values of the dummy bits are artificially chosen so as to generate the dummy sequences after interleaving and coding. Finally, in this simplified variant of implementation of the invention,

• the positions taken by these forced dummy bits are determined starting from the position and the values of the dummy sequences SYNC ' _F and by going up the transformations of the bit stream one by one,
• the values taken by these dummy bits or the relations giving the values of the dummy bits according to the neighboring information bits are also determined by going up the transformations of the bit stream one by one.

If all the stages of the transmission chain are concerned, the key steps concern the inversion of the interlace and corrector coding operations.

Remaining at the scale of a signal frame at the output of the transmission chain, the positions, values or relations giving the values of the dummy bits in the useful information flow are fixed. They can be calculated once and for all and then applied to each successive frame.

A second embodiment of the invention consists in applying the invention to a subset located downstream of the transmission chain consisting of blocks in series whose transfer functions are all invertible. In practice, the portion of maximum length of the transmission chain for which the inversion of the bit stream can be satisfactorily realized is identified. For this we go back from the modulator output signal to the sequence of useful data to be transmitted. The bitstream intended to produce modulated signals D (t), containing a dummy synchronization sequence, is injected only at the input of this subset, ie at the output of the first noninvertible function of the transmission chain in the inverse order of the transmission functions (from the modulator - end of the chain - to the correction coder - start of the chain). This second variant of the invention is for example applied if the transmission chain comprises an encryption device or cryptography whose function has by nature a non-determinable inverse.

The method according to the invention can be implemented from software elements. Such software can be executed by the sending equipment so as to modify the useful binary sequence to be transmitted, which is for example produced by an application. It can also be executed by a computer connected to said transmitter for the purpose of setting it.

The method according to the invention may be available as a computer program product on a computer readable medium. The support can be electronic, magnetic, optical, electromagnetic or a support infra-red diffusion type. Such supports are, for example, Random Access Memory RAMs (ROMs), magnetic or optical tapes, disks or disks (Compact Disk - Read Only Memory (CD-ROM), Compact Disk - Read / Write (CD-R / W) and DVD).

Claims (19)

1. A method for jamming a communication system (EM, REC) involving generating at least one dummy synchronisation sequence (SYNC_F) in a signal (S) intended to be transmitted by at least one transmitter (EM_B1, EM_B2,..., EM_B3) compatible with said communication system (EM, REC), said signal (S) comprising data (D_U,T) generated by an application and intended to be transmitted to a receiver, said method comprising the following steps:

   - defining said dummy synchronisation sequence (SYNC_F) and its time and/or frequency position within said signal (S) to be transmitted;

   - estimating the value and the position of the dummy bits (B_F) to be inserted into the sequence of data (D_U,T) to be transmitted at the input of the transmission chain or of a sub-part of the transmission chain so as to obtain, in the sequence produced at the output of said transmission chain, the predefined value and time position of the symbols of said dummy synchronisation sequence (SYNC_F);

   - inserting said dummy bits (B_F) into said sequence of data (D_U,T) at the obtained positions.
2. The jamming method according to claim 1, wherein, when the transfer function F of said transmission chain is reversible, the value and the position of said dummy bits (B_F) are estimated by determining the reverse transfer function F^-1 of said transfer function F and by applying said reverse transfer function F^-1 to said dummy synchronisation sequence (SYNC_F).
3. The jamming method according to claim 2, wherein said reverse transfer function F^-1 of said transmission chain is determined by forming, in reverse order, the composition of the reverse transfer functions of the various blocks forming said chain.
4. The jamming method according to claim 3, wherein said transmission chain comprises at least one k/n capacity correcting code (402), the transfer function of which is reversed by resolving the following system of equations: $\left[\begin{array}{ccc}{i}_0& \dots & i_{k-1}\end{array}\right]=\left[\begin{array}{ccc}{c}_{p_1}& \dots & c_{p_d}\end{array}\right]{\left[\begin{array}{ccccc}{m}_{0,p_1}& m_{0,p_2}& m_{0,p_3}& \cdots & m_{0,p_d}\\ \cdots & \cdots & \cdots & \cdots & \cdots \\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,p_3}& \cdots & m_{k-1,p_d}\end{array}\right]}^{-1},$

   

   where [CP1...CPd] are the symbols, the value of which is fixed in the coded sequence, [i_o,...i_k-1] is the sequence to be produced at the input of said code and m_i,pj are the coefficients of the generator matrix of said code, with p₁, p₂,...p_d being all of the positions of the symbols, the value of which is fixed in the coded sequence, with d being an integer that is at most equal to the number n of symbols of the coded sequence.
5. The jamming method according to claim 4, wherein said correcting code is a linear block code or a convolutional code or a turbo code or a low-density parity-check code (LDPC).
6. The jamming method according to any one of claims 3 to 5, wherein said transmission chain further comprises a jammer (403) and/or an interleaver (404) and/or a $$\left[\begin{array}{ccc}{i}_0& \mathrm{...}& i_{k-1}\end{array}\right]=\left[\begin{array}{ccc}{c}_{p_1}& \mathrm{...}& c_{p_d}\end{array}\right]\cdot {\left[\begin{array}{ccccc}{m}_{0,p_1}& m_{0,p_2}& m_{0,p_3}& \mathrm{...}& m_{0,p_d}\\ \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}& \mathrm{...}\\ m_{k-1,p_1}& m_{k-1,p_2}& m_{k-1,p_3}& \mathrm{...}& m_{k-1,p_d}\end{array}\right]}^{-1},$$

   

   framing module (405) and/or a signal binary encoder (406) and/or a modulator (407).
7. The jamming method according to claim 1, wherein, when said transfer function F of said transmission chain is non-surjective, the value and the position of the dummy bits are estimated by seeking the input sequence T' of said transmission chain that minimises a distance criterion between the sequence F(T')(t) obtained at the output of said transmission chain when said sequence T' is effectively produced at its input and said dummy synchronisation sequence (SYNC_F).
8. The jamming method according to claim 7, wherein said distance criterion is taken as being equal to the integral, over a given duration, of the square norm of the difference between said sequence F(T')(t) obtained at the output of said transmission chain and said dummy synchronisation sequence (SYNC_F).
9. The jamming method according to any one of claims 7 to 8, wherein seeking the input sequence T' of said transmission chain that minimises said distance criterion is carried out on a sub-set of the set of possible binary sequences at the input of said transmission chain.
10. The jamming method according to any one of the preceding claims, wherein said sequence of data (D_U,T) is produced by an application (401), from among an audio, image or video encoder.
11. The jamming method according to claim 1, wherein, when said transfer function F of said transmission chain is non-surjective, said dummy bits (B_F) are inserted into the sequence produced at the input of a sub-part of said transmission chain, the transfer function of which is surjective and the output of which is common to the output of said transmission chain.
12. The jamming method according to claim 11, wherein said transmission chain comprises an encryption device and said sub-part of said transmission chain excludes said device.
13. The jamming method according to any one of the preceding claims, wherein the values of the symbols of said dummy synchronisation sequence (SYNC_F) are identical to those of the symbols of a synchronisation sequence (SYNC) that comprises said signal for synchronising together a compatible receiver and transmitter of said communication system.
14. The jamming method according to any one of the preceding claims, wherein the time and/or frequency position of the symbols of said dummy synchronisation sequence (SYNC_F) are different to those of the symbols of a synchronisation sequence (SYNC) that comprises said signal for synchronising together a compatible receiver and transmitter of said communication system.
15. A device (EM_B1, EM_B2,..., EM_B3) for transmitting a signal, comprising a transmission chain for converting a sequence of data (D_U,T) to be transmitted into a signal (S) to be transmitted and a means adapted to implement the steps of the method according to any one of claims 1 to 14.
16. A cooperative jamming system comprising a plurality of transmission devices (EM_B1, EM_B2,..., EM_B3) according to claim 15 and for which the time and/or frequency positions of said dummy synchronisation sequences (SYNC_F) inserted into the signal transmitted by each transmission device are different from each other.
17. The cooperative jamming system comprising a plurality of transmission devices (EM_B1, EM_B2,..., EM_B3) according to claim 15 and for which each of said transmission devices (EM_B1, EM_B2,..., EM_B3) transmits a signal (S) comprising a plurality of dummy synchronisation sequences (SYNC_F), the values and/or time positions and/or frequency positions of which are different from each other.
18. A computer program comprising instructions for executing the steps of the method according to any one of claims 1 to 14, when said program is executed by a processor.
19. A processor-readable recording medium which stores a program comprising instructions for executing the steps of the method according to any one of claims 1 to 14 when said program is executed by a processor.

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