EP2613342A2 - Method for manufacturing a double-gate non-volatile memory cell - Google Patents

Abstract

The invention relates to a method for manufacturing a double-gate non-volatile memory cell (100), in which the steps of: a) at least partially forming the gate (130) of the control transistor comprising obtaining a relief (132) of a semiconductor material on a substrate (160, 162); b) forming the control gate (140) of the storage transistor, comprising the steps of: forming on at least one flank of the relief (132) a semiconductor material configured to store electrical charges; depositing a first layer (210) so as to cover the stack of layers (143); etching the first layer (210) so as to form a first pattern (144) juxtaposed to the relief (132); c) forming a second layer (220) on the first pattern (144), d) etching the second layer (220) so as to form on the first pattern (144) a second pattern (146) having a substantially planar upper face (145).

Description

TECHNICAL FIELD OF THE INVENTION

The invention relates to the field of non-volatile memory devices or electronic memories. It finds for particularly advantageous application the field of dual-gate Flash type electronic memories comprising a control gate, also designated gate of the control transistor, and a storage gate, also designated control gate of the storage transistor.

STATE OF THE ART

• les EPROMs, de l'anglais « Erasable Programmable Read Only Memories » c'est-à-dire « mémoires mortes (à lecture seule) effaçables et programmables » dont le contenu peut être écrit électriquement, mais qui doivent être soumises à un rayonnement ultra violet (UV) pour effacer les informations qui y sont mémorisées.
• les EEPROMs, de l'anglais « Electrically Erasable Programmable ROMs » c'est-à-dire « mémoires mortes effaçables et programmables électriquement » dont le contenu peut donc être écrit et effacé électriquement, mais qui requièrent pour leur réalisation des surfaces de semi-conducteur plus importantes que les mémoires de type EPROM, et qui sont donc plus coûteuses à réaliser.
• les mémoires Flash. Ces mémoires non volatiles ne présentent pas les inconvénients des mémoires EPROMs ou EEPROMs mentionnés ci-dessus. En effet, une mémoire Flash est formée d'une pluralité de cellules mémoires pouvant être programmées électriquement de manière individuelle, un grand nombre de cellules, appelé bloc, secteur ou page, pouvant être effacées simultanément et électriquement. Les mémoires Flash combinent à la fois l'avantage des mémoires EPROMs en terme de densité d'intégration et l'avantage des mémoires EEPROMs en terme d'effacement électrique.

There are several types of nonvolatile memories, that is to say memories retaining information stored in the absence of power supply, and can be written and / or erased electrically:

• EPROMs, "Erasable Programmable Read Only Memories" ie "erasable and programmable read-only memories" whose content can be written electrically, but which must be subjected to ultra-violet radiation. purple (UV) to erase the information stored in it.
• the EEPROMs, from the English "Electrically Erasable Programmable ROMs" ie "erasable and electrically programmable read-only memories" whose content can therefore be written and electrically erased, but which require for their realization semicircular surfaces conduct larger than the EPROM type memories, and are therefore more expensive to achieve.
• Flash memories. These nonvolatile memories do not have the drawbacks of the EPROMs or EEPROMs mentioned above. Indeed, a flash memory is formed of a plurality of memory cells can be individually electrically programmed, a large number of cells, called block, sector or page, can be erased simultaneously and electrically. Flash memories combine both the advantage of EPROMs in terms of integration density and the advantage of EEPROMs in terms of electrical erasure.

In addition, the durability and low power consumption of Flash memories make them interesting for many applications: digital cameras, cell phones, printers, PDAs, laptops, or portable devices for reading and sound recording, including so-called USB keys, which are able to connect directly to a "universal serial bus" become a standard of the microphone computing, and many other applications. Flash memories do not have mechanical elements, which gives them a good resistance to shocks.

Most Flash memories are of the "stand-alone" type, that is to say that they are autonomous devices with large storage capacities, generally greater than 1 gigabit or Gb (1Gb = 10 ⁹ bits) , and which are dedicated to mass storage applications.

There are also so-called on-board Flash memories whose realization is integrated with that of a process, for example the so-called CMOS, acronym of the complementary metal oxide semiconductor, the technological process most widely used by the industry. microelectronics for the realization of integrated circuits based on "complementary" transistors (C) of "metal-oxide-semiconductor" (MOS) type. These memories are of growing interest, for example in the automotive or microcontroller fields, for storing data or codes. These embedded flash memories are made on a chip which also includes CMOS circuits intended to perform logical functions other than data storage. These embedded flash memories are generally made for storage capacities lower than those of "stand-alone" type memories, their capacity generally ranging from a few bits to a few megabits or Mb (1 Mb = 10 ⁶ bits). The target characteristics of the on-board flash memories are a low production cost, excellent reliability (especially at high temperature), low power consumption, or a high programming speed, these characteristics being a function of the application for which they are intended. .

Most Flash memory points have a structure of MOS transistor type comprising three electrodes: source, drain and gate, the latter for creating a conduction channel between source and drain. Their particularity to allow the nonvolatile storage of information is they further comprise an electric charge storage site, called floating gate, formed for example of a polycrystalline silicon layer disposed between two oxide layers, placed between the electrically conductive gate material and the transistor channel. The storage is obtained by applying to the conductive material a voltage greater than the threshold voltage, for example between 15 volts and 20 volts, so as to store the information in the form of charges trapped by the floating gate.

However, such memories have drawbacks limiting the reduction of their dimensions. Indeed, a reduction in the thickness of the tunnel oxide which is arranged between the channel and the polycrystalline silicon layer constituting the floating gate, leads to an increase in SILC, the acronym for "stress induced leakage current" designating the "Leakage current induced by the voltage". The prolonged use of such a memory, that is to say the repetition of write and erase cycles, generates in the long run defects in the tunnel oxide which tend to evacuate the charges trapped in the gate floating. Similarly, a high SILC or leakage current affects the retention time of the charges in the floating gate. In practice, it is therefore difficult to reduce the thickness of the tunnel oxide of these memories to less than 8 nanometers or nm (1 nm = 10 ^-9 meters) without the SILC becoming a critical phenomenon for storage. In addition, by reducing the dimensions of such a memory cell, parasitic coupling between the floating gates of two adjacent cells of the same memory becomes important and can therefore degrade the reliability of the memory.

For these reasons, MONOS type memories (Metal Oxide Nitride Oxide Silicon), also called NROM memories, have been proposed to replace the polycrystalline silicon floating gate memories. The document US 5,768,192 describes such memories in which the electric charges are stored in traps formed in a floating gate composed of nitride and disposed between two oxide layers. In such a nitride layer, the traps are isolated from each other. Thus, an electron stored in one of the traps remains physically located in this trap, which makes these memories much less sensitive to defects in the tunnel oxide, and therefore less impacted by an increase in SILC. Indeed, in the presence of a in the tunnel oxide, the storage layer, that is to say the nitride layer, loses only the electrons located in the vicinity of the defect, the other electrons trapped are not affected by this defect. These memories therefore have better reliability. It is thus possible to have a tunnel oxide with a thickness less than approximately 8 nm, and thus to reduce the programming voltages required. In addition, because of the small thickness of the nitride to form the storage layer, the coupling between two adjacent memory cells is greatly reduced compared to polycrystalline silicon floating gate cells. Finally, the structure of a NROM-type memory is also suitable for making on-board memories because of the simplicity of the method of integration of these memories.

The document S. Kianian and coauthors "A novel 3 volt-only, small area erase, high density E2PROM flash," Technical Digest of VLSI Technology, 1994, p.71 " , describes another type of memory, called "split-gate" memory, that is to say "shared grid" memory which combines within the same memory cell a storage transistor and a selection transistor (or control transistor) formed on a single active area. Such a double-gate memory cell is generally programmed by carrier injection by the source, a mechanism which requires the presence of a selection transistor coupled to the storage transistor, and which makes it possible to increase the programming speed while reducing the consumption. compared to a NROM type memory.

In order to benefit from the advantages of each of the above structures, ie: split-gate and NROM, the document US 2004/207025 proposes another type of double grid memory combining the two structures. One of the difficulties in producing these memories then concerns the control of the relative position of the gates, that is to say the position of the gate of the control transistor relative to the position of the control gate of the storage transistor. Indeed, these grids are made by two successive photolithographies, the misalignment of the second gate with respect to the first gate fixing the length of the second gate. A poor control of the relative positions of the two grids thus results in a poor control of the electrical characteristics of the second transistor, and therefore bad memory performance. Therefore, a very precise control of the position of the grids is necessary when performing this type of memory.

In order to overcome this alignment constraint, the document US 7,130,223 proposes also to realize a double grid memory combining the structure of a memory NROM type with a split-gate architecture. However, the control gate of the storage transistor is in this case made in the form of a lateral spacer of the gate of the control transistor, which is arranged against one of the two lateral flanks of the gate of the control transistor. Such a structure makes it possible to precisely control the position and the dimension of the control gate of the storage transistor relative to the gate of the control transistor. Indeed, the control gate of the storage transistor being made in the form of a lateral spacer of the gate of the control transistor it is then self-aligned on the latter.

However, with such a structure, it is very difficult to then perform a resumption of electrical contact on the control gate of the storage transistor given the small dimensions of this grid in the form of lateral spacer. This problem is illustrated on the figure 1 . The figure 1a shows a sectional view of an example of such a double grid memory cell. Between the source areas 110 and 120 drain the two grids shared by the same cell are available. As mentioned above, the control gate 140 of the storage transistor is made on the source side 110 in the form of a spacer of the gate 130 of the control transistor and is therefore self-aligned thereon. The gate 130 of the control transistor, which is comparable to that of a simple MOS type transistor, can be realized in a conventional manner by various means and methods known to those skilled in the art. On the figure 1a it can be seen that the surface 141, which makes it possible to establish electrical contact with the control gate 140 of the storage transistor, is particularly limited in the case of a triangular shaped spacer. The form which results most naturally from the formation of the spacer with the means and processes known to those skilled in the art. The contact surface 141 corresponds to the silicidation of the underlying material which is polycrystalline silicon 142 and which constitutes, by volume, the bulk of the transistor of storage. Storage is typically achieved using a stack or layer sandwich 143 containing an electric charge trapping layer. This trapping layer constitutes the floating gate which serves to trap the charges storing the state of the memory cell in the control gate of the storage transistor as previously described.

The figure 1b shows a sectional view of another example of such a double-gate memory cell where the contact surface 141 of the control gate of the storage transistor is enlarged by striving to obtain the most rounded possible shape of the spacer. This type of shape is however difficult to obtain with polycrystalline silicon 142, which material constitutes the bulk of the control gate of the storage transistor.

The resumption of contact on the control gate of the storage transistor is very difficult to implement in the context of an industrial process and particularly requires very restrictive positioning specifications for vias connections, especially those connection of the control gate of the storage transistor, are always well positioned. A fault of positioning of the vias would prevent the operation of the cell and could in particular create a short circuit between gate of the control transistor and control gate of the storage transistor.

An object of the present invention is therefore to provide a new memory cell structure or a new method for facilitating the resumption of contact of each of the grids and to limit the risk of short circuit.

Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated.

SUMMARY OF THE INVENTION

• ○ formation au moins partielle de la grille du transistor de commande comprenant l'obtention d'un relief en un matériau semi conducteur sur un substrat;
• ○ formation de la grille de contrôle du transistor de mémorisation. La formation de la grille de contrôle comprend de préférence les étapes de: formation sur au moins un flanc du relief en un matériau semi conducteur et au moins une partie du substrat d'un empilement de couches configuré pour stocker des charges électriques; dépôt d'une première couche d'un matériau de préférence semi conducteur de manière à recouvrir l'empilement de couches au moins; gravure de la première couche de manière à former un premier motif de préférence juxtaposé au relief en un matériau semi conducteur de la grille du transistor de commande.

De préférence, la formation de la grille de contrôle du transistor de mémorisation comprend en outre les étapes suivantes de: formation d'une deuxième couche, de préférence en un matériau semi conducteur, au moins sur le premier motif ; gravure de la deuxième couche de sorte à former sur le premier motif un deuxième motif présentant une face supérieure sensiblement plane. Avantageusement, cette surface est adaptée pour permettre une reprise de contact sur la grille de contrôle du transistor de mémorisation.To achieve this objective, one aspect of the present invention relates to a method for manufacturing a double-gate non-volatile memory cell comprising a control transistor comprising a gate and a transistor. storage device comprising a control gate adjacent to the gate of the control transistor, in which the steps of:

• ○ at least partial formation of the gate of the control transistor comprising obtaining a relief of a semiconductor material on a substrate;
• ○ formation of the control gate of the storage transistor. The formation of the control gate preferably comprises the steps of: forming on at least one flank of the relief a semiconductor material and at least a portion of the substrate of a stack of layers configured to store electrical charges; depositing a first layer of a preferably semiconductor material so as to cover at least the layer stack; etching the first layer so as to form a first pattern preferably juxtaposed to the relief in a semiconductor material of the gate of the control transistor.

Preferably, the formation of the control gate of the storage transistor further comprises the following steps of: forming a second layer, preferably a semiconductor material, at least on the first pattern; etching the second layer so as to form on the first pattern a second pattern having a substantially planar upper face. Advantageously, this surface is adapted to allow a resumption of contact on the control gate of the storage transistor.

The contact surface of the control gate of the storage transistor is therefore significantly extended. The positioning of the contact grid with respect to a connection via the upper wiring layers is thus facilitated. In addition, the risks of misplacement and the risks of short circuit between the grids are reduced.

Moreover, the volume of material accessible and available thereafter for siliciding is also increased which improves the electrical connection between the gate of the control transistor and the wiring layers.

• Le premier motif est situé sur le flanc du relief de la grille du transistor de commande et sur l'empilement de couches.
• Le premier motif présente une section sensiblement triangulaire. Alternativement, il présente une portion supérieure sensiblement arrondie. Le deuxième motif prolonge alors cette portion supérieure pour former une face sensiblement plane.
• Le relief en un matériau semi conducteur constitue la grille du transistor de commande. Il forme une ligne ou un rectangle. Si les flancs du relief en un matériau semi conducteur sont sensiblement perpendiculaires au substrat, alors le premier motif présente une section en forme de triangle rectangle dont les deux cotés opposés à l'hypoténuse sont respectivement tournés vers la grille du transistor de commande et vers le caisson d'isolement.
• Le deuxième motif présente une forme sensiblement parallélépipédique, un coté du parallélépipède formant la face supérieure sensiblement plane. La face est la face la plus éloignée du substrat.
• Les sections des premier et deuxième motifs sont prises selon un plan sensiblement perpendiculaire à la surface du substrat portant la cellule mémoire (ou surface sur laquelle est disposée la grille du transistor de commande).
• La grille de contrôle du transistor de mémorisation forme un espaceur pour la grille du transistor de commande.
• De préférence, la formation de l'empilement de couches comprend des étapes de dépôt effectuées sur l'ensemble de la plaque.
• Le dépôt de la première couche est effectué de manière à ce que la première couche recouvre un flanc au moins du relief en un matériau semi conducteur et se prolonge sur le substrat. De préférence, le dépôt de la première couche est effectué sur l'ensemble de la plaque. De préférence, la première couche est déposée directement sur l'empilement de couches.
• Avantageusement, le dépôt de la première couche est un dépôt conforme.
• Avantageusement, l'épaisseur du dépôt de la première couche est au moins égale au quart de l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. De préférence l'épaisseur du dépôt de la première couche est au moins égale à la moitié de l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. Encore plus préférentiellement, elle est environ égale à l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. Cette épaisseur relative permet de mieux contrôler la largeur finale de la grille de contrôle du transistor de mémorisation après gravure standard.
• De préférence le dépôt de la deuxième couche est effectué de manière à ce que la deuxième couche recouvre le premier motif et se prolonge sur le substrat.
• Préférentiellement, la formation de la deuxième couche consiste en un dépôt.
• Avantageusement, la formation de la deuxième couche est réalisée de manière à ce que son épaisseur soit constante sur toute la surface déposée. La formation de cette couche constitue donc un dépôt conforme.
• Avantageusement, l'épaisseur de la deuxième couche est adaptée pour ajuster la largeur de la face supérieure sensiblement plane dont on veut pouvoir disposer pour la reprise de contact en fonction d'un angle supérieur que forme le premier motif de section sensiblement triangulaire. L'angle supérieur est l'angle le plus éloigné du substrat. Il est ainsi relativement aisé de définir la surface qui servira à effectuer la reprise de contact.
• De préférence, l'épaisseur du dépôt de la deuxième couche est comprise entre un quart de et deux fois l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. Avantageusement, l'épaisseur du dépôt de la deuxième couche est comprise entre un tiers de et une fois l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. Encore plus avantageusement, l'épaisseur du dépôt de la deuxième couche est environ égale à la moitié de l'épaisseur du relief en un matériau semi conducteur de la grille du transistor de commande. On obtient ainsi une large surface permettant de faciliter la reprise de contact.
• Avantageusement, le procédé comprend au moins une séquence d'étapes effectuée à l'issue de la gravure de la deuxième couche. Chaque séquence comprend au moins le dépôt d'une couche additionnelle en un matériau similaire à celui de la deuxième couche puis une gravure anisotrope de cette couche additionnelle, la gravure étant dirigée de manière perpendiculaire au plan du substrat. Ainsi, on peut obtenir une surface supérieure plane et étendue même si la gravure anisotrope n'est pas parfaitement anisotrope. De préférence on ajuste l'épaisseur du dépôt de la couche additionnelle pour obtenir en fin de séquence une face supérieure présentant la surface souhaitée. Chaque séquence est de préférence effectuée avant l'étape de protection des motifs par une résine.
• Avantageusement, l'étape de formation au moins partielle de la grille du transistor de commande comprend, préalablement du dépôt de la première couche, la formation d'une couche sacrificielle également au dessus du relief en un matériau semi conducteur. Le procédé comprend également une étape de retrait de la couche sacrificielle, effectuée postérieurement à l'étape de gravure de la deuxième couche, de sorte à générer une différence de niveau entre la face supérieure du deuxième motif et l'extrémité supérieure du relief en un matériau semi conducteur. L'extrémité supérieure du relief en un matériau semi conducteur est la dimension la plus haute de la grille du transistor de commande prise selon une direction perpendiculaire au plan du substrat. Ainsi, la face supérieure est plus haute que l'extrémité du relief. Les risques de courts-circuits sont ainsi encore réduits.
• La formation de la grille de contrôle du transistor de mémorisation est effectuée de sorte que la grille de contrôle du transistor de mémorisation est auto alignée avec la grille du transistor de commande.
• Le matériau semi conducteur de la première couche est identique au matériau semi conducteur de la deuxième couche.
• De préférence, le relief en un matériau semi conducteur formant la grille du transistor de commande est en silicium. De préférence, il s'agit de silicium poly cristallin.
• De préférence, le matériau semi conducteur de la première couche est du silicium poly cristallin.
• De préférence, le matériau semi conducteur de la deuxième couche est du silicium poly cristallin. Le procédé selon l'invention est encore plus avantageux lorsque le matériau utilisé pour la grille de contrôle du transistor de mémorisation est du silicium poly cristallin. En effet avec ce type de matériau il est particulièrement difficile d'obtenir un premier motif présentant une forme supérieure arrondie.
• Avantageusement, la gravure de la première couche comprend : une première gravure anisotrope dirigée perpendiculairement à un plan du substrat. Cette gravure laisse en place une couche résiduelle moins épaisse sur les surfaces parallèles au plan du substrat que sur les surfaces inclinées par rapport au plan du substrat, c'est-à-dire typiquement sur les flancs du relief. La première gravure peut également faire disparaître la première couche sur les surfaces parallèles au plan du substrat. De préférence, à l'issue de la première gravure il subsiste une portion de la première couche sur les surfaces parallèles au plan du substrat et le procédé comprend une seconde gravure isotrope sélective qui enlève la couche résiduelle avec arrêt de la gravure sur ledit empilement de couches.
• Avantageusement, la gravure de la deuxième couche comprend : une première gravure anisotrope dirigée perpendiculairement au plan du substrat. Cette gravure laisse en place une couche résiduelle moins épaisse sur les surfaces parallèles au plan du substrat que sur les surfaces inclinées par rapport au plan du substrat, c'est-à-dire typiquement sur les flancs du premier motif. La deuxième gravure peut également faire disparaître la deuxième couche sur les surfaces parallèles au plan du substrat. De préférence, à l'issue de la deuxième gravure il subsiste une portion de la deuxième couche sur les surfaces parallèles au plan du substrat et le procédé comprend une seconde gravure isotrope sélective qui enlève la couche résiduelle avec arrêt de la gravure sur ledit empilement de couches. On contrôle ainsi parfaitement la fin de la gravure et l'épaisseur de chacune des couches déposées qui permettront de définir la surface de contact pour la connexion de la grille de contrôle du transistor de mémorisation.

Optionally, the invention may further have at least any of the following optional features:

• The first pattern is located on the side of the relief of the gate of the control transistor and on the stack of layers.
• The first pattern has a substantially triangular section. Alternatively, it has a substantially rounded upper portion. The second pattern then extends this upper portion to form a substantially flat face.
• The relief in a semiconductor material constitutes the gate of the control transistor. It forms a line or a rectangle. If the flanks of the relief in a semiconductor material are substantially perpendicular to the substrate, then the first pattern has a section in the form of a right triangle whose two sides opposite the hypotenuse are respectively turned towards the gate of the control transistor and towards the isolation box.
• The second pattern has a substantially parallelepiped shape, one side of the parallelepiped forming the substantially flat upper face. The face is the farthest side of the substrate.
• The sections of the first and second patterns are taken in a plane substantially perpendicular to the surface of the substrate carrying the memory cell (or surface on which is arranged the gate of the control transistor).
• The control gate of the storage transistor forms a spacer for the gate of the control transistor.
• Preferably, the formation of the stack of layers comprises deposition steps performed on the entire plate.
• The deposition of the first layer is performed so that the first layer covers at least one flank of the relief in a semiconductor material and extends on the substrate. Preferably, the deposition of the first layer is performed on the entire plate. Preferably, the first layer is deposited directly on the stack of layers.
• Advantageously, the deposition of the first layer is a compliant deposit.
• Advantageously, the thickness of the deposition of the first layer is at least equal to a quarter of the thickness of the relief in a semiconductor material of the gate of the control transistor. Preferably the thickness of the deposit of the first layer is at least half the thickness of the relief in a semiconductor material of the gate of the control transistor. Even more preferably, it is approximately equal to the thickness of the relief in a semiconductor material of the gate of the control transistor. This relative thickness makes it possible to better control the final width of the control gate of the storage transistor after standard etching.
• Preferably the deposition of the second layer is carried out so that the second layer covers the first pattern and extends on the substrate.
• Preferably, the formation of the second layer consists of a deposit.
• Advantageously, the formation of the second layer is carried out so that its thickness is constant over the entire deposited surface. The formation of this layer is therefore a compliant deposit.
• Advantageously, the thickness of the second layer is adapted to adjust the width of the substantially planar upper face which it is desired to be available for the contact recovery as a function of a greater angle that forms the first substantially triangular section pattern. The upper corner is the farthest angle from the substrate. It is thus relatively easy to define the surface that will be used to perform the resumption of contact.
• Preferably, the thickness of the deposition of the second layer is between a quarter of and twice the thickness of the relief in a semiconductor material of the gate of the control transistor. Advantageously, the thickness of the deposition of the second layer is between one third of and one time the thickness of the relief in a semiconductor material of the gate of the control transistor. Even more advantageously, the thickness of the deposit of the second layer is approximately equal to half the thickness of the relief in a semiconductor material of the gate of the control transistor. This gives a large surface to facilitate the resumption of contact.
• Advantageously, the method comprises at least one sequence of steps carried out after the etching of the second layer. Each sequence comprises at least the deposition of an additional layer of a material similar to that of the second layer and then an anisotropic etching of this additional layer, the etching being directed perpendicularly to the plane of the substrate. Thus, it is possible to obtain a flat and extended top surface even if the anisotropic etching is not perfectly anisotropic. Preferably the thickness of the deposition of the additional layer is adjusted to obtain at the end of the sequence an upper face having the desired surface. Each sequence is preferably carried out before the step of protecting the patterns with a resin.
• Advantageously, the step of at least partially forming the gate of the control transistor comprises, prior to the deposition of the first layer, the formation of a sacrificial layer also above the relief in a semiconductor material. The method also comprises a step of removing the sacrificial layer, performed after the etching step of the second layer, so as to generate a difference in level between the upper face of the second pattern and the upper end of the relief in one. semiconductor material. The upper end of the relief in a semiconductor material is the highest dimension of the gate of the control transistor taken in a direction perpendicular to the plane of the substrate. Thus, the upper face is higher than the end of the relief. The risks of short circuits are thus further reduced.
• The formation of the control gate of the storage transistor is performed so that the control gate of the storage transistor is self-aligned with the gate of the control transistor.
• The semiconductor material of the first layer is identical to the semiconductor material of the second layer.
• Preferably, the relief in a semiconductor material forming the gate of the control transistor is silicon. Preferably, it is polycrystalline silicon.
• Preferably, the semiconductor material of the first layer is polycrystalline silicon.
• Preferably, the semiconductor material of the second layer is polycrystalline silicon. The method according to the invention is even more advantageous when the material used for the control gate of the storage transistor is polycrystalline silicon. Indeed with this type of material is particularly difficult to obtain a first pattern having a rounded upper shape.
• Advantageously, the etching of the first layer comprises: a first anisotropic etching directed perpendicular to a plane of the substrate. This etching leaves in place a less thick residual layer on the surfaces parallel to the plane of the substrate than on the surfaces inclined relative to the plane of the substrate, that is to say typically on the sides of the relief. The first etching can also make the first layer disappear on the surfaces parallel to the plane of the substrate. Preferably, at the end of the first etching, a portion of the first layer remains on the surfaces parallel to the plane of the substrate, and the method comprises a second selective isotropic etching which removes the residual layer with stopping of the etching on said stack of layers.
• Advantageously, the etching of the second layer comprises: a first anisotropic etching directed perpendicular to the plane of the substrate. This etching leaves in place a less thick residual layer on the surfaces parallel to the plane of the substrate than on the surfaces inclined relative to the plane of the substrate, that is to say, typically on the flanks of the first pattern. The second etching can also make the second layer disappear on the surfaces parallel to the plane of the substrate. Preferably, at the end of the second etching, there remains a portion of the second layer on the surfaces parallel to the plane of the substrate and the method comprises a second selective isotropic etching which removes the residual layer with stopping of etching on said stack of layers. The end of the etching and the thickness of each of the deposited layers are thus perfectly controlled, which will make it possible to define the contact surface for the connection of the control gate of the storage transistor.

• La formation de l'empilement de couches est effectuée de sorte qu'il se prolonge sur le substrat. L'empilement de couches comprend deux couches d'isolant électrique enserrant une couche intermédiaire de piégeage de charges.
• Le procédé comprend une étape de recouvrement du deuxième motif par au moins une couche additionnelle d'oxyde à haute température, la couche de additionnelle d'oxyde à haute température étant selon une variante avantageuse recouverte d'une couche additionnelle de nitrure de silicium. Le procédé comprend en outre une étape de retrait partiel de la couche additionnelle de sorte à laisser libre en partie au moins la face supérieure sensiblement plane. De préférence, toute la face supérieure sensiblement plane est déprotégée.
• Le procédé comprend en outre une étape de siliciuration de la face supérieure sensiblement plane.

Thus, the etching of the first layer and / or the second layer comprises, after the first anisotropic etching, a second selective isotropic etching with stopping of the etching on the stack of layers.

• The formation of the stack of layers is performed so that it extends on the substrate. The stack of layers comprises two layers of electrical insulation enclosing an intermediate layer for trapping charges.
• The method comprises a step of covering the second pattern with at least one additional layer of oxide at high temperature, the additional layer of oxide of high temperature being in an advantageous variant covered with an additional layer of silicon nitride. The method further comprises a step of partially removing the additional layer so as to leave at least partly at least the substantially flat upper face. Preferably, the entire substantially flat upper face is deprotected.
• The method further comprises a siliciding step of the substantially planar upper face.

Another aspect of the present invention relates to a memory cell obtained according to the method described above.

• un empilement de couches juxtaposé à la grille du transistor de commande, se prolongeant sur une partie au moins du substrat et configuré pour stocker des charges électriques,
• un premier motif en un matériau semi conducteur disposé sur l'empilement de couches au moins et présentant une section sensiblement triangulaire.

En outre, la grille de contrôle du transistor de mémorisation comprend en outre un deuxième motif en un matériau semi conducteur disposé sur le premier motif et configuré pour présenter une face supérieure sensiblement plane.Another aspect of the present invention relates to a double gate nonvolatile memory cell comprising a control transistor comprising a gate and a storage transistor comprising a control gate adjacent to the gate of the control transistor, the gate of the control transistor comprising a relief in a semiconductor material and the control gate of the storage transistor comprising:

• a stack of layers juxtaposed to the gate of the control transistor, extending over at least a portion of the substrate and configured to store electrical charges,
• a first pattern of a semiconductor material disposed on at least the stack of layers and having a substantially triangular section.

In addition, the control gate of the storage transistor further comprises a second pattern of a semiconductor material disposed on the first pattern and configured to have a substantially planar upper face.

BRIEF DESCRIPTION OF THE FIGURES

• La FIGURE 1a 1b illustrent des cellules mémoires à double grille de l'art antérieur.
• La FIGURE 2, qui comprend les figures 2a à 2e, décrit des étapes du procédé selon l'invention et qui permettent d'obtenir une reprise de contact beaucoup plus large sur la grille de contrôle du transistor de mémorisation d'une cellule mémoire à double grille.
• La FIGURE 3, qui comprend les figures 3a à 3f, illustre des étapes additionnelles qui complètent la formation de la grille de contrôle du transistor de mémorisation d'une cellule mémoire à double grille.
• La FIGURE 4, illustre une cellule mémoire à double grille selon un mode particulier de réalisation qui peut être optionnellement être obtenu en mettant en oeuvre le procédé selon l'invention.

The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

• The FIGURE 1a 1b illustrate double grid memory cells of the prior art.
• The FIGURE 2 , which includes FIGS. 2a to 2e , describes steps of the method according to the invention and which make it possible to obtain a much wider contact recovery on the control gate of the storage transistor of a double-gate memory cell.
• The FIGURE 3 , which includes Figures 3a to 3f , illustrates additional steps that complete the formation of the control gate of the storage transistor of a double-gate memory cell.
• The FIGURE 4 illustrates a double-gate memory cell according to a particular embodiment that can be optionally obtained by implementing the method according to the invention.

The accompanying drawings are given by way of example and are not limiting of the invention.

DETAILED DESCRIPTION OF THE INVENTION

It is recalled that one of the objectives of the invention is to obtain a wider contact recovery area which makes it easy to position the storage transistor via a connection connection with the upper wiring layers.

It is specified that in the context of the present patent application, the term "over" does not necessarily mean "in contact with". For example, the deposition of a poly-silicon layer on an insulating layer does not necessarily mean that the poly-silicon layer is in direct contact with the insulating layer, but that means that it covers at least partially by being either directly in contact with it or separated from it by another layer or other element.

The figure 2 , which includes FIGS. 2a to 2e illustrates the steps of an exemplary method according to the invention which makes it possible to obtain a larger contact area on the storage transistor and more precisely on the control gate of the storage transistor.

The figure 2a is a sectional view, similar to that of the figure 1a of a double-gate memory cell at a stage of the manufacturing process in which at least the control transistor has already been partially formed and where the self-aligned storage transistor is being prepared, without having use of lithography operations. It is recalled that the control transistor and the storage transistor share the same source and the same drain. They are therefore included in the same cell. This cell is usually referred to as a double gate transistor, each of the grids making it possible to perform the function of the transistor, either control or memorisation, to which it is dedicated. Up to this point, the manufacture of such a memory cell is done using conventional methods and means implemented by the microelectronics industry including those for the manufacture of MOS type transistors. In a standard way, these transistors, like the double-gate memory cells of the invention, are each manufactured in a box 160 of monocrystalline silicon. The boxes are electrically isolated from each other by trenches 162 typically made of silicon oxide. The formation of these trenches uses a so-called "shallow trench isolation" (STI) technique, that is "shallow trench isolation". The caissons 160 of monocrystalline silicon are in fact most often formed from the thin superficial layer of monocrystalline silicon of an elaborate substrate of the SOI type, of the "silicon on insulator" type, that is to say a "silicon on insulator" substrate. This layer of monocrystalline silicon is itself placed above a "buried oxide layer" most often referred to by its acronym BOX buried oxide layer. Each box is thus completely electrically isolated from its neighbors, laterally and at the bottom, by oxide. Not being necessary for the understanding of the process of the invention, it will be noted that only the surface layer and the lateral trenches 162 in which the boxes 160 are formed are represented. Moreover, the use of a SOI substrate is only a particular example of implementation. Other means and methods may be used so that a dual gate memory cell, employing the method described hereinafter, can be realized in an insulated box 160 and which would be obtained otherwise than from an SOI substrate.

The gate of the control transistor, also designated control gate, whose geometry has been defined by photolithography, comprises at this stage several layers which are: a relief made of semiconductor material 132, preferably polycrystalline silicon, providing the gate function; an oxide layer 133 of the MOS structure under which, as a function of the voltage applied to the gate of the control transistor, a conduction channel (not shown) will be created on the surface of the box 160 between the source areas 111 and drain 121, which are not yet formed at this stage; optionally but advantageously an oxide layer 131 which will be removed, as will be seen later, to advantageously create a difference in level for the contact recovery on the control gate of the storage transistor to prevent a short circuit with the selection grid. This oxide layer 131 may be described as a sacrificial layer. Source 111 and drain 121 will generally be obtained by ion implantation of a dopant of the monocrystalline silicon layer of the isolation chamber 160. The gate 130 of the control transistor serving as mask, source and drain will be self-aligned on it as will be seen later. A first ion implantation (not shown) may be performed at this stage in order to adjust the conduction threshold (VT) of the storage transistor.

The figure 2a shows the layers which are deposited on all the devices being manufactured in order to produce the storage transistor, that is to say on the surface of a wafer of a substrate semiconductor. After formation of the control gates 130, the layers forming the stack or layer sandwich 143 containing the trapping layer are successively deposited. A non-limiting example of a trapping layer is a layer designated by its acronym ONO, that is to say "oxide nitride oxide" of silicon. The inner layer 1432 of silicon nitride (Si ₃ N ₄ ) constitutes the floating gate which serves to trap the charges storing the state of the memory cell in the storage transistor. as previously described. Other structures are possible. In this example, the sandwich comprises three layers: a first layer, designated lower layer 1431, forming an electrical insulator, most often silicon oxide or SiO 2; a second layer, designated intermediate layer or trapping layer 1432, for trapping charges intended to memorize the state of the memory cell, it is typically silicon nitride or Si ₃ N ₄ ; a third layer, designated upper layer 1433, also forming an electrical insulator, made for example of silicon oxide as for the first layer.

Next, a first polycrystalline silicon layer 210 is deposited. This layer is intended to contribute to the formation of the control gate 140 of the storage transistor, also designated storage gate. Preferably, the gate of the control transistor is, as seen above, also made of polycrystalline silicon which has been deposited and previously etched in a conventional manner. The depot will ideally be the most "compliant" possible. A deposit is said to conform when the deposited thicknesses are the same, regardless of the angle of inclination of the surfaces on which it is made. The thickness is homogeneous at all points of the surface covered, the thickness being measured in a direction perpendicular to the free surface of the layer. Such a result can be obtained for example with a deposit method falling into the category of those called LPCVD, the acronym for "low pressure chemical vapor deposition", that is to say "chemical vapor deposition to low pressure ". We can then obtain, as represented on the figure 2a , a horizontal thickness 212 of deposit substantially equal to the vertical thickness 211.

• Dans un premier temps on effectue une gravure très anisotrope de la couche 210, permettant d'abaisser de façon uniforme l'épaisseur de silicium polycristallin dans une direction privilégiée perpendiculaire au plan du substrat. Ce type de gravure peut être réalisé en utilisant les outils classiques de gravure disponibles en microélectronique. En particulier, en utilisant ceux procédant par bombardement physique à l'aide de gaz inertes de préférence à ceux utilisant des gaz réactifs induisant une réaction chimique. Cette première gravure doit permettre de maintenir la surface 213 de la couche de silicium polycristallin 210 située au dessus de l'empilement de couches de la grille 130 du transistor de commande la plus plate possible, c'est-à-dire, comme représenté idéalement sur les figures, en préservant des changements de niveaux les plus abrupts possibles. Dans le même temps, on fait diminuer l'épaisseur de silicium polycristallin en dehors de l'empilement de couches de la grille du transistor de commande. À l'issue de cette première étape de gravure on laisse typiquement une épaisseur 211 de silicium polycristallin au dessus de la grille du transistor de commande, et sur toutes les surfaces horizontales, c'est-à-dire celles parallèles au plan du substrat, de l'ordre de 5 à 10 nm.
• Dans un deuxième temps on effectue une gravure plutôt isotrope de ce qui reste de la couche 210 de silicium polycristallin. L'avantage est qu'avec ce type de gravure on peut obtenir une très bonne sélectivité entre gravure du silicium polycristallin et gravure de la couche d'isolant 1433 (oxyde de silicium) sous jacente. C'est sur cette dernière couche que le dépôt de silicium polycristallin a été effectué pour former la couche 210. On pourra alors aisément arrêter la gravure isotrope du silicium polycristallin sur cette couche d'isolant.

To begin to realize the control gate of the storage transistor in the form of an enlarged spacer of the gate of the control transistor is then practiced a two-step etching of the layer 210 of polycrystalline silicon.

• In a first step, a very anisotropic etching of the layer 210 is carried out, making it possible to uniformly lower the polycrystalline silicon thickness in a preferred direction perpendicular to the plane of the substrate. This type of etching can be achieved using conventional etching tools available in microelectronics. In particular, using those proceeding by physical bombardment using inert gases preferably those using reactive gases inducing a chemical reaction. This first etching must make it possible to maintain the surface 213 of the polycrystalline silicon layer 210 located above the stack of layers of the gate 130 of the control transistor which is as flat as possible, that is to say, as ideally represented. on the figures, preserving the most abrupt level changes possible. At the same time, the thickness of polycrystalline silicon is decreased outside the stack of layers of the gate of the control transistor. At the end of this first etching step, a polycrystalline silicon thickness 211 is typically left above the gate of the control transistor, and on all the horizontal surfaces, that is to say those parallel to the plane of the substrate, of the order of 5 to 10 nm.
• In a second step is carried out a rather isotropic etching of what remains of the layer 210 of polysilicon. The advantage is that with this type of etching it is possible to obtain a very good selectivity between etching of the polycrystalline silicon and etching of the underlying insulator layer 1433 (silicon oxide). It is on this latter layer that the polycrystalline silicon deposition has been carried out to form the layer 210. It is then easy to stop the isotropic etching of the polycrystalline silicon on this insulating layer.

The figure 2b shows the result of the two previous etching steps. As already discussed in the chapter on the state of the art, it is extremely difficult to obtain a form of rounded spacer which would be more favorable for a resumption of contact on the control gate of the storage transistor. After the etches described above, a pattern 144 of triangular shape is obtained for what remains on the flanks of the gate of the control transistor, polycrystalline silicon 142 from the layer 210. This triangular shape is obtained whatever the thickness initially deposited to form this layer using the methods conventionally used in microelectronics. Preferably, a layer 210 of thickness substantially equal to that of the polycrystalline silicon layer 132 which is used to form the gate of the control transistor is deposited. The form The triangular shape of the pattern 144 essentially results from the fact that the engravings are never perfectly anisotropic or perfectly isotropic and that the angles at the level changes are always attacked preferentially.

The Figure 2c illustrates with photos made with a scanning electron microscope (SEM) the triangular shape obtained regardless of the thickness of the deposited silicon layer. The photo 201 shows the result obtained with a layer 210 deposited with a thickness of 65 nm. Photo 202 shows the case of a double deposited thickness of 130 nm.

The figure 2d illustrates an additional step of forming a second layer 220 above the gate 130 of the control transistor and patterns 142 formed by the first layer 210 already in place.

Preferably, this second layer 220 is obtained by conformal deposition of polycrystalline silicon. It is intended to widen the memory control grid spacer. The thickness 221 of this second layer 220 is adjusted according to the final width of the spacer which is to be obtained as will be seen in the following figures. The deposit being consistent: the thickness 221 deposited is the same on all surfaces regardless of their inclination. Before proceeding with the deposition of the second layer 220, a cleaning with hydrofluoric acid (FH) is carried out in order to remove the oxidized layer which has formed spontaneously in the presence of air on the triangular pattern 144 made of polycrystalline silicon 142 from the first deposit. For example, the thickness 221 of the second polycrystalline silicon layer 220 is about half that of the first deposit 210 210.

The figure 2e shows the result of the etching of the second layer 220 of polycrystalline silicon which has been deposited as described in the previous figure. The etching is done in two steps in a manner identical to that described for the etching of the layer 210 corresponding to the first polycrystalline silicon deposit used to form the control gate of the storage transistor. A first anisotropic etching is thus performed in a direction perpendicular to the plane of the substrate. This first etching is followed by a more isotropic or isotropic etching which is, as has been seen, selective vis-à-vis the upper layer 1433 forming an insulator and constituted in this example by a silicon oxide. This stops the engraving on the upper layer 1433 of insulation immediately underlying the stack 143 of layers ONO.

After etching, there remains, from the second layer 220 corresponding to the second deposit, the pattern 146, preferably made of polycrystalline silicon 148, which contributes to substantially widening the control gate of the storage transistor. The method is configured so that this pattern 146 has an upper face 145 as flat as possible, which will greatly facilitate the resumption of contact on this electrode.

The etching 222 of the second layer 220 being essentially anisotropic it is done vertically, that is to say perpendicular to the plane of the substrate. The thickness to be engraved being then higher in the inclined zone 147 corresponding to the hypotenuse of the triangular pattern 144, there remains after etching the pattern 146 on either side of the gate of the control transistor.

Knowing the angle 149 formed by the hypotenuse of the pattern 144 with the vertical, one can easily estimate the width of the upper plane face 145 of the pattern 146 that will be obtained by making the simplifying assumption that the etching is totally anisotropic and is made from a perfectly conformal deposit of thickness 221. It is therefore also possible to determine the thickness 221 of the second layer 220 that must be deposited to obtain a given width of the face 145 and thus adjust the total width of the control gate of the storage transistor.

Typically, in order to determine the thickness to be etched at one side of the polycrystalline silicon relief, the following calculation can be made, based on the shape of the pattern 144. The pattern is obtained after the first etching and has a section corresponding substantially to that of a right triangle: The thickness to be engraved 222 is therefore equal to the thickness of the deposition of the second layer 220 divided by the value of the sine of the angle 149.

For example, with an angle 149 of 45 °, it is found that the width of the upper plane face 145 obtained corresponds to the thickness 221 of the second polycrystalline silicon deposit multiplied by a coefficient equal in this case to 0.5; ie 45 ° cosine This for the ideal conditions mentioned above: a deposition of the second layer 220 perfectly compliant and a completely anisotropic etching. We can of course generalize this calculation to 149. From a practical point of view, it will be noted here simply that whatever the multiplication coefficient observed, the width of the upper plane face 145 increases with the thickness 211. It can therefore be adjusted to better for the application considered by controlling the thickness of the deposition of the second layer 220 used to form the control gate of the storage transistor. This result is to be compared to the triangular pattern 144 obtained after etching the deposition of the first layer which has been seen in the Figures 2c and 2d that it did not vary when the thickness of this first layer was increased.

It may be that in practice the upper face 145 of the second pattern 146 is not perfectly flat or its width is smaller than expected. This is because etching is rarely perfectly anisotropic. According to an advantageous embodiment of the invention, then at least one sequence of steps is carried out, the sequence comprising at least the following steps: the deposition of an additional layer of a material similar to that of the second layer 220 and then anisotropic etching of this additional layer. At the beginning of the sequence, the thickness of the deposition of the additional layer is adjusted to obtain at the end of the sequence an upper face 145 having the desired surface.

Preferably, each sequence comprises a cleaning step before the step of deposition of the additional layer.

In one embodiment, the method comprises a single sequence. In another embodiment, particularly for obtaining an extended surface 145, the method comprises two or more sequences.

These sequences are preferably carried out between the steps referenced 2e and 3a in the figures. Each sequence is preferably carried out before the step of protecting the patterns with a resin.

By varying the thickness of the deposition of the second layer 220 as well as optional sequences of deposition and etching of additional layers whose deposit thicknesses have been carefully controlled, the invention makes it possible to obtain an upper face 145 whose flatness and the surface is precisely controlled.

The figure 3 , which includes Figures 3a to 3f , describes the following steps of the method of forming the control gate of the storage transistor. These steps make it possible to finalize the structure of the memory cell having a much wider contact recovery surface because of the prior application of the steps described with reference to the preceding figures.

The figure 3a illustrates the step where the zone of the storage transistor 140 is defined which will be kept. As illustrated on the figure 4 which will be described in detail later, this figure being a plan view of a non-limiting example of a memory cell, only a portion of the spacer created with the two polycrystalline silicon layers can be left by photoetching, 210 and 220, as explained in the FIGS. 2a to 2e . This spacer was created, without lithography, all around the gate of the control transistor and it is left only on one of the sides of the latter to form the control gate 140 of the storage transistor. Optionally, it is possible to create a wider recovery zone 150, for example in the extension of the gate 130 of the control transistor as illustrated and described with reference to FIG. figure 4 . The figure 3a shows, in section, the photoresist layer used by the corresponding photolithography operation after revelation of the patterns. The resin patterns 310 protect the portion of the spacer, consisting of patterns 144 and 146, which must remain in place.

At this stage, in the unprotected areas 320 by the resin patterns 310, dry etching patterns from the two layers 210 and 220 that have been deposited to form the spacer. The etching of the two upper layers of the stack 143 of ONO layers is then carried out with a stop in the lower layer 1431. figure 3b illustrates this step where the removal of the resin is also carried out. The upper layer of insulator 1433 (silicon oxide in this example) is etched successively, then the intermediate layer 1432 (silicon nitride in this example). Engraving is done on the entire surface of the devices being manufactured. The ONO layer sandwich 143 is protected from etching in the storage transistor by patterns 144 and 146 (polycrystalline silicon patterns in this example). The figure 3b is a sectional view at the end of this engraving. He ... not therefore remains in place at this stage as the lower layer of insulator 1431 (silicon oxide in this example) of the ONO layer which serves as a stop to the etching above. A so-called "dry" etching is an RIE type engraving, which stands for "reactive ion etching", that is to say "reactive ion etching" or "reactive ion etching". In this technique the plasma reacts not only physically but also chemically with the surface of a wafer exposed to it by removing some or some of the substances previously deposited therein. The plasma is generated under low pressure, from 10 ^-2 to 10 ^-1 Torr, by one or more electric or even magnetic fields. The high energy ions of the plasma attack the surface of the wafer by reacting with it.

It will be noted here that the stack of ONO layers 143 is only a typical example of implementation of the trapping layer necessary for producing the storage transistor, which is often also referred to by the generic term "interpoly".

The figure 3c illustrates the step of doping the source 121 and drain 111. In this step, prior to the ion implantation operation 320 intended to boost the source and drain zones, a wet etching is performed. of the layer 1431 remaining from the stack of layers 143, and the deposition of a layer of an oxide called "screen" for example of a thickness of 3 nm. This screen layer, not shown, is intended to protect the underlying silicon during the ion implantation 320 forming source and drain.

Typically, the implanted dopants are then annealed, the screen oxide is removed and the sacrificial layer 131, also called the hard mask, is always present on the gate of the control transistor. The removal of the sacrificial layer 131 advantageously makes it possible to create a stall 360 between the polycrystalline silicon 132 of the gate of the control transistor and that of the control gate of the memory transistor, formed of the patterns 144 and 146. This difference in level thus created minimizes the risk of short circuit between these two electrodes.

The figures 3d and 3d illustrate the embodiment of the spacers after the lower layer 1431 of the stack of layers 143 ONO has been removed and the sacrificial oxide layer 131 which serves to create, as we have just seen, a difference in height between the top of the gate of the control transistor and the top of the memory 140 to minimize the risk of short circuit. Preferably, the sacrificial layer 131 is disposed between the polycrystalline silicon relief 132 and the stack of layers 143. Preferably, the thickness of the sacrificial layer is between 1/5 and 1/3 the thickness of the layer polycrystalline silicon forming the gate of the control transistor. Preferably, the thickness of the sacrificial layer is between a few nanometers and a few tens of nanometers. It thus makes it possible to position the upper end of the polycrystalline silicon relief 132 at a level lower than the upper face 145 of the second pattern 146. The risks of poor connections with the interconnections are thus significantly limited and the risks of short circuits reduced.

This is followed by the deposition of a layer 330. According to an advantageous example, this layer is an oxide called HTO, of the English "high temperature oxide", that is to say "oxide at high temperature" obtained by the LPCVD technique already mentioned previously. Typically, a thickness of 10 nm is deposited. In any case, this thickness must be sufficient to fill the voids resulting from the isotropic etching of the oxide layers of the stack 143 of layers ONO previously intervened. This layer will serve as a bonding layer and etch stop layer during the formation that follows grid spacers.

As shown on the figure 3d the deposition of the layer 330 is followed by a deposition of a layer 340, for example silicon nitride (Si3N4). This deposition can be performed by the same technique as above low pressure chemical vapor deposition (LPCVD). A layer of silicon nitride is deposited which is typically in a thickness range of 20 to 40 nm and will serve as a grid spacer for the following operations of implantation and siliciding of the contacts.

The figure 3e shows the result of the etching of the above layers, that is to say: the layer 330 of HTO and the layer 340 of Si3N4. In a conventional manner, the etching of these layers is initially very anisotropic in order to leave in place on the blanks of the control and storage grids the patterns 332, in HTO, and the patterns 342 in Si3N4 which serve as grid spacers for the next siliciding operation. This very anisotropic etching is followed by a more isotropic etching in order, as described above, to be selective and to allow the etching of the control and storage grids on the polycrystalline silicon to be stopped. This second etching must be sufficient to clear the top 145 of the pattern 146 serving as contact recovery on the control gate of the storage transistor and the top of the gate of the control transistor which will be silicided to ensure a good electrical contact.

Typically, at this stage, a second implantation of the source electrodes 111 and drain 121 is also performed in order to reduce the electrical resistance thereof. This second implantation is self limited by the grid spacers that have just been realized.

The figure 3f shows the zones 350 which are then silicided to obtain a better electrical contact with the vias, shown in FIG. figure 4 , which give access to the electrodes of the double-gate memory cell: gate 130 of the control transistor and control gate 140 of the storage transistor as well as source and drain. As the second implementation above, the siliciding of the contacts is self limited by the grid spacers.

A further advantage of the present invention is that the volume of semiconductor material accessible to perform the siliciding step is increased compared to known methods. The volume of silicide zones is thus increased and the electrical contact is improved.

This operation completes the formation of the electrodes and active elements of non-volatile dual grid memory cells 100 that can benefit from the method of the invention. The following operations concern the formation of all the interconnections between the components and memory cells of a end-of-line, which can be done in a standard way.

The figure 4 illustrates a plan view of a particular and non-limiting example of the invention of a dual-gate memory cell. This plan view shows the four electrodes controlling the memory point. It should be noted here that Figures 1a and 1b are views according to section A of the memory cell on a different scale, however. This view shows in particular the source 110, the drain 120 and the gate 130 of the control transistor. The source 110, the drain 120 and the gate 130 of the control transistor are formed by lithography. Large connection surfaces for receiving vertical connections, that is vias 151, 152 and 153, which provide interconnections with the horizontal wiring layers (not shown) of the device containing such memory cells. The cell also comprises a control gate 140 of the storage transistor. The control gate 140 of the storage transistor is formed, without using lithography, as a spacer on one of the flanks of the gate 130 of the control transistor. The connection surface is as already seen above much smaller. An improvement provided by this particular memory cell structure with respect to the conventional structures consists in substantially doubling this contact surface by creating a zone 150 of electrical contact recovery situated, in this example, in the extension of the gate 130 of the control transistor. . It is then arranged to leave in this zone, between the end of the gate 130 of the control transistor and a separate pattern or block 157, preferably of the same width and the same composition as the gate 130 of the control transistor, two spacers at a distance such that they will be in contact as shown schematically on the section B. It is in this region that a via 154 can ensure electrical contact with the gate 130 of the control transistor. In practice, such a contact recovery zone is only fully useful if it is possible at the same time to obtain a rounded or flat shape of the spacer as in the example of FIG. figure 1b .

• une zone active formée dans une couche de semi-conducteur et comportant un canal disposé entre une source 110 et un drain 120,
• une première grille disposée au moins sur une partie du canal,
• au moins une portion 155 d'un premier espaceur latéral disposé contre au moins un flanc latéral de la première grille, dont une partie forme une seconde grille disposée sur au moins une seconde partie du canal. L'une de la première ou de la seconde grille comportant en outre un empilement de couches 143 dont au moins une desdites couches est apte à stocker des charges électriques. De préférence, la première grille forme la grille 130 du transistor de commande et la seconde grille forme la grille de contrôle 140 du transistor de mémorisation.

In general, the memory cell of which a particular example is represented in figure 4 may have the following characteristics. She includes at least:

• an active area formed in a semiconductor layer and having a channel disposed between a source 110 and a drain 120,
• a first gate disposed at least on a portion of the channel,
• at least a portion 155 of a first lateral spacer disposed against at least one lateral flank of the first gate, a portion of which forms a second gate disposed on at least a second portion of the channel. One of the first or second gate further comprising a stack of layers 143, at least one of said layers is capable of storing electrical charges. Preferably, the first gate forms the gate 130 of the control transistor and the second gate forms the control gate 140 of the storage transistor.

Preferably, the memory cell further comprises at least a portion of a second lateral spacer disposed against at least one lateral flank of a block 157 disposed on the semiconductor layer, the second lateral spacer being in contact with the first lateral spacer, the two lateral spacers being composed of similar materials, said portion of the second lateral spacer forming at least a portion of a contact pad.

Optionally, in this example, a portion 156 is electrically connected to the second gate. This portion 156 is disposed against two lateral flanks of the first grid distinct and perpendicular to each other. The electrical contact pad, or contact resumption surface, is here formed by this spacer portion 156 and the spacer portion 155 formed against the block 157, and is disposed in the extension of the first gate. Such an embodiment variant has the particular advantage of being able to bring the electrically conductive lines intended to be made to contact the first gate and the second gate, thus making it possible to increase the density of a memory device formed of a matrix of memory cells. .

This double-grid electronic memory cell structure makes it possible to perform electrical contact recovery of each of the grids with a risk of short-circuiting between the grids. This structure makes it possible to relax somewhat the constraints related to the alignment of the electrical contacts by report to the gates of the memory cell, and this without having to implement an additional level of photolithography dedicated to this recovery of electrical contact.

However, it has been found that, in practice, the resumption of contact for this type of cell is really facilitated and the risks of short circuits significantly reduced only if it is possible to obtain a rounded or substantially flat shape of the spacer as in the example of the figure 1b .

The method according to the invention and a particular example of which is described with reference to Figures 2a to 3f allows to obtain this type of form. The invention thus makes it possible to considerably facilitate the resumption of contact and this for various structures of memory cells, the structure described above and an example of which is illustrated in FIG. figure 4 not being limiting of the invention. The method according to the present invention, applied to a memory cell having a structure as described in the paragraphs referring to the figure 4 , achieves particularly advantageous results.

The invention is not limited to the only previously described embodiments and extends to any embodiment in accordance with its spirit.

In particular, the invention is not limited to a layer 210 of polycrystalline silicon and / or a layer 220 of polycrystalline silicon. These layers may also be made of any other semiconductor material or a stack of layers comprising a semiconductor material.

In view of the foregoing description, it thus clearly appears that the present invention makes it possible to obtain a double-gate electronic memory cell making it possible to perform electrical contact recovery of each of the grids that do not require very precise alignment of the contacts. the grids and limiting the risk of short circuits between them.

Claims (18)

A method of manufacturing a dual gate non-volatile memory cell (100) comprising a control transistor comprising a gate (130) and a storage transistor comprising a control gate (140) adjacent to the gate (130) of the gate transistor. command, in which the steps of: At least partial formation of the gate (130) of the control transistor comprising obtaining a relief (132) of a semiconductor material on a substrate (160, 162); ○ forming the control gate (140) of the storage transistor, comprising the steps of: forming on at least one flank of the relief (132) a semiconductor material and at least a portion of the substrate (160, 162) of a stack of layers (143) configured to store electrical charges; depositing a first layer (210) of a semiconductor material so as to cover at least the stack of layers (143); etching the first layer (210) so as to form a first pattern (144) juxtaposed to the relief (132) in a semiconductor material of the gate (130) of the control transistor; characterized in that the formation of the control gate (140) of the storage transistor further comprises the following steps of: Forming a second layer (220) of a semiconductor material at least on the first pattern (144), ○ etching the second layer (220) so as to form on the first pattern (144) a second pattern (146) having a substantially planar upper face (145) configured to allow contact back on the control gate (140) of the storage transistor. Method according to the preceding claim wherein the section of the first pattern (144) has substantially a triangle shape of which two adjacent sides are respectively facing the gate of the control transistor and the substrate (160, 162). A method according to any preceding claim wherein the section of the second pattern (146) has a substantially parallelepiped shape, one side of the parallelepiped forming the upper face (145) substantially planar. A method according to the preceding claim taken in combination with claim 2, comprising a step of adjusting the thickness of the second layer (220) according to an upper angle (149) formed by the section of the first pattern (144). ) so as to adjust the width of the upper face (145) substantially flat. A method according to any one of the preceding claims wherein the etching of the first layer (210) comprises a first anisotropic etching directed perpendicularly to a plane of the substrate (160, 162) to leave in place a residual layer on the flanks of the relief ( 132). A method according to any one of the preceding claims wherein the etching of the second layer (220) comprises a first anisotropic etching directed perpendicular to a plane of the substrate (160, 162) to leave a residual layer on the first pattern (144). ). Process according to any one of the two preceding claims comprising, after the first anisotropic etching, a second selective isotropic etching with stopping of the etching on the stack of layers (143). A process according to any one of the preceding claims wherein the formation of the second layer (220) is carried out so that its thickness is constant over the entire deposited surface. A process according to any one of the preceding claims wherein the thickness of the deposition of the second layer (220) is between one-quarter to two times, and preferably one-third to one-fold, the thickness relief (132) of a semiconductor material of the gate (130) of the control transistor. Process according to any one of the preceding claims, in which the thickness of the deposition of the first layer (210) is at least equal to a quarter of, and preferably approximately equal to, the thickness of the relief (132) made of a semi-material conductor of the gate (130) of the control transistor. Process according to any one of the preceding claims comprising at least one sequence of steps carried out after the etching of the second layer (220), each sequence comprising at least the deposition of an additional layer of a similar material that of the second layer (220) and then anisotropic etching of this additional layer, the method preferably comprising at least two sequences. A method according to any preceding claim wherein the at least partial formation of the gate (130) of the control transistor comprises, prior to the deposition of the first layer (210), the formation of a sacrificial layer (131) at the the top of the relief (132) of a semiconductor material, the method also comprising a step of removing the sacrificial layer (131) performed after the etching step of the second layer (220) so as to generate a difference in level between the upper face (145) of the second pattern (146) and the upper end of the relief (132) of a semiconductor material. A method according to any one of the preceding claims wherein the control gate (140) of the storage transistor forms a spacer for the gate (130) of the control transistor. A method as claimed in any preceding claim wherein the formation of the control gate (140) of the storage transistor is performed such that the control gate (140) of the storage transistor is self-aligned with the gate (130) of the control transistor. A method according to any one of the preceding claims wherein the semiconductor material of the first layer (210) is polycrystalline silicon and wherein the semiconductor material of the second layer (220) is also polycrystalline silicon and wherein said stack layer (143) preferably comprises two layers of electrical insulation (1431, 1433) enclosing a charge trapping intermediate layer (1432). A process according to any one of the preceding claims comprising a step of covering the second pattern (146) with at least one additional layer of high temperature oxide (330) and preferably with an additional layer of silicon nitride (340) and a partial removal step of the additional layer at least so as to leave at least partly at least the upper face (145) substantially flat. A method as claimed in any one of the preceding claims comprising a step of siliciding the substantially planar upper face (145). A dual gate nonvolatile memory cell (100) comprising a control transistor comprising a gate (130) and a storage transistor including a control gate (140) adjacent to the gate (130) of the control transistor, the gate (130) ) of the control transistor comprising a relief (132) of a semiconductor material and the control gate (140) of the storage transistor comprising: a stack of layers (143) juxtaposed to the gate of the control transistor (140) and configured to store electrical charges, a first pattern (144) of a semiconductor material disposed on the stack of layers (143) and having a substantially triangular section, characterized in that the control gate (140) of the storage transistor further comprises a second pattern (144) of semiconductor material disposed on the first pattern (144) and configured to have a substantially planar upper face (145).

Images