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EP2389052A4 - WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND PULP FOR INTERCONNECTION HOLE - Google Patents

WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND PULP FOR INTERCONNECTION HOLE

Info

Publication number
EP2389052A4
EP2389052A4 EP11728762A EP11728762A EP2389052A4 EP 2389052 A4 EP2389052 A4 EP 2389052A4 EP 11728762 A EP11728762 A EP 11728762A EP 11728762 A EP11728762 A EP 11728762A EP 2389052 A4 EP2389052 A4 EP 2389052A4
Authority
EP
European Patent Office
Prior art keywords
wiring substrate
pulp
manufacturing
interconnection hole
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11728762A
Other languages
German (de)
French (fr)
Other versions
EP2389052A1 (en
Inventor
Shogo Hirai
Hiroyuki Ishitomi
Tsuyoshi Himori
Satoru Tomekawa
Yutaka Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Kyoto Elex Co Ltd
Original Assignee
Panasonic Corp
Kyoto Elex Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Kyoto Elex Co Ltd filed Critical Panasonic Corp
Publication of EP2389052A1 publication Critical patent/EP2389052A1/en
Publication of EP2389052A4 publication Critical patent/EP2389052A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0272—Mixed conductive particles, i.e. using different conductive particles, e.g. differing in shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0425—Solder powder or solder coated metal powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Conductive Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
EP11728762A 2010-02-25 2011-02-22 WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND PULP FOR INTERCONNECTION HOLE Withdrawn EP2389052A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010040538A JP4616927B1 (en) 2010-02-25 2010-02-25 WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND VIA PASTE
PCT/JP2011/000988 WO2011105053A1 (en) 2010-02-25 2011-02-22 Wiring substrate, method for producing wiring substrate, and via paste

Publications (2)

Publication Number Publication Date
EP2389052A1 EP2389052A1 (en) 2011-11-23
EP2389052A4 true EP2389052A4 (en) 2012-01-18

Family

ID=43596780

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11728762A Withdrawn EP2389052A4 (en) 2010-02-25 2011-02-22 WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND PULP FOR INTERCONNECTION HOLE

Country Status (6)

Country Link
US (1) US8563872B2 (en)
EP (1) EP2389052A4 (en)
JP (1) JP4616927B1 (en)
CN (1) CN102282918B (en)
TW (1) TWI432103B (en)
WO (1) WO2011105053A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4917668B1 (en) * 2010-12-29 2012-04-18 パナソニック株式会社 Multilayer wiring board and method for manufacturing multilayer wiring board
JP4795488B1 (en) * 2011-01-18 2011-10-19 パナソニック株式会社 WIRING BOARD, WIRING BOARD MANUFACTURING METHOD, AND VIA PASTE
JP5099272B1 (en) * 2011-12-26 2012-12-19 パナソニック株式会社 Multilayer wiring board and manufacturing method thereof
WO2013099204A1 (en) * 2011-12-26 2013-07-04 パナソニック株式会社 Wiring board and manufacturing method therefor
TW201340807A (en) * 2011-12-28 2013-10-01 Panasonic Corp Flexible wiring board, method for manufacturing flexible wiring board, package product using flexible wiring board, and flexible multilayer wiring board
CN103314652A (en) * 2012-01-17 2013-09-18 松下电器产业株式会社 Wiring substrate and production method therefor
DE102012001883B3 (en) * 2012-02-01 2013-04-25 Isabellenhütte Heusler Gmbh & Co. Kg Soldering method and corresponding soldering device
CN105033496B (en) * 2015-07-03 2018-01-09 北京康普锡威科技有限公司 A kind of compound lead-free high-temperature solder of high-strength highly-conductive and preparation method thereof
KR102412612B1 (en) * 2015-08-28 2022-06-23 삼성전자주식회사 board for package and prepreg
CN107848075B (en) 2015-09-15 2021-03-19 株式会社村田制作所 Joining member, method for manufacturing joining member, and joining method
WO2017056842A1 (en) 2015-09-28 2017-04-06 株式会社村田製作所 Heat pipe, heat dissipation component, and method for producing heat pipe
CN107835724B (en) * 2015-11-05 2020-09-08 株式会社村田制作所 Joining member and method for manufacturing joining member
CN109673112B (en) * 2017-10-13 2021-08-20 鹏鼎控股(深圳)股份有限公司 Flexible circuit board and manufacturing method thereof
US11426818B2 (en) 2018-08-10 2022-08-30 The Research Foundation for the State University Additive manufacturing processes and additively manufactured products
DE102018007243B4 (en) * 2018-09-13 2020-08-13 Diehl Ako Stiftung & Co. Kg Electrical circuit
JP2020077772A (en) * 2018-11-08 2020-05-21 富士通株式会社 Wiring board and electronic device
US11581239B2 (en) 2019-01-18 2023-02-14 Indium Corporation Lead-free solder paste as thermal interface material

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002290052A (en) * 2001-03-23 2002-10-04 Kyocera Corp Multilayer wiring board
EP1408726A1 (en) * 2001-07-18 2004-04-14 Matsushita Electric Industrial Co., Ltd. METHOD AND MATERIAL FOR MANUFACTURING CIRCUIT−FORMED SUBSTRATE

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
CA2196024A1 (en) 1996-02-28 1997-08-28 Craig N. Ernsberger Multilayer electronic assembly utilizing a sinterable composition and related method of forming
US5890915A (en) * 1996-05-17 1999-04-06 Minnesota Mining And Manufacturing Company Electrical and thermal conducting structure with resilient conducting paths
JP3187373B2 (en) 1998-07-31 2001-07-11 京セラ株式会社 Wiring board
US6326555B1 (en) 1999-02-26 2001-12-04 Fujitsu Limited Method and structure of z-connected laminated substrate for high density electronic packaging
TW498707B (en) * 1999-11-26 2002-08-11 Matsushita Electric Ind Co Ltd Wiring substrate and production method thereof
JP2002094242A (en) * 2000-09-14 2002-03-29 Denso Corp Material for connecting layers of printed multi-layer board and method for manufacturing printed multi-layer board using the material
US6930395B2 (en) * 2000-12-05 2005-08-16 Matsushita Electric Industrial Co., Ltd. Circuit substrate having improved connection reliability and a method for manufacturing the same
EP1489695B1 (en) * 2002-03-04 2008-09-10 Sumitomo Electric Industries, Ltd. Anisotropic conductive film and method for producing the same
US6574114B1 (en) * 2002-05-02 2003-06-03 3M Innovative Properties Company Low contact force, dual fraction particulate interconnect
US7078822B2 (en) * 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
JP2004265607A (en) * 2003-01-23 2004-09-24 Matsushita Electric Ind Co Ltd Conductive paste, circuit board using the same, and manufacturing method of the circuit board
TWI325739B (en) 2003-01-23 2010-06-01 Panasonic Corp Electroconductive paste, its manufacturing method, circuit board using the same electroconductive paste, and its manufacturing method
JP4078990B2 (en) * 2003-01-23 2008-04-23 松下電器産業株式会社 Conductive paste, circuit forming substrate using the conductive paste, and manufacturing method thereof
US7367116B2 (en) 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
JP2005136034A (en) * 2003-10-29 2005-05-26 Matsushita Electric Ind Co Ltd Multilayer flexible printed wiring board and its production process
US7427717B2 (en) * 2004-05-19 2008-09-23 Matsushita Electric Industrial Co., Ltd. Flexible printed wiring board and manufacturing method thereof
JP2009147026A (en) * 2007-12-12 2009-07-02 Panasonic Corp Circuit board and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002290052A (en) * 2001-03-23 2002-10-04 Kyocera Corp Multilayer wiring board
EP1408726A1 (en) * 2001-07-18 2004-04-14 Matsushita Electric Industrial Co., Ltd. METHOD AND MATERIAL FOR MANUFACTURING CIRCUIT−FORMED SUBSTRATE

Also Published As

Publication number Publication date
CN102282918B (en) 2014-09-10
WO2011105053A1 (en) 2011-09-01
EP2389052A1 (en) 2011-11-23
JP4616927B1 (en) 2011-01-19
US20110290549A1 (en) 2011-12-01
US8563872B2 (en) 2013-10-22
TW201206263A (en) 2012-02-01
JP2011176220A (en) 2011-09-08
CN102282918A (en) 2011-12-14
TWI432103B (en) 2014-03-21

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20110711

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Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

A4 Supplementary search report drawn up and despatched

Effective date: 20111216

RIC1 Information provided on ipc code assigned before grant

Ipc: H05K 1/09 20060101ALI20111212BHEP

Ipc: H05K 3/40 20060101ALI20111212BHEP

Ipc: H05K 3/46 20060101AFI20111212BHEP

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

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Effective date: 20131205