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EP2256578A1 - Low-dropout Spannungsregler mit niedrigem Ruhestrom - Google Patents

Low-dropout Spannungsregler mit niedrigem Ruhestrom Download PDF

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Publication number
EP2256578A1
EP2256578A1 EP10004211A EP10004211A EP2256578A1 EP 2256578 A1 EP2256578 A1 EP 2256578A1 EP 10004211 A EP10004211 A EP 10004211A EP 10004211 A EP10004211 A EP 10004211A EP 2256578 A1 EP2256578 A1 EP 2256578A1
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EP
European Patent Office
Prior art keywords
voltage
control
transistor
current
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10004211A
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English (en)
French (fr)
Inventor
Claude Renous
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Publication of EP2256578A1 publication Critical patent/EP2256578A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to a low voltage drop voltage regulator circuit, or LDO. More particularly, the present invention relates to a circuit configuration for minimizing quiescent current in an LDO.
  • LDOs are DC regulators that receive an input voltage from a voltage source, such as a battery, and provide a stable output voltage at an electrical load.
  • the voltage source may vary or become depleted over time, but the load requires a constant supply voltage to operate.
  • the minimum difference between the input and output voltages that still allows the low-voltage regulator to regulate the output voltage is known as the "drop out voltage".
  • This waste voltage should be as low as possible to maximize efficiency while minimizing energy dissipation, and is thus between 1.0 and 1.5 V. For example, if the waste voltage is 0.7 V, the input voltage must be at least 4.0 V to provide an output voltage of 3.3 V.
  • Low voltage drop regulators are particularly useful in battery-powered portable applications, such as mobile phones, digital music players, personal digital assistants, cameras, and so on.
  • the LDO1 controller comprises an IN input node and an OUT output node.
  • the input node receives a Vin input voltage provided by a PS power source, such as a battery.
  • the output node OUT is connected to a load LD and provides a regulated output voltage Vreg and an output current Iout to the load LD.
  • the regulator LDO1 comprises a regulation transistor TREG, a GCS gate control stage and an EAMP error amplifier.
  • the regulation transistor TREG here a PMOS transistor, has its source S connected to the input node IN and its drain D connected to the output node OUT.
  • the gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
  • the GCS gate control stage comprises a high-gate bias resistor RG1 ("pull-up gate resistor") and a control transistor TQ, here an NPN bipolar transistor.
  • the resistor RG1 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG.
  • the transistor TQ has a collector C connected to the gate G of the transistor TREG and an emitter E connected to ground by a resistor RG2.
  • the base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP.
  • the EAMP amplifier includes a negative input and a positive input.
  • the negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source.
  • the positive input receives a feedback voltage Vf.
  • the feedback voltage is a percentage of the output voltage Vreg, provided by a voltage divider comprising resistors R1, R2.
  • the error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the GCS gate control stage.
  • the quiescent current Iq is defined as the current that is used to bias the GCS gate control stage, and is equal to a current Iin at the input node IN of the controller minus a current Iout supplied to the load LD and an Iamp current supplied to the EAMP error amplifier.
  • the quiescent current is considered to consist essentially of the current flowing in the gate resistor RG1.
  • the reference voltage Vref is assumed to be 1.8V and R2 is assumed to be 0.
  • the horizontal axis represents time and it is assumed that the voltage Vin gradually decreases as the source of power is discharging.
  • the quiescent current Iq is substantially constant in the region on the left side of the dashed line and begins to increase when the ohmic region is reached, particularly when the current consumption in the load is high. For both current consumption (50 nA and 50 mA), the quiescent current increases abruptly and reaches a maximum value when the output voltage Vreg is almost equal to the input voltage Vin (Vin-Vreg ⁇ 0, 2 V).
  • the error amplifier EAMP tries to maintain the output voltage at its nominal value (Vref) and draws the gate voltage Vg downwards. Assuming that the voltage V CE flowing through the transistor TQ is very low, the maximum value of the quiescent current is approximately equal to Vin / (RG1 + RG2).
  • Iamp current flowing through the error amplifier is in general constant and it will therefore be considered that nothing can be done to control its value.
  • US Pat. No. 7,312,598 discloses a low waste voltage regulator having a quiescent current control circuit including a PMOS detecting transistor capable of detecting a low charge current, for example 0.5 mA.
  • a voltage Vqc is set to a high value.
  • the controller when it detects the low charge current state, generates a relatively low quiescent current by disabling some components, and so less power is consumed.
  • the voltage Vqc is set to a low value so that all components disabled for the low charge state are quickly enabled for full operation.
  • Embodiments of the invention provide a low voltage dropout voltage regulator comprising a regulating transistor for providing a regulated output voltage from an input voltage, a gate control stage including a gate circuit high-bias gate resistor and a control transistor, for supplying a gate voltage to the control transistor, an error amplifier for supplying a control voltage to a control transistor control terminal, and a quiescent current control circuit for limiting a quiescent current flowing through the gate control stage as the input voltage approaches the output voltage and inputs the control transistor into an ohmic conduction mode .
  • the quiescent current control circuit includes a current source providing a current of reference and is configured to control the quiescent current by mirror effect based on the reference current.
  • the current control circuit is also configured to simultaneously control the control voltage supplied by the error amplifier to the control terminal of the control transistor.
  • the current control circuit comprises an output which is connected to the control terminal of the control transistor and is configured to change the control voltage supplied by the error amplifier to the control terminal.
  • the quiescent current control circuit comprises a first transistor having a first conduction terminal connected to the current source, a second conduction terminal arranged to receive the output voltage and a terminal control circuit arranged to receive the gate voltage, and the gate resistance circuit comprises a transistor which is coupled in current mirror configuration with the first transistor of the idle current control circuit.
  • the low-voltage voltage regulator comprises a Miller compensation branch connected between a conduction terminal of the control transistor and the first conduction terminal of the control transistor.
  • the quiescent current control circuit comprises a second transistor having a control terminal connected to the first conduction terminal of the first transistor, a first conduction terminal connected to the ground, and a second conduction terminal connected to the control terminal of the control transistor.
  • the gate resistance circuit comprises a gate transistor interacting with a transistor of the quiescent current control circuit to create a current mirror between the quiescent current control circuit and the grid control stage.
  • the gate resistance circuit also comprises a first resistor in parallel with the gate transistor and a second resistor in series with the first resistor.
  • the quiescent current control circuit is configured to be in a deactivated state in which it does not consume current when the control transistor has not entered ohmic conduction mode.
  • the regulation transistor is in ohmic conduction mode when the voltage difference between the input voltage and the regulated output voltage is less than or equal to 2.0 V.
  • Embodiments of the invention also relate to a portable device comprising a battery for providing an input voltage, a circuit powered by a regulated voltage, and a low voltage voltage regulator according to one of the embodiments. described above, to provide the regulated output voltage from the input voltage.
  • the figure 3 illustrates a LDO2 low voltage regulator according to one embodiment of the invention.
  • the LDO2 regulator comprises an input node IN and an output node OUT.
  • the input node receives an input voltage Vin supplied by a PS power source, such as a battery.
  • the output node OUT is connected to a load LD schematically represented by a resistor RL and a capacitor CL in parallel, and provides a regulated output voltage Vreg and an output current Iout to the load LD.
  • the regulator LDO2 comprises a regulation transistor TREG, a gate control stage GCS, an amplifier amplifier EAMP (differential amplifier) and a current control circuit CCT.
  • the regulation transistor TREG here a PMOS transistor, has its source S connected to the node IN and its drain D connected to the node OUT.
  • the gate G of the transistor is driven by a gate voltage Vg supplied by the GCS gate control stage.
  • the GCS gate control stage comprises a gate resistance circuit RG10 and a control transistor TQ, here an NPN bipolar transistor.
  • the resistance circuit RG10 has a terminal connected to the input node IN and a terminal connected to the gate G of the transistor TREG.
  • the transistor TQ has a collector C connected to the gate G of the transistor TREG and a transmitter E connected to ground (GND) by a resistor RG2.
  • the base B of the transistor TQ receives a control voltage Vc supplied by the error amplifier EAMP.
  • the EAMP amplifier includes a negative input and a positive input.
  • the negative input receives a stable voltage Vref provided by a stable voltage source BG, such as a bandgap voltage source.
  • the positive input receives a feedback voltage Vf.
  • the feedback voltage is a percentage of the output voltage Vreg provided by a voltage divider comprising resistors R1, R2.
  • the error amplifier compares the reference voltage Vref and the feedback voltage Vf, and supplies the control voltage Vc to the gate control stage GCS.
  • the quiescent current control circuit CCT has two inputs respectively connected to the gate G of the transistor TREG and to the output node OUT of the regulator, and an output connected to the base B of the transistor TQ.
  • the quiescent current control circuit CCT has an internal current source CS10, and is arranged to detect the gate voltage Vg applied by the gate control stage GCS to the transistor TREG. When the gate voltage Vg reaches a value which indicates that the transistor TREG has entered ohmic conduction mode, the quiescent current control circuit CCT activates and controls the quiescent current Iq passing through the gate control stage GCS so to prevent the quiescent current from reaching excessive values. Also, the quiescent current control circuit CCT "takes over" the error amplifier EAMP and takes control of the voltage Vc applied to the base B of the transistor TQ in order to control the gate voltage Vg of the transistor TREG regulation.
  • the control of the quiescent current Iq by the control circuit CCT is carried out by means of a current mirror mechanism between the current source CS10 and the gate control stage GCS.
  • a transistor may be added to the GCS gate control stage.
  • a PMOS transistor TG is arranged in the gate resistance circuit RG10, i.e. in the pull-up section of the GCS gate control stage. which receives the input voltage Vin and supplies the gate voltage Vg.
  • the gate resistance circuit RG10 comprises two resistors RG11, RG12 in series and a transistor TG is diode-connected in parallel with the resistor RG11, its drain D being connected to its gate G.
  • the resistor RG11 has a high value, for example 1 M ⁇ , and is provided as a leakage resistor to ensure that the gate voltage Vg of the regulating transistor TREG receives the input voltage Vin in the absence of control by the error amplifier, for example when the circuit is switched on.
  • the resistance RG12 has a low value, for example 10 K ⁇ .
  • the figure 4 illustrates an example of implementation of the quiescent current control circuit CCT and an example of implementation of the error amplifier EAMP.
  • the quiescent current control circuit CCT comprises a PMOS transistor T10, an NMOS transistor T11, and the current source CS10.
  • a branch Miller compensation comprising, for example, a resistor R10 and a capacitor C10 may also be provided.
  • the transistor T10 has its source S connected to the output node OUT of the regulator LDO2, its drain D connected to ground (GND) by the current source CS10, and its gate G connected to the gate G of the regulation transistor TREG in order to detect the gate voltage Vg.
  • the transistor T11 has its gate connected to the drain D of the transistor T10, its drain D connected to the base B of the transistor TQ, and its source S connected to ground.
  • the compensation branch Miller comprising the resistor R10 and the capacitor C10, is connected between the emitter E of the transistor TQ and the drain D of the transistor T10.
  • the error amplifier EAMP conventionally comprises a current source CS1, PMOS transistors TE1, TE2, NPN bipolar transistors TE3, TE4 and resistors RE1, RE2.
  • the current source CS1 has a first terminal connected to the input node IN of the regulator, and a second terminal connected to the sources S of the transistors TE1, TE2.
  • the drains D of the transistors TE1, TE2 are respectively connected to the collectors C of the transistors TE3, TE4.
  • Transmitters E of transistors TE3, TE4 are respectively connected to ground by resistors RE1, RE2.
  • the collector C of the transistor TE4 is connected to the base B of the transistor TQ and supplies the control voltage Vc when the quiescent current control circuit CCT is in the non-conductive state.
  • the bases B of the transistors TE3, TE4 are both connected to the collector C of the transistor TE3.
  • the gate G of the transistor TE1 receives the reference voltage Vref and the gate G of the transistor TE2
  • the quiescent current control circuit CCT is arranged to monitor the voltage difference between the gate voltage Vg and the output voltage Vreg.
  • the transistor T10 of the current control circuit CCT is in the non-conducting state because the voltage difference Vgs between its gate G and its source S is positive and therefore higher than its negative threshold voltage (Vg> Vreg).
  • Current source CS10 also prevents transistor T11 from driving. Therefore, the quiescent current control circuit CCT is in the off state and does not interfere with the normal operation of the EAMP error amplifier. In addition, it does not consume power.
  • the LDO2 regulator functions as the conventional LDO1 regulator of the figure 1 .
  • the error amplifier EAMP When the input voltage Vin decreases, for example as the power source PS discharges if it is a battery, the error amplifier EAMP tries to maintain the output voltage Vreg necessary, as explained above.
  • the gate voltage Vg begins to decrease and the difference between the gate voltage and the source voltage of the transistor T10, which is equal to Vg-Vreg, becomes negative and lower than its negative threshold voltage (Vg ⁇ Vreg).
  • the transistor TQ is highly conductive and the transistor T10 begins to become conductive.
  • the current source CS10 imposes a current Iref by the transistor T10 and also limits the quiescent current by a current mirror effect.
  • the ratio between the controlled quiescent current Iq and the current Iref is determined by the respective dimensions of the transistors T10 and TG, that is to say their respective W / L ratios (W being the width of the gate and L being the length of the gate of the transistors).
  • W being the width of the gate
  • L being the length of the gate of the transistors.
  • the drain voltage of the transistor T10 causes the transistor T11 to begin to become conductive, and thus to control the base voltage Vb of the transistor TQ and to prevent the error amplifier EAMP from pulling the control voltage Vc upwards. .
  • the base B of the transistor TQ is pulled to ground, and the transistor T11 regulates the conduction of the transistor TQ.
  • the transistor T11 controls the base B of the transistor TQ to ensure that Iref is equal to the current flowing through the current source CS10, so that an additional control mechanism appears.
  • Iref is equal to the through current CS10
  • the current Iq is controlled and is equal to Iref or proportional to Iref as a function of the W / L ratios.
  • the reference voltage Vref is assumed to be 1.8V, and R2 is assumed to be 0.
  • the horizontal axis represents time and it is assumed that the voltage Vin gradually decreases.
  • the quiescent current Iq is substantially constant in the region to the left of the dashed line.
  • Vin approaches the nominal value the output voltage Vreg and Vin-Vreg becomes equal to 0.2 V.
  • the quiescent current control circuit CCT prevents the gate control stage GCS from rapidly pulling the gate voltage Vg towards the gate. low while preventing the quiescent current Iq from decreasing abruptly.
  • the quiescent current Iq is approximately maintained at the same value it had before reaching the ohmic conduction mode.
  • the figure 6 illustrates schematically an example of application of a LDO2 low voltage regulator according to the invention.
  • the low voltage LDO2 regulator is arranged in a portable HDV device having a BT battery forming its PS power source, and circuitry on MBD motherboard.
  • the circuitry may include, for example, a BBP baseband processor configured to establish a telephone communication over a cellular network.
  • the battery provides the Vin input voltage of the LDO2 regulator and the regulated voltage Vreg provided by the LDO2 regulator powers all or some of the components of the motherboard, in particular the BBP baseband processor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
EP10004211A 2009-05-15 2010-04-21 Low-dropout Spannungsregler mit niedrigem Ruhestrom Withdrawn EP2256578A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0902363 2009-05-15

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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012060304A (ja) * 2010-09-07 2012-03-22 Toshiba Corp デジタル／アナログ変換器
US9035641B1 (en) * 2011-06-06 2015-05-19 Altera Corporation Startup circuit
US9535439B2 (en) * 2013-11-08 2017-01-03 Texas Instruments Incorporated LDO current limit control with sense and control transistors
US9665111B2 (en) * 2014-01-29 2017-05-30 Semiconductor Components Industries, Llc Low dropout voltage regulator and method
CN105446403A (zh) 2014-08-14 2016-03-30 登丰微电子股份有限公司 低压差线性稳压器
EP3051378B1 (de) * 2015-01-28 2021-05-12 ams AG Schaltung eines Reglers mit geringer Abfallspannung und Verfahren zur Steuerung einer Schaltung eines Reglers mit geringer Abfallspannung
US9575498B2 (en) 2015-01-29 2017-02-21 Qualcomm Incorporated Low dropout regulator bleeding current circuits and methods
US9813056B2 (en) 2015-09-21 2017-11-07 Analog Devices Global Active device divider circuit with adjustable IQ
CN108508954A (zh) * 2018-06-11 2018-09-07 贵州道森集成电路科技有限公司 一种超低功耗低压差线性稳压器
US10788848B2 (en) * 2019-02-26 2020-09-29 Stmicroelectronics Design And Application S.R.O. Voltage regulator with controlled current consumption in dropout mode
CN109992036B (zh) * 2019-04-28 2021-05-25 南京英锐创电子科技有限公司 应用ldo电路的芯片及电子设备
US11392155B2 (en) 2019-08-09 2022-07-19 Analog Devices International Unlimited Company Low power voltage generator circuit
US11086343B2 (en) 2019-11-20 2021-08-10 Winbond Electronics Corp. On-chip active LDO regulator with wake-up time improvement
EP3951551B1 (de) * 2020-08-07 2023-02-22 Scalinx Spannungsregler und -verfahren
CN114460994B (zh) * 2020-11-09 2024-09-27 扬智科技股份有限公司 电压调整器
FR3117622B1 (fr) 2020-12-11 2024-05-03 St Microelectronics Grenoble 2 Courant d'appel d'au moins un régulateur de tension à faible chute
CN114625206B (zh) * 2020-12-11 2024-08-02 意法半导体(格勒诺布尔2)公司 至少一个低压差电压调节器的涌入电流
US11687104B2 (en) 2021-03-25 2023-06-27 Qualcomm Incorporated Power supply rejection enhancer
US11656643B2 (en) * 2021-05-12 2023-05-23 Nxp Usa, Inc. Capless low dropout regulation
CN114740947B (zh) * 2022-04-26 2023-10-20 思瑞浦微电子科技（苏州）股份有限公司 基于ldo的动态电流响应电路、动态电流控制方法及芯片
US20240201721A1 (en) * 2022-12-16 2024-06-20 Renesas Electronics Corporation Low dropout regulator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4906913A (en) * 1989-03-15 1990-03-06 National Semiconductor Corporation Low dropout voltage regulator with quiescent current reduction
US5867015A (en) * 1996-12-19 1999-02-02 Texas Instruments Incorporated Low drop-out voltage regulator with PMOS pass element
US7312598B1 (en) * 2006-08-25 2007-12-25 National Semiconductor Corporation Capacitor free low drop out regulator
US20080191670A1 (en) * 2005-07-21 2008-08-14 Freescale Semiconductor, Inc. Voltage Regulator With Pass Transistors Carrying Different Ratios Of The Total Load Current And Method Of Operation Therefor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315230A (en) * 1992-09-03 1994-05-24 United Memories, Inc. Temperature compensated voltage reference for low and wide voltage ranges
US6285246B1 (en) * 1998-09-15 2001-09-04 California Micro Devices, Inc. Low drop-out regulator capable of functioning in linear and saturated regions of output driver
US7095257B2 (en) * 2004-05-07 2006-08-22 Sige Semiconductor (U.S.), Corp. Fast low drop out (LDO) PFET regulator circuit
US7446514B1 (en) * 2004-10-22 2008-11-04 Marvell International Ltd. Linear regulator for use with electronic circuits
US8604762B2 (en) * 2006-05-25 2013-12-10 Texas Instruments Incorporated Low noise, low dropout regulators
DE602007012242D1 (de) * 2007-08-30 2011-03-10 Austriamicrosystems Ag Spannungsregler und Verfahren zur Spannungsregelung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4906913A (en) * 1989-03-15 1990-03-06 National Semiconductor Corporation Low dropout voltage regulator with quiescent current reduction
US5867015A (en) * 1996-12-19 1999-02-02 Texas Instruments Incorporated Low drop-out voltage regulator with PMOS pass element
US20080191670A1 (en) * 2005-07-21 2008-08-14 Freescale Semiconductor, Inc. Voltage Regulator With Pass Transistors Carrying Different Ratios Of The Total Load Current And Method Of Operation Therefor
US7312598B1 (en) * 2006-08-25 2007-12-25 National Semiconductor Corporation Capacitor free low drop out regulator

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
AL-SHYOUKH M ET AL: "A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 42, no. 8, 1 August 2007 (2007-08-01), pages 1732 - 1742, XP011188648, ISSN: 0018-9200 *
GABRIEL A RINCON-MORA ET AL: "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 33, no. 1, 1 January 1998 (1998-01-01), XP011060653, ISSN: 0018-9200 *
MOHAMMAD AL-SHYOUKH ET AL: "A Transient-Enhanced 20 A-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation", CONFERENCE 2006, IEEE CUSTOM INTEGRATED CIRCUITS, IEEE, PISCATAWAY, NJ, USA, 1 September 2006 (2006-09-01), pages 615 - 618, XP031052546, ISBN: 978-1-4244-0075-1 *
SHAN YUAN ET AL: "Low dropout voltage regulator for wireless applications", 33RD.ANNUAL IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE. PESC 2002. CONFERENCE PROCEEDINGS. CAIRNS, QUEENSLAND, AUSTRALIA, JUNE 23 - 27, 2002; [ANNUAL POWER ELECTRONICS SPECIALISTS CONFERENCE], NEW YORK, NY : IEEE, US, vol. 2, 23 June 2002 (2002-06-23), pages 421 - 424, XP010747488, ISBN: 978-0-7803-7262-7 *
ZUSHU YAN ET AL: "A low-voltage CMOS low-dropout regulator with novel capacitor-multiplier frequency compensation", CIRCUITS AND SYSTEMS, 2008. ISCAS 2008. IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 18 May 2008 (2008-05-18), pages 2685 - 2688, XP031392565, ISBN: 978-1-4244-1683-7 *

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