EP2049967A2 - Controlled frequency core processor and method for starting-up said core processor in a programmed manner - Google Patents

Abstract

The invention concerns a controlled frequency core processor. It comprises at least one processor, a non-volatile memory comprising a start-up program, a bridge interconnecting the busses which link the different components of said core processor, an interface component. The non-volatile memory comprises at least two corresponding configurations with respect to the frequency, each of which has a mode of operation of the busses and/ or of the components of said core processor. The non-volatile memory comprises an information which allows for determining which mode of operation has to be used, wherein said information is read by the interface component in order to determine the selected mode. The interface component generates one or several clock signals. The frequency of said clock signals generated substantially corresponds to the one described by the configuration of the selected mode. The clock signals control the busses and/ or the components of said core processor. The invention also concerns a method for starting-up said core processor in a programmed manner. In particular, the invention is applied to core processors installed in an aircraft.

Description

 Heart processor frequency pi lotée and method of starting said processor heart in a n mode programmed.

The invention relates to a frequency-controlled processor core and a method of starting said processor core in a programmed mode. In particular, the invention applies to processor cores embedded in aircraft.

A processor core, also known as the CPU card, is an onboard electronic card comprising a processor performing calculations and treatments. For example, a processor core may in particular be embedded in an aircraft type system where it performs a set of specific numerical calculations. A processor core, particularly in the aeronautical field, performs tasks of great criticality, such as the management of flight parameters, and must therefore have significant reliability. To meet these constraints, a processor core is defined by a detailed definition file and validated, and must be the subject of a validation / certification phase both conceptually and materially. It follows in particular that each modification of a characteristic of said processor core must be subject to an evolution of the definition file followed by a study of risk and / or impact on its reliability and those of related equipment. It is of course worth noting that such studies have a significant impact on the cost of the core processor. In this context, one of the characteristics of a processor core that can be modified not only during the design phase but also during the life cycle of said core is the frequency of the components included in the processor core. The modification of the frequency of the components included in the processor core is generally referred to as the "clamping / unclamping" of a processor core. In addition, in relation to the previously stated constraints, it is desirable that the "clamping / unclamping" of the processor core can be performed without hardware modification ("without hardware retrofit").

It is known, to perform a "clamping / unclamping" of a processor core, to include in it frequency multiplying components (PLL), and / or clock drivers including jumpers ("Clock drivers by pull-up / pull-down"). Unfortunately, a hardware "retrofit" is inevitable to achieve the frequency change of the processor core. This is reflected in particular by an impossibility of dynamic change (that is to say during operation) of configuration, as well as the disadvantages previously exposed.

In the computer field in particular that of personal computers, basic input / output systems (BIOS) can be provided in some cases with a device integrated in the motherboard for changing the processor frequency and the bus frequency. However, this solution does not have sufficient security and reliability characteristics for an embedded processor core. Indeed, if an erroneous value is written via the BIOS before restarting the computer, it will be unable to start again and will be in an unstable and unpredictable state.

The purpose of the invention is in particular to overcome the aforementioned drawbacks. For this purpose, the subject of the invention is a processor core comprising at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the different components of said processor core. The processor core comprises an interface component, a non-volatile memory comprising at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core. The nonvolatile memory includes information to determine which mode of operation should be used. Said information is read by the interface component to determine the chosen mode. The interface component generates one or more clock signals. The frequency of said generated clock signals substantially corresponds to that described by the configuration of the chosen mode. The clock signals drive the buses and / or the components of said processor core.

Advantageously, when the reading by the interface component of the information on the selected mode proves impossible or erroneous, the interface component is adapted to choose a default mode. In one embodiment, the processor core comprises a clock delivering a reference clock signal. The frequency of said reference clock signal is then multiplied by the interface component to generate the signals whose frequency corresponding substantially to that described by the configuration of the chosen mode.

The processor core may receive a protection signal, said signal authorizing or not depending on its value the writing of information to determine which mode of operation should be used. The information to determine which operating mode should be used is for example modifiable by programming the non-volatile memory and / or the processor.

The invention also relates to a method for starting a processor core comprising at least one non-volatile memory comprising a startup program, a bridge interconnecting buses connecting the various components of said processor core, an interface component, the memory non-volatile having at least two frequency configurations each corresponding to a mode of operation of the buses and / or components of said processor core. The non-volatile memory includes information to determine which mode of operation is to be used, said information being read by the interface component to determine the mode chosen. The method comprises the following steps: a power-up step of the processor core, the components of the processor core being held by the interface component in an inhibited state; a step where the interface component prohibits the resetting of the non-volatile memory; a read access step by the interface component to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory; a step of generation by the interface component of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core; o a step of disinhibition by the interface component of the different components.

Advantageously, after the processor core power-up step, the method includes a delay step until the reference clock signal satisfies certain defined stability criteria.

Advantageously, if the reading by the interface component of the information on the mode chosen at the read access step proves impossible or erroneous, the interface component chooses at the step in place of inaccessible or erroneous information a default mode.

In one embodiment, after the step of generating by the interface component one or more signals whose frequency corresponds to the configuration of the selected mode, the method includes a delay step until the buses reach stably their target frequency.

In another embodiment, at the signal generation step by the interface component, the latter determines multiplicative factors to be applied to the frequency of a reference clock signal to obtain one or more signals of which the frequency corresponds to that described in the configuration corresponding to the selected mode.

The advantages of the invention include that it makes it possible to secure and make reliable the management of bus frequency changes. It can be totally managed at the hardware level of the processor core. The invention allows a hardware check of the restart configuration with a still valid default configuration, even if the storage area of the configuration is erased. Other characteristics and advantages of the invention will become apparent with the aid of the following description made with reference to the appended drawings which represent:

FIG. 1, a block diagram of the processor core according to the invention;

FIG. 2, a diagram of a process for starting the processor core in a programmed mode according to the invention;

FIG. 1 shows a block diagram of a processor core according to the invention. The frequency-controlled processor core according to the invention comprises in particular at least one processor 1. The processor 1 is particularly suitable for performing numerical calculations. The processor 1 communicates via at least one processor bus 10 to the other components of the processor core. The processor core may also comprise RAM 3, for example DDR-SDRAM type memory. The RAM 3 is accessible via a memory bus 1 1. The processor core may also include external buses 13, such as one or more PCI buses. The processor core comprises a nonvolatile memory 4 comprising the startup program. The non-volatile memory 4 may for example be a FLASH memory bank. The processor core comprises an interface component 6 between a clock 5 (for example, a quartz), a multiplexed peripheral bus 1 1 to which is connected in particular the nonvolatile memory 4 comprising the startup program, and possibly a signal of protection 7 of the startup program. The interface component 6 may be a programmable component. The processor core comprises a bridge 2 responsible for managing and interconnecting the buses of said core.

The startup program included in the nonvolatile memory 4 includes the instructions necessary to start the processor core. The non-volatile memory 4 comprises at least two frequency configurations, each corresponding to a mode of operation of the buses and / or components of the processor core: a bridled mode, an unbridled mode. The operating frequency of the buses in unbridled mode is greater or equal to the flanged mode. The nonvolatile memory 4 comprises information, contained for example in memory locations, for determining which mode of operation should be used for the next start of the processor core. The configuration relating to a given operating mode describes in particular the frequency at which the buses must operate and possibly, if relevant, the components of the processor core. The protection signal 7 authorizes or not according to its value the writing of the information to determine which mode of operation should be used. For example, when the protection signal 7 is received, it is possible to read but not to write the information to determine which mode of operation should be used. Conversely, when the protection signal 7 is not received, it is possible to write said information. The information to determine which operating mode is to be used can be modified by programming the nonvolatile memory 4 and / or the processor 1.

The interface component 6 receives a reference clock signal 5 from the clock. The interface component 6 reads the information on the chosen mode included in the non-volatile memory 4. If the reading of the information on the chosen mode proves impossible or erroneous (the detection can for example be ensured by a mechanism cyclic redundancy check or Cyclic Redundancy Check or by checking the membership of the read values to a predefined value range), the interface component 6 selects a mode by default, corresponding, for example, to the lowest frequency of the different buses and / or components of the processor core. The default mode can in particular be programmed within the interface component 6. This mechanism provides an additional level of security, in particular avoiding the use of a value entered by mistake or inaccurate in the non-volatile memory. of the selected mode and the associated configuration included in the non-volatile memory 4, the interface component 6 generates one or more clock signals from the reference clock signal 5. These clock signals generated have a frequency corresponding to that described in the configuration of the selected mode. These generated clock signals are used to drive the buses and / or components of the processor core. These clock signals will then be used for each bus and / or component and will then determine their operating frequency. Thus, if the configuration describing the flanged mode corresponds to an operating frequency of 100 MHz for the processor bus 10, the memory bus 1 1, the interface component will generate a signal of frequency substantially equal to 100 MHz, thus forcing the processor 1, the processor bus 10, the RAM 3 and the memory bus 1 1 to operate at 100 MHz. Thus, if the configuration describing the unbridled mode corresponds to an operating frequency of 133 MHz for the processor bus 10, the memory bus 11, the interface component will generate a frequency signal substantially equal to 133 MHz, thus forcing the processor 1 , the processor bus 10, the RAM 3 and the memory bus 11 to operate at 133 MHz. It is of course possible to define, if the processor core can support it moreover, different bus frequencies for the same mode given according to the components, and to operate the memory bus 1 1 at a different speed of the processor bus 1.

FIG. 2 schematically illustrates a method for starting the processor core in a programmed mode according to the invention. Elements identical to the elements already presented in the other figures bear the same references. The starting method according to the invention describes the starting sequence of a processor core according to the invention (for example, that illustrated in FIG. 1) in a given operating mode. In a step 20, the processor core is powered on. The core processor components (such as the processor 1, the bridge 2, ...) are maintained in an inhibited state (or according to the English expression "reset"). A step 21 delays until the clock signal from clock 5 meets certain defined stability criteria. The interface component 6 prohibits in a step 22 the resetting of the nonvolatile memory 4 comprising the startup program. Then in a step 23, the interface component 6 reads the information contained in the non-volatile memory 4, in particular the selected operating mode and the associated configuration. If the reading by the interface component 6 of the information on the chosen mode proves to be impossible or erroneous, the interface component 6 chooses in step 23 instead of the inaccessible or erroneous information a default mode, corresponding for example to the lowest frequency of the various buses and / or components of the processor core. From this information, in a step 24, the interface component 6 generates one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses and / or the components of said processor core. For this, the interface component determines the multiplicative factor to be applied to the frequency of the clock signal 5 to obtain a signal whose frequency corresponds to the configuration corresponding to the selected mode. Thus, this multiplicative factor depends on the configuration of the selected mode and is therefore different depending on whether the active mode selected is the bridled mode or the unbridled mode. From this multiplicative factor, the interface component 6 generates a signal whose frequency corresponds to the configuration of the selected mode. This signal is then used by the different buses of the processor core. In a delay step, a time delay makes it possible to wait for the buses to stably reach their target frequency. Then, the interface component 6 disinhibits the various components (processor 1, bridge 2, ...), in a step 26. The processor 1, the bridge 2, the buses, and the other components can then start in a step 27 in the selected mode, flanged or not. The processor core can then be used by the operating system in the selected operating mode.

The operating mode can be changed to another mode. To make this change, it is possible for example to remove the protection of the non-volatile memory containing the startup program by modifying the input protection signal 7 to allow writing. The chosen mode can then be re-registered either by programming (for example by using a JTAG type cable) or by the processor 1. The new configuration will only be taken into account after a power failure.

Claims

A processor core comprising at least one processor (1), a non-volatile memory (4) comprising a startup program, a bridge (2) interconnecting buses (10, 1 1, 12, 13) connecting the different components (1). , 3, 4, 6) of said processor core, characterized in that it comprises an interface component (6), a non-volatile memory (4) comprising at least two frequency configurations each corresponding to a mode of operation of the buses (10, 11, 12, 13) and / or components (1, 3, 4, 6) of said processor core, the nonvolatile memory (4) having information to determine which mode of operation is to be used, said information being read by the interface component (6) to determine the selected mode, the interface component (6) generating one or more clock signals, the frequency of said generated clock signals substantially corresponding to that described by the configuration of the selected mode, said clock signals oge driving the buses (10, 11, 12, 13) and / or the components (1, 3, 4, 6) of said processor core. 2. Heart processor according to claim 1 characterized in that, when the reading by the interface component (6) of the information on the selected mode is impossible or erroneous, the interface component (6) is adapted to choose a default mode. 3. Heart processor according to any one of claims 1 to 2 characterized in that it comprises a clock delivering a reference clock signal (5), the frequency of said reference clock signal (5) being multiplied by the interface component (6) for generating the signals whose frequency corresponds substantially to that described by the configuration of the chosen mode. 4. Heart processor according to any one of claims 1 to 3, characterized in that it receives a protection signal (7), said signal allowing or not depending on its value the writing of the information to determine which mode of operation should be used 5. Heart processor according to claim 4 characterized in that the information for determining which operating mode is to be used is modifiable by programming the nonvolatile memory (4) and / or by the processor (1). Process for starting a processor core comprising at least one non-volatile memory (4) comprising a startup program, a bridge (2) interconnecting buses (10, 1 1, 12, 13) connecting the different components (1) , 3, 4, 6) of said processor core, characterized in that, the processor core also having an interface component (6), the non-volatile memory (4) having at least two frequency configurations each corresponding to a mode of operation of buses (10, 1 1, 12, 13) and / or components (1, 3, 4, 6) of said processor core, the nonvolatile memory (4) having information to determine which mode of operation is to be used, said information being read by the interface component (6) to determine the chosen mode, it comprises the following steps: a step (20) of powering the processor core, the components of the processor core (1, 3 ) being maintained by the interface component in a inhibited state; a step (22) where the interface component (6) prohibits the resetting of the non-volatile memory (4); a step (23) of read access by the interface component (6) to the information relating to the selected operating mode and the associated configuration contained in the non-volatile memory (4); a step (24) of generation by the interface component (6) of one or more signals whose frequency corresponds to the configuration of the selected mode, said signals driving the buses (10, 1 1, 12, 13) and / or the components (1, 3, 4, 6) of said processor core; a step (26) of disinhibition by the interface component (6) of the various components (1, 2). 7. Method according to claim 6, characterized in that after step (20) of powering the processor core, the method comprises a step (21) of delay until the reference clock signal ( 5) meet certain defined criteria of stability. 8. Method according to any one of claims 6 to 7 characterized in that if the reading by the interface component (6) of the information on the mode chosen in step (23) read access s is impossible or erroneous, the interface component (6) chooses in step (23) instead of the inaccessible or erroneous information a default mode. 9. Method according to any one of claims 6 to 8 characterized in that after the step (24) of generating by the interface component (6) of one or more signals whose frequency corresponds to the configuration of the In the selected mode, the method includes a delay step (25) until the buses stably reach their target frequency. 10. Method according to any one of claims 6 to 10 characterized in that in step (24) of generating signals by the interface component (6), the latter (6) determines multiplicative factors to applying at the frequency of a reference clock signal (5) to obtain one or more signals whose frequency corresponds to that described in the configuration corresponding to the selected mode.