[go: up one dir, main page]

EP2005575B1 - Selbstkalibrierender mischer - Google Patents

Selbstkalibrierender mischer Download PDF

Info

Publication number
EP2005575B1
EP2005575B1 EP07735271.4A EP07735271A EP2005575B1 EP 2005575 B1 EP2005575 B1 EP 2005575B1 EP 07735271 A EP07735271 A EP 07735271A EP 2005575 B1 EP2005575 B1 EP 2005575B1
Authority
EP
European Patent Office
Prior art keywords
load
signal
mixer
adjustor
slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP07735271.4A
Other languages
English (en)
French (fr)
Other versions
EP2005575A2 (de
Inventor
Patrick A. Y. Ozenne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Priority to EP07735271.4A priority Critical patent/EP2005575B1/de
Publication of EP2005575A2 publication Critical patent/EP2005575A2/de
Application granted granted Critical
Publication of EP2005575B1 publication Critical patent/EP2005575B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/109—Means associated with receiver for limiting or suppressing noise or interference by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1433—Balanced arrangements with transistors using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products

Definitions

  • the invention relates to a mixer circuit, and also relates to a device comprising a mixer circuit, to a method, to a computer program product and to a medium.
  • Examples of such a mixer circuit are circuits comprising mixers.
  • Examples of such a device are devices comprising transmitters, receivers and/or transceivers.
  • a prior art mixer circuit is known from EP 1 531 553-A1 , which discloses in its Figs. 2 and 3 a mixer circuit comprising a mixer for receiving an input signal and an oscillation signal and for outputting an output signal and comprising a compensation branch in parallel to the mixer for receiving the input signal and for in response to the input signal providing an adjustable compensation signal.
  • the output signal and the compensation signal are combined for compensating a distortion of the mixer.
  • the known mixer circuit is disadvantageous, inter alia, owing to the fact that a parallel compensation branch is used. Such an additional branch must estimate the distortion that is to be compensated all the time, during calibration as well as during normal operation, and thereby introduces additional noise and additional distortion itself.
  • the mixer circuit By providing the mixer circuit with a mixer comprising a load having an adjustable load value and with an adjustor for sweeping the load and with a detector for detecting components of the output signal for the swept load and with a selector for selecting a detection and in response setting the load, a distortion of the mixer is reduced without a parallel compensation needing to be introduced.
  • the mixer circuit according to the invention is further advantageous, inter alia, in that its calibration and its normal operation are separated from each other.
  • a distortion of the mixer is minimized for the particular component.
  • the second order intermodulation product or IM2 is responsible for relatively much distortion. Therefore it is important to reduce the distortion of the mixer for this particular (frequency) component.
  • a second order input intercept point or IIP2 represents an amplitude of the input signal at which a desired output signal in amplitude becomes equal to a spectral component of the second order intermodulation product. So, a relatively small second order intermodulation product results in a relatively high second order input intercept point, which is an important demand in for example wireless technologies. Further information about IM2 and IIP2 is disclosed in US-Application 2005-0124311 and US-Application 2006-0035611 .
  • An embodiment of the mixer circuit according to the invention is defined by the input signal comprising an amplitude modulation jammer signal or a two tones signal. Each one of these input signals has proven to function well.
  • the amplitude modulation jammer signal for example comprises a 20kHz amplitude modulation jammer signal and the two tones signal for example comprises a 100kHz two tones signal, without excluding other frequencies.
  • the controller for example comprises or forms part of a processor or a processor system and the adjustor for example comprises a hardware or software counter and/or a hardware or software converter for converting a count value into an adjustment signal destined for the load.
  • the load In the calibration mode the load is to be swept and then to be set.
  • the non-calibration mode such as a normal operation mode the load should keep its set load value.
  • a difference between two subsequent adjustment signals should be a relatively small step and in a non-sensitive mode a difference between two subsequent adjustment signals should be a relatively large step.
  • the clock signal for clocking the adjustor In a fast mode the clock signal for clocking the adjustor should be relatively fast and in a slow mode the clock signal for clocking the adjustor should be relatively slow.
  • the device according to the invention comprises the mixer circuit according to the invention.
  • the switches couple the receiver and the transmitter via the input signal generator to each other in a calibration mode and couple the receiver and the transmitter to one antenna or to their own antennas in a non-calibration mode such as a normal operation mode.
  • Embodiments of the device according to the invention and of the method according to the invention and of the computer program product according to the invention and of the medium according to the invention correspond with the embodiments of the mixer circuit according to the invention.
  • the invention is based upon an insight, inter alia, that a parallel compensation or an adjustment of a parallel compensation is to be avoided, and is based upon a basic idea, inter alia, that a load of a mixer should have an adjustable load value and an adjustor should sweep the load and a detector should detect a component of a mixer output signal for the swept load and selector should select a detection and in response set the load.
  • the invention solves the problem, inter alia, to provide a mixer circuit comprising a mixer in which mixer circuit a distortion of the mixer is reduced without a parallel compensation being needed.
  • the mixer circuit according to the invention is further advantageous, inter alia, in that its calibration and its normal operation are separated from each other.
  • the mixer 2 shown in the Fig. 1 comprises first and second transistors 21 and 22 comprising first main electrodes (for example emitters or sources) coupled to each other and comprises a third transistor 23 comprising a first main electrode (for example an emitter or a source) coupled via a current source 24 to ground and comprising a second main electrode (for example a collector or a drain) coupled to the first main electrodes of the first and second transistors 21 and 22.
  • first main electrodes for example emitters or sources
  • a third transistor 23 comprising a first main electrode (for example an emitter or a source) coupled via a current source 24 to ground and comprising a second main electrode (for example a collector or a drain) coupled to the first main electrodes of the first and second transistors 21 and 22.
  • a second main electrode (for example a collector or a drain) of the first transistor 21 is coupled via a first impedance 25 (for example a parallel circuit of a capacitor and a resistor) to a reference terminal and a second main electrode (for example a collector or a drain) of the second transistor 22 is coupled via a second impedance 26 (for example a parallel circuit of a capacitor and a resistor) to the reference terminal.
  • a first impedance 25 for example a parallel circuit of a capacitor and a resistor
  • second main electrode (for example a collector or a drain) of the second transistor 22 is coupled via a second impedance 26 (for example a parallel circuit of a capacitor and a resistor) to the reference terminal.
  • a control electrode (for example a basis or a gate) of the third transistor 23 constitutes an input 27 for receiving an input signal and control electrodes (for example bases or gates) of the first and second transistors 21 and 22 constitute an oscillator input 28a,28b for receiving an oscillator signal and the second main electrodes of the first and second transistors 21 and 22 constitute an output 29a,29b for outputting an output signal.
  • the second main electrodes of the first and second transistors 21 and 22 are further coupled to each other via a load 3.
  • This load 3 comprises four parallel branches, one branch comprising an impedance 31 and the other three branches each comprising a serial construction of an impedance 32,34,36 and a switch 33,35,37.
  • the load 3 further comprises a control input 38 for receiving an adjustment signal for adjusting the load 3 by operating the switches 33,35,37. Different constructions per branch and different constructions of the branches and different numbers of branches are not to be excluded.
  • the load 3 has an adjustable load value.
  • the mixer circuit 1 further comprises an adjustor 4 for adjusting the load 3 by supplying an adjustment signal to the load 3 via the control input 38. In a calibration mode the adjusted load 3 is swept such that it has different load values at different moments in time.
  • the mixer circuit 1 further comprises a detector 5 for detecting a component of the output signal per load value and a selector 6 for selecting a detection result and for instructing the adjustor 4 to set the load in response to the selected detection result.
  • the set load 3 has a set load value.
  • the detector 5 comprises an amplifier 51 and filtering circuitry 52 for filtering the component and slope detection circuitry 53 coupled to each other in a serial construction.
  • the detection of the component per load value comprises a slope detection of the component per load value.
  • the selector 6 comprises comparison circuitry 61 for comparing slope values with each other for finding an extreme slope value that defines the selected detection result and thereto comprises for example a memory 62 coupled to an output of the slope detection circuitry 53 for receiving and storing slope values.
  • the memory 62 is coupled to the comparison circuitry in one direction for receiving instructions to provide one or more slope values and in the other direction for providing the slope values.
  • the mixer circuit 1 further comprises a controller 7 that for example comprises the adjustor 4 and the selector 6 for in a calibration mode sweeping the adjustor 4 and for in a non-calibration mode locking the adjustor 4 and/or for in respective sensitive and non-sensitive modes providing adjustment signals with respective smaller and larger steps to the load 3.
  • the adjustor 4 for example comprises a clock input for receiving a clock signal and an output for providing an adjustment signal to the load 3 and the controller for example comprises a clock signal generator 71 for generating the clock signal for in respective fast and slow modes generating respective faster and more slowly clock signals.
  • the controller 7 further for example comprises a processor 72 for controlling the adjustor 4 and the signal clock generator 71 and the comparison circuitry 61 and the memory 62.
  • the processor may be integrated into the adjustor 4 and/or the signal clock generator 71 and/or the comparison circuitry 61 and/or the memory 62, or the adjustor 4 and/or the signal clock generator 71 and/or the comparison circuitry 61 and/or the memory 62 may form part of the processor 72 etc.
  • the device 8 comprises a receiver 81 comprising the mixer 2 and a transmitter 82 and an input signal generator 91 for receiving a transmitter signal from the transmitter 82 via a transmitter switch 93 and for in response to the transmitter signal providing the input signal via a receiver switch 97 to the mixer 2.
  • the receiver 81 further comprises for example the receiver switch 97 with an operation input coupled to an output of receiving circuitry 96 and with a calibration input coupled to an output of the input signal generator 91 and with an output coupled to the input 27 of the mixer 2.
  • the transmitter 82 further comprises for example the transmitter switch 93 with an input coupled to first transmitting circuitry 94 and with an operation output coupled to an input of second transmitting circuitry 92 and with a calibration output coupled to an input of the input signal generator 91.
  • the device 8 further comprises for example an antenna circuit 83 with an antenna coupled to antenna circuitry that comprises an input coupled to an output of the second transmitting circuitry 92 and that comprises an output coupled to an input of the receiving circuitry 96.
  • the component may for example comprise a second order intermodulation product, without excluding other components.
  • the second order intermodulation product or IM2 is responsible for relatively much distortion. Therefore it is important to reduce the distortion of the mixer 2 for this particular (frequency) component.
  • a second order input intercept point or IIP2 represents an amplitude of the input signal at which a desired output signal in amplitude becomes equal to a spectral component of the second order intermodulation product. So, a relatively small second order intermodulation product results in a relatively high second order input intercept point, which is an important demand in for example wireless technologies.
  • the mixer circuit 1 functions as follows.
  • an input signal such as for example an amplitude modulation jammer signal (for example a 20kHz AM jammer signal) or a two tones signal (for example a 100kHz two tones signal) is supplied to the input 27.
  • This input signal may originate from a specific generator not shown and controlled by the controller 7 or may originate from the input signal generator 91 as later explained at the hand of the Fig. 3 .
  • an oscillation signal such as a local oscillation signal is supplied to the input 28 shown in the Fig. 2 and comprising the inputs 28a and 28b shown in the Fig. 1 .
  • the load 3 receives via the control input 38 an adjustment signal originating from the adjustor 4.
  • the adjustor 4 for example comprises a counter, without excluding other kinds of adjustors, and the adjustment signal then comprises subsequent count values.
  • the load 3 is adjusted by opening and/or closing one or more of the switches 33 and 35 and 37.
  • the adjustment signal may comprise one round of increasing or decreasing count values and may comprise several rounds of increasing and/or decreasing count values such as triangle shaped signals (increasing count values followed by decreasing count values etc.). These triangle shaped signals have proven to function very well.
  • the filtering circuitry 52 filters the IM2 component per different output signal and supplies the IM2 component per output signal to the slope detection circuitry 53, which detects the slope of the IM2 component per output signal.
  • Slope values are stored in the memory 62 and the comparison circuitry 61 determines an extreme slope value that for example defines the load value corresponding to the output signal that has resulted in this extreme load value.
  • the load 3 is set to this particular load value, via the adjustor 4. Thereto, the counter of the adjustor 4 is for example locked and generates a fixed count value that is used as an adjustment signal. Then, a non-calibration mode such as a normal operation mode may begin.
  • the input signal may originate from the input signal generator 91 as shown in the Fig. 3 .
  • the transmitter 82 is used for providing a transmitter signal via the transmitter switch 93 and the input signal generator 91 converts the transmitter signal into the input signal that is supplied via the receiver switch 97 to the mixer 2.
  • the transmitter switch 93 and the receiver switch 97 therefore, in a calibration mode, couple the receiver 81 and the transmitter 82 with each other via the input signal generator 91 and, in a non-calibration mode, couple the mixer circuit 1 of the receiver 81 and the first transmitting circuitry 94 of the transmitter 82 each to the antenna circuit 83.
  • the detection of the IM2 component may be performed via a diode and/or the filtering circuitry 52 may comprise a diode.
  • This diode comprises an anode for receiving an amplified output signal and comprises a cathode coupled via a parallel construction of a capacitor and a resistor to ground.
  • the clock speed of the counter of the adjustor is smaller than the IM2 frequency
  • the clock speed of the counter of the adjustor is larger than the IM2 frequency
  • the operation of the mixer circuit 1 could be as shown in the Fig. 4 .
  • the blocks in the Fig. 4 have the following meaning:
  • Step 1 From 30dBm to 60dBm (+/-5dBm) of IIP2 level, high clock, low precision.
  • Step2 To reduce the calibration duration, an initial value of the counter can be loaded such as the calibration value minus ten or zero if it was smaller than zero.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transmitters (AREA)
  • Superheterodyne Receivers (AREA)
  • Transceivers (AREA)
  • Amplifiers (AREA)

Claims (10)

  1. Mischerschaltung (1), die Folgendes umfasst:
    - einen Mischer (2) zum Empfangen eines Eingangssignals und eines Oszillationssignals und zum Ausgeben eines Ausgangssignals, wobei der Mischer (2) eine Last (3) mit einem einstellbaren Lastwert enthält,
    - eine Einstelleinrichtung (4) zum Einstellen der Last (3) während einer Kalibrierungsbetriebsart, so dass die eingestellte Last (3) zu unterschiedlichen Zeitpunkten unterschiedliche Lastwerte besitzt,
    - einen Detektor (5) zum Detektieren einer Frequenzkomponente des Ausgangssignals pro Lastwert, wobei die Frequenzkomponente ein Intermodulationsprodukt zweiter Ordnung enthält, wobei der Detektor (5) eine Filterungsschaltungsanordnung (52) zum Filtern der Frequenzkomponente und eine Steigungsdetektionsschaltungsanordnung (53), die mit dem Ausgang der Filterungsschaltung verbunden ist, enthält, wobei die Detektion der Komponente pro Lastwert eine Detektion der Steigung der Komponente pro Lastwert enthält, und
    - eine Auswahleinrichtung (6) zum Auswählen eines Detektionsergebnisses und zum Anweisen der Einstelleinrichtung (4), um die Last in Reaktion auf das ausgewählte Detektionsergebnis einzustellen, wobei die Auswahleinrichtung (6) eine Vergleichsschaltungsanordnung (61) umfasst, um Steigungswerte miteinander zu vergleichen, um einen extremen Steigungswert zu finden, der das ausgewählten Detektionsergebnis definiert, das von der Einstelleinrichtung zum Einstellen der Last verwendet wird, wobei die eingestellte Last (3) einen eingestellten Lastwert hat.
  2. Mischerschaltung (1) nach Anspruch 1, wobei das Eingangssignal ein Amplitudenmodulations-Störersignal oder ein Zweitonsignal enthält.
  3. Mischerschaltung (1) nach Anspruch 1, die ferner Folgendes umfasst:
    - eine Steuereinheit (7), die die Einstelleinheit (4) und die Auswahleinrichtung (6) enthält, um in einer Kalibrierungsbetriebsart die Einstelleinrichtung (4) zum Abtasten zu veranlassen und um in einer Nichtkalibrierungsbetriebsart die Einstelleinrichtung (4) zu verriegeln.
  4. Mischerschaltung (1) nach Anspruch 1, die ferner Folgendes umfasst:
    - eine Steuereinheit (7), die die Einstelleinrichtung (4) für empfindliche und nicht empfindliche Betriebsarten enthält, die Einstellsignale mit kleineren bzw. größeren Schritten für die Last (3) bereitstellen.
  5. Mischerschaltung (1) nach Anspruch 1, die ferner Folgendes umfasst:
    eine Steuereinheit (7), die die Einstelleinrichtung (4) mit einem Takteingang zum Empfangen eines Taktsignals und mit einem Ausgang zum Bereitstellen eines Einstellsignals für die Last (3) enthält und einen Taktsignalgenerator (71) zum Erzeugen des Taktsignals für schnelle bzw. langsame Betriebsarten, die schnellere bzw. langsamere Taktsignale erzeugen, enthält.
  6. Vorrichtung (8), die die Mischerschaltung (1) nach Anspruch 1 umfasst.
  7. Vorrichtung (8) nach Anspruch 6, die ferner Folgendes umfasst:
    - einen Empfänger (81), der den Mischer (2) enthält,
    - einen Sender (82) und
    - einen Eingangssignalgenerator (91) zum Empfangen eines Sendesignals von dem Sender (82) über einen Senderschalter (93) und zum Bereitstellen in Reaktion auf das Sendesignal des Eingangssignals über einen Empfängerschalter (97) für den Mischer (2).
  8. Verfahren, das die folgenden Schritte umfasst:
    - für einen Mischer (2) zum Empfangen eines Eingangssignals und eines Oszillationssignals und zum Ausgeben eines Ausgangssignals Einstellen einer Last (3) des Mischers (2) während einer Kalibrierungsbetriebsart, wobei die Last (3) einstellbare Lastwerte hat, so dass die eingestellte Last (3) zu verschiedenen Zeitpunkten unterschiedliche Lastwerte besitzt, und
    - Detektieren mittels eines Detektors einer Frequenzkomponente des Ausgangssignals pro Lastwert, wobei die Frequenzkomponente ein Intermodulationsprodukt zweiter Ordnung enthält, Auswählen eines Detektionsergebnisses und Einstellen der Last (3) in Reaktion auf das ausgewählte Detektionsergebnis, wobei die eingestellte Last (3) einen eingestellten Lastwert besitzt,
    wobei der Schritt des Detektierens das Filtern mittels eines Filters der Frequenzkomponente und eine Steigungsdetektion mittels einer Steigungsdetektionsschaltungsanordnung, die mit dem Ausgang des Filters verbunden ist, für die Steigung der Komponente pro Lastwert umfasst und wobei das Auswählen das Vergleichen von Steigungswerten miteinander umfasst, um einen extremen Steigungswert zu finden, der das ausgewählte Detektionsergebnis definiert.
  9. Computerprogrammprodukt zum Ausführen der Schritte des Verfahrens nach Anspruch 8.
  10. Medium, das das Computerprogrammprodukt nach Anspruch 9 enthält.
EP07735271.4A 2006-03-30 2007-03-27 Selbstkalibrierender mischer Not-in-force EP2005575B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07735271.4A EP2005575B1 (de) 2006-03-30 2007-03-27 Selbstkalibrierender mischer

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP06300306 2006-03-30
EP07735271.4A EP2005575B1 (de) 2006-03-30 2007-03-27 Selbstkalibrierender mischer
PCT/IB2007/051068 WO2007113733A2 (en) 2006-03-30 2007-03-27 Self-calibrating mixer

Publications (2)

Publication Number Publication Date
EP2005575A2 EP2005575A2 (de) 2008-12-24
EP2005575B1 true EP2005575B1 (de) 2016-10-19

Family

ID=38421426

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07735271.4A Not-in-force EP2005575B1 (de) 2006-03-30 2007-03-27 Selbstkalibrierender mischer

Country Status (5)

Country Link
US (1) US8160533B2 (de)
EP (1) EP2005575B1 (de)
JP (1) JP4682335B2 (de)
CN (1) CN101416381B (de)
WO (1) WO2007113733A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045944B2 (en) * 2007-09-14 2011-10-25 Qualcomm Incorporated Offset correction for passive mixers
US8060043B2 (en) * 2008-10-09 2011-11-15 Freescale Semiconductor Adaptive IIP2 calibration
ES2406705T3 (es) * 2008-12-12 2013-06-07 St-Ericsson Sa Método y sistema de calibración de un punto de interceptación de intermodulación de segundo orden de un transceptor de radio
US8204467B2 (en) 2009-02-10 2012-06-19 Telefonaktiebolaget Lm Ericsson (Publ) Passive mixer mismatch tuning using self-tests to suppress IM2
US8634793B2 (en) 2010-05-10 2014-01-21 Csr Technology Inc. IP2 calibration measurement and signal generation
US9344789B2 (en) * 2013-06-07 2016-05-17 Robert Bosch Gmbh Digital microphone interface supporting multiple microphones
CN114374404B (zh) * 2020-10-14 2024-01-02 瑞昱半导体股份有限公司 无线收发器的校正方法及校正电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278522A (en) * 1992-11-19 1994-01-11 Codex, Corp. High frequency voltage controlled oscillator
JP3565281B2 (ja) * 1993-10-08 2004-09-15 ソニー株式会社 受信機
TW408525B (en) * 1998-10-09 2000-10-11 Ind Tech Res Inst A transceiver device which could switch rapidly the receiving/transmitting mode
US6960962B2 (en) * 2001-01-12 2005-11-01 Qualcomm Inc. Local oscillator leakage control in direct conversion processes
WO2002084859A1 (en) * 2001-04-18 2002-10-24 Nokia Corporation Balanced circuit arrangement and method for linearizing such an arrangement
US7657241B2 (en) * 2002-02-01 2010-02-02 Qualcomm, Incorporated Distortion reduction calibration
US7127716B2 (en) * 2002-02-13 2006-10-24 Hewlett-Packard Development Company, L.P. Method of load balancing a distributed workflow management system
US20050124311A1 (en) * 2003-12-03 2005-06-09 Farsheed Mahmoudi Low-voltage low-power high-linearity active CMOS mixer
EP1751849B1 (de) * 2004-05-13 2013-11-06 ST-Ericsson SA Gegentaktmischer unter verwendung von kalibrierung der last-impedanz
US7177616B2 (en) * 2004-08-13 2007-02-13 Freescale Semiconductor, Inc. High linearity and low noise CMOS mixer and signal mixing method

Also Published As

Publication number Publication date
US8160533B2 (en) 2012-04-17
CN101416381A (zh) 2009-04-22
JP2009531930A (ja) 2009-09-03
EP2005575A2 (de) 2008-12-24
WO2007113733A2 (en) 2007-10-11
JP4682335B2 (ja) 2011-05-11
US20090305648A1 (en) 2009-12-10
WO2007113733A3 (en) 2007-12-06
CN101416381B (zh) 2012-07-25

Similar Documents

Publication Publication Date Title
EP2005575B1 (de) Selbstkalibrierender mischer
US7873342B2 (en) Low IF receiver of rejecting image signal and image signal rejection method
JP5335995B2 (ja) 位相調整用集積回路および通信ユニット
MXPA04008636A (es) Tecnicas de calibracion para sintetizadores de frecuencia.
US20160013816A1 (en) Adaptive/Configurable Intermediate Frequency (IF) Wireless Receiver And Bluetooth Device Using The Same
US4955077A (en) Radio with broad band automatic gain control circuit
US5604465A (en) Adaptive self-calibration for fast tuning phaselock loops
US8736249B2 (en) High frequency power detector circuit and radio communication device
US7498888B2 (en) Method and arrangement for interference compensation in a voltage-controlled frequency generator
US7450925B2 (en) Receiver for wireless communication systems and I/Q signal phase difference correction method therefor
US9094021B2 (en) Semiconductor device and variation information obtaining program
US6999012B2 (en) Temperature compensation device for automatic gain control loop
US20050141636A1 (en) Modulator and semiconductor integrated circuit including modulator and wired or wireless communication device including modulator and semiconductor device
US20010006356A1 (en) Voltage controlled oscillator assembly
US20040012441A1 (en) RF power amplifier digital gain flattening over multiband frequencies
US20100220820A1 (en) Receiver with Mixed-Mode Automatic Gain Control
EP1556968B1 (de) Ein integrierter hochsignalpegeldetektor anwendbar für die automatische pegelregelung
US20060094387A1 (en) Method and system for a second order input intercept point (IIP2) correction
JP2002217763A (ja) 入力レベル表示方法、入力レベル表示装置
WO2007044126A2 (en) System and method of transmitter power detection
JP2007027942A (ja) 位相制御方法及び位相制御発振装置、送信用アレーアンテナ
US20060093072A1 (en) Method and system for process, voltage, and temperature (PVT) correction
KR100338643B1 (ko) 위상동기루프에서 위상잡음을 감소시키기 위한 장치
JPH03145339A (ja) Ａｍラジオ受信機
JP3064981B2 (ja) 送信電力自動制御回路

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20081030

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20091028

DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20160523

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 839091

Country of ref document: AT

Kind code of ref document: T

Effective date: 20161115

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602007048370

Country of ref document: DE

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 11

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20161019

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

REG Reference to a national code

Ref country code: DE

Ref legal event code: R082

Ref document number: 602007048370

Country of ref document: DE

Representative=s name: GRUENECKER PATENT- UND RECHTSANWAELTE PARTG MB, DE

Ref country code: DE

Ref legal event code: R081

Ref document number: 602007048370

Country of ref document: DE

Owner name: OCT CIRCUIT TECHNOLOGIES INTERNATIONAL LTD., IE

Free format text: FORMER OWNER: NXP B.V., EINDHOVEN, NL

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 839091

Country of ref document: AT

Kind code of ref document: T

Effective date: 20161019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170120

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20170221

Year of fee payment: 11

Ref country code: DE

Payment date: 20170222

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170219

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170220

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20170224

Year of fee payment: 11

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602007048370

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170119

26N No opposition filed

Effective date: 20170720

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170331

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170327

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170327

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602007048370

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20180327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181002

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20070327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161019