Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F17/00—Fixed inductances of the signal type
  • H01F17/0006—Printed inductances
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F17/00—Fixed inductances of the signal type
  • H01F17/0006—Printed inductances
  • H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F27/00—Details of transformers or inductances, in general
  • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
  • H01F27/346—Preventing or reducing leakage fields
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09218—Conductive traces
  • H05K2201/09254—Branched layout

Definitions

• This patent document relates generally to techniques for reducing interference in a circuit, and more particularly to techniques using magnetically differential inductors to reduce interference in a circuit.
• interference can cause problems with the operation of circuits. Interference can therefore make the design of a system difficult. For example, in a circuit where inductors are used, the inductors can interfere with other components in the circuit.
• CMOS complementary metal-oxide semiconductor
• RF radio- frequency
• the transceiver's circuitry typically includes sensitive components susceptible to interference with other components.
• communication standards relating to the operation of the transceiver set requirements for noise, output power, spectral emission, etc., of the transceiver.
• An apparatus of the present invention includes an inductor formed by two or more conductive loops, wherein the conductive loops are configured such that magnetic fields generated are at least partially canceled.
• Another embodiment of the invention provides a method of reducing interference in a circuit including forming an inductance using two or more inductors, with the inductors arranged such that current flows through the inductors in different directions to at least partially cancel magnetic fields generated from the inductors.
• Another embodiment of the invention provides a method of minimizing interference between circuitry on an integrated circuit, including forming an inductance on the integrated circuit using to or more conductive loops coupled together.
• the conductive loops define a first axis extending through the conductive loops and a second axis perpendicular to the first axis, hi this example, the method includes configuring the conductive loops such that current flows in opposite directions through some of the loops to at least partially cancel magnetic fields generated from the loops, and such that magnetic cancellation is maximized at locations along the second axis.
• the relative positions circuitry is configured to . achieve a desired amount of magnetic cancellation.
• FIG. 1 is a diagram representing an inductor having a single loop.
• FIG. 2 shows two magnetically differential inductors coupled in series.
• FIG. 3 is an equivalent circuit diagram of the inductors shown in FIG. 2.
• FIG. 4 A shows another example two magnetically differential inductors coupled in series.
• FIG. 4B shows an example four magnetically differential inductors coupled in series.
• FIG. 5 shows another example of series coupled magnetically differential inductors.
• FIG. 6 shows another example of series coupled magnetically differential inductors.
• FIG. 7 shows two magnetically differential inductors coupled in parallel.
• FIG. 8 is an equivalent circuit diagram of the inductors shown in FIG. 7.
• FIG. 9 is a diagram illustrating a first and second current loop.
• FIG. 10 is a diagram showing magnetically differential inductors and a current loop.
• FIG. 11 is a diagram illustrating a single inductor with similar properties to the inductors shown in FIG. 10.
• FIG. 12 is a series coupled magnetically differential inductor.
• FIG. 13 is a parallel coupled magnetically differential inductor.
• FIGS. 14-15 show other examples of series coupled magnetically differential inductors.
• FIGS. 16-17 show other examples of parallel coupled magnetically differential inductors.
• FIGS. 18-24 show circuitry formed on an integrated circuit to illustrate layout techniques of the present invention.
• An IC utilizing techniques of the present invention may be used for any desired application, including wireless transmission systems such as mobile or cellular communication devices or other wireless devices. Note, however, that the present invention may be used in any other application where it is desirable to reduce or minimize interference in a circuit formed on a printed circuit board, an IC, or any other type of package.
• an RF apparatus takes the form of an RF receiver or transceiver for a high performance communication system.
• Such an apparatus may include various blocks of circuitry that perform the various functions of the RF apparatus.
• circuitry blocks in an RF transceiver may include digital processing circuitry, voltage controlled oscillator (VCO) circuitry, antenna interface circuitry, transmit circuitry, receive circuitry, etc.
• VCO voltage controlled oscillator
• the VCO circuitry may include one or more inductors that may interfere with digital circuitry in another circuitry block. Interference can result from both intentional loops (e.g., an inductance included in a design) and parasitic loops (e.g., inductances resulting from the routing of conductors in a circuit). For the RF apparatus to function properly and meet the applicable specifications, the interference and noise needs to be reduced or minimized to a desirable level.
• the present invention provides techniques for overcoming interference effects.
• an inductance can be formed in numerous ways.
• an inductor can be formed by one or more turns of a conductive loops.
• an inductor can be formed on one or more layers of the IC.
• an inductance may result from the routing of conductive traces used to connect components together in a device.
• inductors having multiple turns are used to increase the inductance in a given area or to improve the Q (inductor quality factor) of the inductor.
• Q inductor quality factor
• One disadvantage of multiple turns is that the added resistance can be significant, reducing the Q of the inductor.
• the present invention addresses the problem of interference by designing inductive structures in such a way that magnetic fields generated by the structures is at least partially canceled.
• One feature of the invention relates to configuring inductive structures such that the inductive structures function as magnetically differential inductors.
• a magnetically differential inductive structure may take the form of two or more inductors configured so that current flows in opposite directions (e.g., clockwise in one inductor and counterclockwise in the other inductor). With current flowing in opposite directions in two similar inductors, the magnetic fields created by the current flowing through the inductors will at least partially cancel each other out.
• there are many ways of configuring a magnetically differential inductive structure there are many ways of configuring a magnetically differential inductive structure.
• inductor designs use inductors with one loop where a single loop provides the most desired properties.
• the present invention utilizes structures with two differential loops, in order to reduce or minimize noise and interference with other components in a device.
• structures can be used with more than two loops, where the combination of loops are configured to at least partially cancel the magnetic fields generated by all of the loops.
• a first example of a differential inductive structure uses two series coupled inductors configured such that current flows in the opposite direction in each of the inductors.
• a second example of a differential inductive structure uses two parallel coupled inductors configured such that current flows in the opposite direction in each of the inductors.
• each type of structure has advantages over the other type, depending on the specific application.
• FIG. 1 is a diagram representing an inductor 10 having a single loop with terminals 12 and 14.
• FIG. 1 also shows the relative dimensions of the inductor 10, which define the area A of the inductor 10.
• the direction of current I that flows through the inductor 10 is also shown in FIG. 1.
• FIG. 2 shows first and second inductors 1OA and 1OB coupled in series between terminals 12 and 14.
• the inductors 1OA and 1OB are each half the size of the inductor 10.
• the inductors 1 OA and 1 OB can be thought of as inductor 10 broken at the dashed line, flipped vertically, with their ends joined.
• FIG. 3 is an equivalent circuit diagram of the inductors 1OA and 1OB, showing the series connection, and the direction of the current through the inductors 1OA and 1OB.
• the inductors 1OA and 1OB are arranged in an approximate figure-eight pattern (as are the series coupled examples described below).
• inductors 1OA and 1OB Since the sum of the areas of inductors 1OA and 1OB are equal to the area of the inductor 10 shown in FIG. 1, the inductance between terminals 12 and 14 will be the same as the inductance of inductor 10.
• the total resistance of inductors 1OA and 1OB may be slightly greater than the resistance of inductor 10, due to the increased length of the conductors (by approximately 4X, where X represents a length, and 4X represents four times the length X).
• FIG. 4A shows another example of series coupled magnetically differential inductors.
• FIG. 4A shows first and second inductors 1OC and 1OD coupled in series between terminals 12 and 14. Like the example shown in FIG. 2, the inductors 1OC and 1OD are each half the size of the inductor 10 shown in FIG. 1.
• An equivalent circuit diagram of the example shown in FIG. 4 would be similar to the diagram shown in FIG. 3.
• the inductance between terminals 12 and 14 will be the same as the inductance of inductor 10.
• the total resistance of inductors 1OC and 1OD maybe slightly greater than the resistance of inductor 10, due to the increased length of the conductors (by approximately 2X).
• a comparison of the single loop inductor 10 shown in FIG. 1 with the series coupled loops 1OC and 1OD will be similar to the comparison discussed above.
• the inductance (first order) will be the same.
• the Q should be a little worse in the series coupled inductors, but perhaps better than the example shown in FIG. 2.
• the magnetic fields generated by inductors 1OC and 1OD are at least partially cancelled.
• any desired number of loops can be used, where the combination of loops are configured to at least partially cancel the magnetic fields generated by the loops.
• FIG. 4B shows another example of series coupled magnetically differential inductors. Instead of two series loops, the examples shown in FIG. 4B includes four series loops.
• FIG. 4B shows four inductors 1OC, 10D, 1OE, and 1OF coupled in series between terminals 12 and 14.
• An equivalent circuit diagram of the example shown in FIG. 4B would be similar to the diagram shown in FIG. 3, with the addition of series connected inductors 1OE and 1OF.
• FIG. 5 shows another example of series coupled magnetically differential inductors.
• FIG. 5 shows first and second inductors 1OG and 1OH coupled in series between terminals 12 and 14.
• the inductors 1OG and 1OH are round, rather than rectangular.
• An equivalent circuit diagram of the example shown in FIG. 5 would be similar to the diagram shown in FIG. 3. If the sum of the areas of inductors 1OG and 1OH shown in FIG. 5 are equal to the area of the inductor 10 shown in FIG. 1, then the inductance between terminals 12 and 14 will be the same as the inductance of inductor 10.
• the magnetic fields generated by inductors 1OG and 1OH will at least partially cancel since the inductors are configured such that current I flows in opposite directions through the inductors 1OG and 1OH.
• FIG. 6 shows another example of series coupled magnetically differential inductors.
• FIG. 6 shows first and second inductors 101 and 10J coupled in series between terminals 12 and 14.
• the inductors 101 and 10J each have a hexagonal, rather than a rectangular shape.
• An equivalent circuit diagram of the example shown in FIG. 6 would be similar to the diagram shown in FIG. 3. If the sum of the areas of inductors 101 and 10J shown in FIG. 6 are equal to the area of the inductor 10 shown in FIG. 1, then the inductance between terminals 12 and 14 will be the same as the inductance of inductor 10.
• the magnetic fields generated by inductors 101 and 10J will at least partially cancel since the inductors are configured such that current I flows in opposite directions through the inductors 101 and 10J.
• FIG. 7 shows first and second inductors 16 and 18 coupled in parallel between terminals 20 and 22.
• the inductors 16 and 18 are each half the size of the inductor 10 shown in FIG. 1.
• the inductors 16 and 18 can be thought of as the inductor 10 of FIG. 1 broken at the dashed line, with the current direction changed in one of the halves. Note that other configurations of parallel coupled loops are also possible.
• FIG. 8 is an equivalent circuit diagram of the inductors 16 and 18, showing the parallel connection, and the direction of the currents I 1 and I 2 through the inductors 16 and
• the total magnetic field from the inductors 16 and 18 will at least partially cancel out.
• the amount of magnetic field cancellation depends on factors such as the distance from the magnetically differential inductors 16 and 18, as well as the direction from the magnetically differential inductors. These two factors are discussed in detail below.
• FIG. 9 is a diagram illustrating a first current loop 30 and a second current loop 32.
• the current loop 30 has a radius SL 1 and an area A 1 .
• the current loop 32 has a radius S 2 and an area A 2 .
• loops 30 and 32 are separated by a distance R.
• the magnetic field resulting from current flowing through loop 30 is illustrated by the following equation:
• FIG. 10 is a diagram showing series coupled inductors 34 and 36, like the series coupled inductors described above. Note that for clarity, FIG. 10 (and some of the following examples) does not show terminals, but terminals similar to those shown in FIG. 2 will be used in an actual device.
• the inductors 34 and 36 each have an area A 1 , and are configured such that current flows through the inductors 34 and 36 in opposite directions, as shown by the arrows. Since magnetic cancellation is optimal where the distance to each of the inductors 34 and 36 is equal (i.e., where the two opposite magnetic fields will be equal), an axis 38 is defined where magnetic cancellation is optimal. At all points along axis 38, the distance to each of the inductors 34 and 36 is equal.
• a second axis 40 is perpendicular to the axis 38 and extends through the centers of both inductors 34 and 36.
• the least amount of magnetic cancellation will be found along axis 40, since one inductor or the other is closer, and therefore will not be completely canceled by the other.
• the knowledge of where the optimal and worse case directions for magnetic cancellation occur is useful when designing a circuit layout (discussed below). Note that examples where an inductive structure has a large number of loops, there may be multiple directions with good magnetic cancellation.
• FIG. 10 also shows a loop 42, which may be a part of a component located elsewhere on an IC or circuit board. As shown, the loop 42 is located along the axis 40, putting the loop 42 at the worst possible angle for magnetic cancellation of inductors 34 and 36. Knowing that loop 42 is at the worst possible angle will enable the calculation of the effectiveness of the worst case magnetic cancellation at various distances.
• the loop 42 is at a distance R 1 from inductor 34, and at a distance R 2 from inductor 36.
• M DIFF the difference in mutual inductance
• R — (i.e., the average distance between the inductors 34 and 36
• equation (5) can be expressed as:
• FIG. 11 is a diagram illustrating a single loop 44 having the same area as the sum of inductors 34 and 36. Referring back to equation (3), the mutual inductance (M ONELOOP ) between inductor 44 and the
• loop 42 can be shows as:
• Table I is a table illustrating the values of
• ⁇ R is assumed to be 300 ⁇ m, which is
• One aspect of the present invention relates to the efficient and effective layout of a device, for example, an RF apparatus using CMOS technologies. Where interference is a concern, the present invention enables inductors to be used that reduce or minimize the magnetic fields generated by the inductors. In addition, by knowing where the magnetic cancellation has the greatest effect in a device, components of the device can be designed accordingly to place interfering components in optimal locations relative to the inductors. Further, by changing the geometries of the magnetically differential inductors, the axis of maximum cancellation (e.g., axis 38 in FIG. 10) can be moved and pointed toward a desired direction (described below).
• the axis of maximum cancellation e.g., axis 38 in FIG. 10
• FIG. 12 shows series coupled inductors 50 and 52, which are similar to the inductors 34 and 36 shown in FIG. 10.
• the inductors 50 and 52 each have an area A 1 , and are configured such that current flows through the inductors 50 and 52 in opposite directions, as shown by the arrows. Since magnetic field cancellation is optimal where the distance to each of the inductors 34 and 36 is equal, the axis 38 is defined where magnetic cancellation is optimal.
• the second axis 40 is perpendicular to the axis 38 and extends roughly through the centers of both inductors 50 and 52.
• FIG. 13 shows parallel coupled inductors 54 and 56, which are similar to the inductors 16 and 18 shown in FIG. 7.
• the inductors 54 and 56 also each have an area A 1 , and are configured such that current flows through the inductors 54 and 56 in opposite directions, as shown by the arrows.
• the axis 38 is defined where magnetic cancellation is optimal.
• the second axis 40 is perpendicular to the axis 38 and extends roughly through the centers of both inductors 54 and 56.
• FIG. 13 illustrates that some of the concepts discussed below apply to both series and parallel coupled magnetically differential inductors, although most of the following examples show series coupled inductors.
• the axis of maximum cancellation (axis 38) can be moved and pointed toward a desired direction.
• FIG. 14 shows series coupled inductors 5OA and 52A, which are similar to inductors 50 and 52 in FIG. 12, but with a different configuration.
• the inductors 50A and 52A each have the same area A 1 as inductors 50 and 52, but have different
• the inductors 50A and 52 A are elongated in the horizontal direction (relative to the view shown in FIG. 14). Since the areas A 1 of inductors 50 and 52 are the same as the areas A 1 of inductors 5OA and 52A, the inductances are the same. However, despite having the same inductance as inductors 50 and 52, the axis 38 in FIG. 14 is offset relative to the axis 38 shown in FIG. 12. Like the examples above, the distance from any point along axis 38 to the inductors 50A and 52 A are equal (e.g., from a point on the axis 38 to the center point of each inductor). As shown, the axis 38 in FIG. 14 is
• FIG. 15 illustrates another example of magnetically differential inductors.
• FIG. 15 shows series coupled inductors 5OB and 52B, which are similar to the inductors shown in FIGS. 12 and 14, but with yet another configuration.
• the inductors 5OB and 52B each have the same area A 1 as inductors 50 and 52, but have
• the inductors 5OB and 52B are elongated in the vertical direction (relative to the view shown in FIG. 15). Since the areas A 1 of inductors 50 and 52 are the same as the areas A 1 of inductors 5OB and 52B, the inductances are the same. However, despite having the same inductance as inductors 50 and 52, the axis 38 in FIG. 15 is offset relative to the axis 38 shown in FIG. 12. Like the examples above, the distance from any point along axis 38 to the inductors 5OB and 52B are equal (e.g., from a point on the axis 38 to the center point of each
• the axis 38 in FIG. 15 is + ⁇ 2 degrees relative to the angle of the
• FIGS. 14 and 15 illustrate examples of how magnetically differential inductors can be configured to point the axis 38 an any desired direction. Note that, in all of the examples shows, inductors can be configured as mirror images, pointing the axis 38 in different quadrants.
• FIG. 16 shows parallel coupled inductors 54A and 56A, which are similar to inductors 54 and 56 in FIG. 13, but with a different configuration.
• the inductors 54A and 56A each have the same dimensions and area A 1 as inductors 54 and 56, but are
• the axis 38 in FIG. 16 is offset relative to the axis 38 shown in FIG. 13. Like the examples above, the distance from any point along axis 38 to the inductors 54A and 56A are equal (e.g., from a point on the axis 38 to
• FIG. 17 shows parallel coupled inductors 54B and 56B, which are similar to inductors 54 and 56 in FIG. 13, but with yet another configuration.
• the inductors 54B and 56B each have the same area A 1 as inductors 54 and 56, but are offset. Since the
• inductors 54 and 56 are the same as the areas A 1 of inductors 54B and 56B, the inductances are the same.
• the inductors 54B and 56B are offset as before, but also different dimensions, hi this example, the inductors 54B and 56B are elongated in the vertical direction (relative to the view shown in FIG. 17).
• the axis 38 in FIG. 17 is offset relative to the axis 38 shown in FIG. 13.
• the distance from any point along axis 38 to the inductors 54B and 56B are equal (e.g., from a point on the axis 38 to the center point
• An RF apparatus such as an RF transceiver, may include various blocks of analog and digital circuitry.
• various interference problems can arise.
• one or more inductors used on a voltage controlled oscillator (VCO) circuitry may cause interference with digital circuitry located elsewhere on the IC.
• VCO voltage controlled oscillator
• using magnetically differential inductors may solve the interference problem.
• the inductors and overall layout may need to be adjusted to bring interference down to a suitable level. Following are examples of such adjustments.
• FIG. 18 is a diagram representing an IC 60 having several blocks of circuitry used in an RF apparatus.
• FIG. 18 shows VCO circuitry 62, and other blocks of circuitry 64, 66, and 68. Circuitry in other areas of the IC 60 is not shown.
• the present invention can apply to any desired type of circuit and circuit partition.
• the VCO circuitry 62 required one or more inductances.
• the VCO inductances tend to interfere with digital circuitry found in circuit blocks 64, 66, and/or 68.
• a first technique for reducing interference between the VCO circuitry 62 and the other circuit is to position the VCO circuitry 62 far away from circuitry in which interference is a concern.
• the inductor(s) provided in the VCO circuitry 62 can be magnetically differential inductors, such as those described above, to reduce the amount of interference.
• the configuration of the inductor(s) and the layout of the IC 60 can be changed to optimize the configuration.
• inductances (whether intentional or parasitic) present in both interfering circuitry can be configured to reduce the amount of interference. For example, if an intentional inductor in the VCO circuitry 62 interferes with a parasitic inductance in another circuit block, magnetically differential inductors can be utilized by both the intentional inductor and by the parasitic inductance.
• FIG. 19 shows the IC 60 with magnetically differential inductors 70, for example, like the inductors shown in FIG. 12. Note that the inductors are not necessarily drawn to scale, and are enlarged to illustrate the techniques of the invention. Also, the box shown around VCO circuitry 62 in FIG. 18 has been removed for clarity. As mentioned above, assume that, even with the magnetically differential inductors 70, interference with one or more of the circuitry blocks is a concern. As shown, and as was described in detail above, magnetic cancellation by the inductors 70 is greatest along axis 38.
• circuitry blocks and/or the inductors 70 can be moved. Now assume that interference between the VCO 62 and the block of circuitry 64 is a problem.
• FIG. 20 shows an example where the layout is changed based on the location of axis 38. As shown in FIG. 20, the block of circuitry 64 has been moved so that it is located along the axis 38 (the axis of optimal magnetic cancellation).
• FIG. 21 shows an example where the configuration of the magnetically differential inductors is altered to minimize interference with circuitry 64.
• magnetically differential inductors 7OA are configured in such a way that the axis 38 points toward the circuitry 64 (e.g., see FIG. 14), thus reducing the interference between the VCO circuitry 62 and the circuitry 64.
• FIG. 22 shows another example where the configuration of the magnetically differential inductors, and the layout of the IC 60 is altered to minimize interference between the VCO 62 and other circuitry on the IC 60.
• FIG. 22 shows an example where circuitry blocks 64 and 66 are positioned near each other.
• the magnetically differential inductors 7OB are configured such that the axis 38 points toward both blocks of circuitry 64 and 66. If one of the blocks is more of a concern that the other, the configuration of the inductors, and/or the position of the circuitry blocks can be tweaked such that the axis 38 is closer to the circuitry that is more of a concern.
• multiple circuitry blocks can be positioned along the axis 38.
• FIG. 23 shows an example that is the same as that shown in FIG. 22, except that parallel coupled magnetically differential inductors 7OC are used in place of series coupled inductors. As shown, the inductors 7OC are configured to point the axis 38 to both blocks of circuitry 64 and 66.
• FIG. 24 shows an example like FIG. 21, where the configuration of the magnetically differential inductors is altered to minimize interference with circuitry 64.
• magnetically differential inductors 7OA are configured in such a way that the axis 38 points toward the circuitry 64 (e.g., see FIG. 14), thus reducing the interference between the VCO circuitry 62 and the circuitry 64.
• a parasitic inductance in the block of circuitry 64 is configured with magnetically differential loops 72.
• the magnetically differential loops 72 are also configured so that the axis of optimal cancellation 38 points toward the magnetically differential inductors 7OA.
• the concept of magnetically differential inductors can be applied to any circuitry where interference is a concern.
• a large digital component can be divided into two smaller components with one of the smaller components oriented opposite the other component, such that the magnetic fields from one component at least partially cancel the magnetic fields from the other component.
• the digital component could also be divided into four (or more) smaller components.
• driver circuitry can comprise two smaller driver circuits, where the two driver circuits are arranged as mirror images of each other, so that magnetic fields generated by the circuits are at least partially cancelled.
• circuitry can comprise four circuits arranged in separate quadrants, and arranged in such a way that magnetic fields are canceled (i.e., in two groups of mirrored images).
• circuitry can be comprised of other numbers of circuit portions arranged in ways that achieve some level of magnetic cancellation. These techniques can be used for any type of circuitry where magnetic cancellation is desired.

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