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EP1851747B1 - Pixel addressing circuit and method of controlling such circuit - Google Patents

Pixel addressing circuit and method of controlling such circuit Download PDF

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Publication number
EP1851747B1
EP1851747B1 EP06709335A EP06709335A EP1851747B1 EP 1851747 B1 EP1851747 B1 EP 1851747B1 EP 06709335 A EP06709335 A EP 06709335A EP 06709335 A EP06709335 A EP 06709335A EP 1851747 B1 EP1851747 B1 EP 1851747B1
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EP
European Patent Office
Prior art keywords
addressing
transistor
gate
transistors
actuating
Prior art date
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EP06709335A
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German (de)
French (fr)
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EP1851747A1 (en
Inventor
Walid Benzarti
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation

Definitions

  • the invention also relates to a method for controlling such an addressing circuit.
  • OLEDs are flat screens that utilize the luminescent properties of organic light emitting diodes. Unlike liquid crystal displays (LCDs), which are addressed in voltage, the OLED type diodes are addressed in current. In order to operate OLED displays with the same conventional addressing structures used for LCD displays, a voltage-to-current converter circuit must be used.
  • a conventional structure for controlling a pixel consists of two transistors T1, T2, for example of the MOSFET type, of a capacitor C and a diode D, of the OLED type.
  • Transistor T1 is an actuating transistor, operating analogically as a voltage controlled current generator.
  • the actuating transistor T1 is connected in series with the diode D across a supply voltage Vcc. It converts an actuating voltage Vg1 applied to its gate, in current flowing in the diode D.
  • the capacitor C is connected between the gate of the actuating transistor T1 and a fixed potential, for example ground, the supply voltage Vcc or another potential.
  • the transistor T2 is a switching transistor, intended to determine whether the pixel is selected or not, operating in a digital binary manner, namely with a conduction position and a blocking position.
  • the switching transistor T2 is controlled by an addressing voltage Vg2 applied to its gate, passing the transistor T2 from its conduction position to its blocking position and vice versa.
  • the switching transistor T2, for addressing the diode D of the pixel is connected between data signals Vd and the gate of the actuating transistor T1.
  • the data signals Vd are thus transmitted to the gate of the transistor actuating circuit T1, when the switching transistor T2 is conducting, which transforms these voltage signals into current for controlling the intensity of the illumination of the diode D.
  • Transistors T1 and T2 are preferably NMOS in amorphous silicon, thin film type (TFT, "Thin Film Transistor”).
  • TFT thin film type
  • the use of amorphous silicon for the fabrication of the transistor T1 can, however, cause a degradation of this transistor, during the addressing of the diode D, since the operating transistor T1 operates as a current generator for more than 95% the addressing time of the pixel.
  • This degradation of the actuating transistor T1 essentially results in a drift of its threshold voltage Vt.
  • Several factors are behind this drift. The first is due to the diffusion of the hydrogen in the amorphous silicon, when the actuating transistor T1 is in operation, and the second, much more preponderant, is due to the injection of carriers into the insulator of the gate of the actuating transistor T1, in this case nitride. Indeed, these carriers are stored in the nitride and play a role of memory effect modifying the threshold voltage Vt of the actuating transistor T1.
  • the document US 2004/0001037 proposes a circuit for decreasing the drift of the threshold voltage of the actuating transistor of a standard control structure of a pixel, via a modified addressing system.
  • the voltage applied to the drain of the operating transistor, in series with the diode, of the OLED type varies as a function of the voltage applied to the gate of the actuating transistor.
  • the aim of the invention is to overcome these drawbacks and to provide a pixel addressing circuit for optimizing the reliability of the transistors and the time-dependent operation of the addressing circuit.
  • Another object of the invention is to provide a simple and easy control method for implementing such an addressing circuit.
  • the method is characterized in that it comprises, during one or more data frames, the application, on the gates of the first and second switching transistors, of addressing voltages, capable of rendering, respectively, blocked and passing the associated operating transistors, so as to pass one of the operation transistors in one addressing and control phase of the diode and the other operating transistor in a repair phase, and alternatively during one or more subsequent data frames.
  • the addressing circuit 1 of a pixel comprises a first control circuit a constituted by a structure according to the prior art.
  • a first actuating transistor T1a is thus connected in series with the organic light-emitting diode D, across the supply voltage Vcc.
  • An operating voltage Vg1a is applied to the gate of the first actuating transistor T1a.
  • the first control circuit a also comprises a first capacitor Ca, connected between the gate of the first actuating transistor T1a and a fixed potential, for example the ground, in the particular embodiment of the figure 2 .
  • a first switching transistor T2a controlled by an addressing voltage Vg2a, between a conduction position and a blocking position, is connected between first data signals Vda and the gate of the first actuating transistor T1a.
  • the addressing circuit 1 comprises a second control circuit b, identical in structure to the first control circuit a, comprising a second actuating transistor T1b, connected in series with the diode D across the supply voltage Vcc.
  • a second capacitor Cb is connected between the gate of the second actuating transistor T1b and a fixed potential, for example ground.
  • An operating voltage Vg1b is applied to the gate of the second actuating transistor T1b.
  • the second control circuit b also comprises a second switching transistor T2b, controlled by an addressing voltage Vg2b applied to its gate, and connected between second data signals Vdb and the gate of the second operating transistor T1b.
  • the data signals Vda and Vdb and the addressing voltages Vg2a and Vg2b of the switching transistors T2a and T2b are supplied by a control circuit 2 (FIG. figure 2 ), allowing both to control the addressing of the diode D and alternatively the repair of the actuating transistors T1a and T1b.
  • the first and second switching transistors T2a, T2b are connected to two separate outputs of the control circuit 2. This can then provide them, respectively, different addressing voltages Vg2a, Vg2b.
  • a voltage capable of blocking this transistor is temporarily applied, during a repair phase, to this gate. This voltage must be lower than the voltages at the source and the drain of this transistor.
  • a negative voltage is applied to the gate of the actuating transistor T1a. This causes the removal of carriers that have been injected into the nitride.
  • the diode D While the actuating transistor T1a is in the repair phase, the diode D is controlled by the second actuating transistor T1b, which is in the addressing phase and operates as a current generator. For this, it receives on its grid positive Vg1b actuation signals.
  • the control circuits (a or b) While one of the control circuits (a or b) is intended for the addressing and control of the diode D, the other control circuit (b or a) repairs its operating transistor, unsolicited for addressing and controlling diode D.
  • the second actuating transistor T1b is in repair. It is then blocked and only a very weak current, less than 10 -10 A, flows in its channel. The voltage at its terminals then influences neither the first operating transistor T1a nor the good operation of the diode D. Conversely, when the diode D is addressed and controlled via the second operating transistor T1b, the first transistor T1a is under repair and the voltage at its terminals does not influence the second actuating transistor T1b or the proper operation of the diode D.
  • the gates of the operating transistors T1a and T1b are connected to the voltages Vda and Vdb, respectively, via the first and second switching transistors T2a and T2b.
  • the control circuit 2 simultaneously applies a positive data voltage Vda, intended to control the diode D, to the drain of the switching transistor T2a of the first circuit a control circuit and a negative Vdb data voltage, for the repair of the gate of the actuating transistor T1b, on the drain of the second switching transistor T2b of the second control circuit b.
  • control circuit 2 supplies positive Vda and Vdb data signals so that the drive transistor T1a goes into the repair phase while the second actuation transistor T2b, previously repaired, then goes into the addressing and control phase of the diode D.
  • each pixel 4 is addressed by an addressing circuit 1 according to the figure 2 and the control circuit 2 of each pixel 4 comprises a first circuit 5a for addressing the rows of the matrix 3, arranged, for example, to the left of the matrix 3, and a second circuit 5b for addressing the rows of the matrix 3, arranged, for example, to the right of the matrix 3.
  • the control circuit 2 also comprises a first circuit 6a for addressing the columns of the matrix 3, arranged, for example, at the top of the matrix 3, and a second circuit 6b for addressing the columns of the matrix 3 arranged, for example, at the bottom of the matrix 3.
  • circuits 5a and 6a are respectively connected to the gate and the drain of the switching transistor T2a of each pixel 4 and respectively provide the addressing voltages Vg2a and the data signals Vda of each pixel 4.
  • circuits 5b and 6b are respectively connected to the gate and the drain of the switching transistor T2b of each pixel 4 and respectively provide the addressing voltages Vg2b and the data signals Vdb of each pixel 4.
  • the Figures 3 and 4 illustrate the state of the matrix 3 during two successive operating frames.
  • the circuit 5a for addressing the lines and the circuit 6a for addressing the columns are intended alternatively to the addressing and the control of the diodes of the pixels 4 ( figure 3 ) and the repair of the operating transistors T1a of the diodes D of the pixels 4 ( figure 4 ).
  • the row addressing circuit 5b and the column addressing circuit 6b are intended, alternatively, to repair the operating transistors T1b of the diodes D of the pixels 4 (FIG. figure 3 ) and to address and control the diodes D of the pixels 4 ( figure 4 ).
  • circuits 5a and 5b for addressing the rows of the matrix 3 and two circuits 6a and 6b for addressing the columns of the matrix 3 represents a solution allowing the greatest latitude of polarization of the matrix. 3. Furthermore, the particular structure of the addressing circuits 1 facilitates the arrangement according to the matrix 3, because it is easy to connect additional transistors to already existing addressing circuits.
  • the operation of the addressing circuit 1 consists in simultaneously applying, respectively during the same frame and alternately in two successive frames, adjacent or not, signals of opposite polarities on the grids of the actuating transistors T1a and T1b of the addressing circuit 1.
  • the first control circuit a is first intended for the addressing and control of the diode D, during the frame N, while the second control circuit b is simultaneously intended for the repair of the gate of the transistor actuator T1b.
  • the voltage Vg2a applied to the gate of the first switching transistor T2a is positive, for example of the order of 15V
  • the data signals Vda applied to the drain of the switching transistor T2a are order of 10V.
  • the control circuit 2 applies a voltage, for example, of the order of 35V for a predetermined duration of the frame, up to a time t2, making the driver first switching transistor T2a ( figure 5 ).
  • Vda data signals ( figure 6 ), which can oscillate between 15V and 30V, are then transmitted (Vg1a, figure 7 ) to the gate of the actuating transistor T1a, which then starts to control the diode D. Indeed, as shown in FIG.
  • the voltage Vg1a thus remains at 30V until a time t4 corresponding to the end of the frame N and at the beginning of the frame N + 1.
  • the actuating transistor T1a thus remains in the addressing and control phase of the diode D during the entire duration (t1 to t4) of the frame N.
  • the voltage Vg2b applied to the gate of the second switching transistor T2b goes to 10V, at time t1, then to - 10V, at time t2, before returning to 0V at a time t3 just before the moment t4.
  • the control circuit 2 applies on the drain of the transistor T2b negative Vdb data signals, for example of the order of -10V, from the beginning of the frame N, between the instant t1 and the instant t3.
  • the voltage Vg1b, applied on the gate of the second actuating transistor T1b then goes to -10V for the entire duration (t1 to t4) of the frame N, which thus corresponds to the repair phase of the second actuating transistor T1b, which remains blocked during this entire period.
  • the control circuit 2 then supplies Vda data signals of the order of -10V and the voltage Vg2a applied to the gate of the first switching transistor T2a goes to 10V up to a time t5.
  • the transistor T2a is then conductive and transmits the negative voltage of the signals Vda to the gate of the first actuating transistor T1a.
  • the voltage Vg1a applied to the gate of the first actuating transistor T1a thus quickly takes the value -10V.
  • the second switching transistor T2b becomes conductive, for example by applying a voltage Vg2b of the order of 35V, while the data signals Vdb are positive and can oscillate, for example, between 15V and 30V.
  • the transistor T2b is thus conductive at the beginning of this N + 1 frame and the voltage Vg1b applied to the gate of the operating transistor T1b becomes positive, of the order of 30V. It retains this value until the end of the N + 1 frame at time t6, thanks to the presence of the capacitor Cb.
  • the addressing signals Vg2a turn on the first switching transistor T2a and thus transmit on the gate of the operating transistor T1a the data signals Vda, able to operate this transistor. in current generator.
  • the voltage Vg1 remains substantially constant throughout the duration of the frame and controls the illumination of the diode D.
  • the voltage Vg2b applied during this frame to the gate of the operating transistor T1b blocks this transistor and allows the repair of the gate of the actuating transistor T1b.
  • the switching transistors T2a and T2b are made conductive because the voltage Vg2a is of the order of 10V and the voltage Vg2b is of the order of 35V, while the Vdb data signals turn on the drive transistor T1b and Vda data signals make blocking the drive transistor T1a.
  • the first control circuit then passes in turn in the repair phase of the first operating transistor T1a, while the second control circuit b in turn goes into the addressing and control phase of the diode D.
  • each control circuit being alternately intended for the repair of its actuating transistor and the addressing and control of the diode during the duration of one or more frames.
  • the operation is therefore very simple and facilitated by the use of addressing circuits comprising two identical control circuits.
  • the invention is not limited to the various embodiments described above.
  • the values of the voltages are not limited to those indicated above and the operation is identical with other values compatible with the type and the dimensions of the operating transistors T1a and T1b and of switching T2a and T2b.
  • the polarity of the voltages may possibly be modified, as long as the general principle of the addressing circuit 1 is retained, namely with a phase of repair and a phase of addressing and control of the diode performed simultaneously, respectively and alternatively, by each control circuit.
  • a feedback system can be installed by placing photodiodes in a few pixels 4, in order to change over time, depending on the luminance of the screen, the value of the blocking voltage.
  • This type of addressing circuit for the repair of amorphous silicon transistors can be envisaged in any application using this type of transistor in continuous or quasi-continuous operation as a generator. current, in an analog type circuit.
  • the main applications are, for example, medical imaging, microfluidics, etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The pixel addressing circuit comprises two actuating transistors connected in series with a same diode to the terminals of a supply voltage, and two switching transistors each comprising a gate and respectively connected between data signals and the gate of the associated actuating transistors. The gates of the switching transistors are connected to two distinct outputs of a control circuit supplying them with different addressing voltages. The method for controlling the addressing circuit consists in applying addressing voltages to the gates of the switching transistors, which voltages are able to respectively turn the associated actuating transistors off and on so as to make one of the actuating transistors switch to an addressing and control phase of the diode and to make the other actuating transistor switch to a repair phase.

Description

Domaine technique de l'inventionTechnical field of the invention

L'invention concerne un circuit d'adressage de pixels comprenant, pour chaque pixel, des premier et second circuits de contrôle comportant respectivement :

  • des premier et second transistors d'actionnement, en silicium amorphe, comportant chacun une grille et connectés chacun en série avec une diode électroluminescente organique aux bornes d'une tension d'alimentation,
  • des premier et second transistors de commutation, comportant chacun une grille et connectés respectivement entre des premier et second signaux de données et la grille des premier et second transistors d'actionnement associés,
  • des premier et second condensateurs, connectés respectivement entre la grille des premier et second transistors d'actionnement et une des bornes de la tension d'alimentation,
le circuit d'adressage contrôlant les premier et second transistors de commutation, pour rendre les premier et second transistors d'actionnement, simultanément, respectivement et alternativement, bloqué et passant.The invention relates to a pixel addressing circuit comprising, for each pixel, first and second control circuits respectively comprising:
  • first and second actuating transistors, of amorphous silicon, each having a gate and each connected in series with an organic light-emitting diode across a supply voltage,
  • first and second switching transistors, each having a gate and connected respectively between first and second data signals and the gate of the associated first and second driving transistors,
  • first and second capacitors respectively connected between the gate of the first and second actuating transistors and one of the terminals of the supply voltage,
the addressing circuit controlling the first and second switching transistors, for rendering the first and second actuating transistors simultaneously, respectively and alternately, locked and passing.

L'invention concerne également un procédé de contrôle d'un tel circuit d'adressage.The invention also relates to a method for controlling such an addressing circuit.

État de la techniqueState of the art

Les écrans à diodes électroluminescentes organiques (OLED, "Organic Light Emission Displays") sont des écrans plats qui utilisent les propriétés de luminescence de diodes organiques émettrices de lumière. Contrairement aux écrans à cristaux liquides (LCD), qui sont adressés en tension, les diodes de type OLED sont adressées en courant. Afin de faire fonctionner les écrans OLED avec les mêmes structures d'adressage classiques employées pour les écrans LCD, il faut utiliser un circuit convertisseur tension-courant.Organic Light Emitting Displays (OLEDs) are flat screens that utilize the luminescent properties of organic light emitting diodes. Unlike liquid crystal displays (LCDs), which are addressed in voltage, the OLED type diodes are addressed in current. In order to operate OLED displays with the same conventional addressing structures used for LCD displays, a voltage-to-current converter circuit must be used.

Comme représenté sur la figure 1, une structure classique de commande d'un pixel se compose de deux transistors T1, T2, par exemple de type MOSFET, d'un condensateur C et d'une diode D, de type OLED. Le transistor T1 est un transistor d'actionnement, fonctionnant de manière analogique comme un générateur de courant contrôlé en tension. Le transistor d'actionnement T1 est connecté en série avec la diode D aux bornes d'une tension d'alimentation Vcc. Il convertit une tension d'actionnement Vg1 appliquée sur sa grille, en courant circulant dans la diode D. Le condensateur C est relié entre la grille du transistor d'actionnement T1 et un potentiel fixe, par exemple la masse, la tension d'alimentation Vcc ou un autre potentiel.As shown on the figure 1 a conventional structure for controlling a pixel consists of two transistors T1, T2, for example of the MOSFET type, of a capacitor C and a diode D, of the OLED type. Transistor T1 is an actuating transistor, operating analogically as a voltage controlled current generator. The actuating transistor T1 is connected in series with the diode D across a supply voltage Vcc. It converts an actuating voltage Vg1 applied to its gate, in current flowing in the diode D. The capacitor C is connected between the gate of the actuating transistor T1 and a fixed potential, for example ground, the supply voltage Vcc or another potential.

Le transistor T2 est un transistor de commutation, destiné à déterminer si le pixel est ou non sélectionné, fonctionnant de manière numérique binaire, à savoir avec une position de conduction et une position de blocage. Le transistor de commutation T2 est commandé par une tension d'adressage Vg2, appliquée sur sa grille, faisant passer le transistor T2 de sa position de conduction à sa position de blocage et réciproquement. Le transistor de commutation T2, permettant l'adressage de la diode D du pixel, est connecté entre des signaux de données Vd et la grille du transistor d'actionnement T1. Les signaux de données Vd sont ainsi transmis à la grille du transistor d'actionnement T1, lorsque le transistor de commutation T2 est conducteur, qui transforme ces signaux de tension en courant destiné à contrôler l'intensité de l'éclairage de la diode D.The transistor T2 is a switching transistor, intended to determine whether the pixel is selected or not, operating in a digital binary manner, namely with a conduction position and a blocking position. The switching transistor T2 is controlled by an addressing voltage Vg2 applied to its gate, passing the transistor T2 from its conduction position to its blocking position and vice versa. The switching transistor T2, for addressing the diode D of the pixel, is connected between data signals Vd and the gate of the actuating transistor T1. The data signals Vd are thus transmitted to the gate of the transistor actuating circuit T1, when the switching transistor T2 is conducting, which transforms these voltage signals into current for controlling the intensity of the illumination of the diode D.

Les transistors T1 et T2 sont, de préférence, des NMOS en silicium amorphe, du type à films minces (TFT, "Thin Film Transistor"). L'utilisation de silicium amorphe pour la fabrication du transistor T1 peut cependant provoquer une dégradation de ce transistor, au cours de l'adressage de la diode D, car le transistor d'actionnement T1 fonctionne comme un générateur de courant pendant plus de 95% du temps d'adressage du pixel.Transistors T1 and T2 are preferably NMOS in amorphous silicon, thin film type (TFT, "Thin Film Transistor"). The use of amorphous silicon for the fabrication of the transistor T1 can, however, cause a degradation of this transistor, during the addressing of the diode D, since the operating transistor T1 operates as a current generator for more than 95% the addressing time of the pixel.

Cette dégradation du transistor d'actionnement T1 se traduit essentiellement par une dérive de sa tension de seuil Vt. Plusieurs facteurs sont à l'origine de cette dérive. Le premier est dû à la diffusion de l'hydrogène dans le silicium amorphe, lorsque le transistor d'actionnement T1 est en fonctionnement, et le deuxième, beaucoup plus prépondérant, est dû à l'injection de porteurs dans l'isolant de la grille du transistor d'actionnement T1, en l'occurrence du nitrure. En effet, ces porteurs sont stockés dans le nitrure et jouent un rôle d'effet mémoire modifiant la tension de seuil Vt du transistor d'actionnement T1.This degradation of the actuating transistor T1 essentially results in a drift of its threshold voltage Vt. Several factors are behind this drift. The first is due to the diffusion of the hydrogen in the amorphous silicon, when the actuating transistor T1 is in operation, and the second, much more preponderant, is due to the injection of carriers into the insulator of the gate of the actuating transistor T1, in this case nitride. Indeed, these carriers are stored in the nitride and play a role of memory effect modifying the threshold voltage Vt of the actuating transistor T1.

Pour remédier à cette dégradation, le document US 2004/0001037 propose un circuit permettant de diminuer la dérive de la tension de seuil du transistor d'actionnement d'une structure standard de commande d'un pixel, par l'intermédiaire d'un système d'adressage modifié. En particulier, la tension appliquée au drain du transistor d'actionnement, en série avec la diode, de type OLED, varie en fonction de la tension appliquée à la grille du transistor d'actionnement.To remedy this deterioration, the document US 2004/0001037 proposes a circuit for decreasing the drift of the threshold voltage of the actuating transistor of a standard control structure of a pixel, via a modified addressing system. In particular, the voltage applied to the drain of the operating transistor, in series with the diode, of the OLED type varies as a function of the voltage applied to the gate of the actuating transistor.

Cependant, même si un tel circuit permet de diminuer la dérive de la tension de seuil du transistor d'actionnement, il ne permet pas de réparer le transistor d'actionnement, à savoir augmenter sa durée de vie et optimiser son fonctionnement.However, even if such a circuit makes it possible to reduce the drift of the threshold voltage of the actuating transistor, it does not make it possible to repair the operating transistor, namely to increase its life and optimize its operation.

L'article « Polarity-Balanced Driving to Reduce VTH Shift in a-Si for Active-Matrix OLEDs » de You B-H et al. (2004 Sid International Symposium Digest of Technical Papers, Seattle, May 25-27, 2004 ), décrit un circuit d'adressage permettant d'améliorer le fonctionnement de ses transistors. Le circuit comporte deux transistors d'actionnement et quatre transistors de commutation fonctionnant avec un adressage en mode pair et impair.Article "Polarity-Balanced Driving to Reduce VTH Shift in a-Si for Active-Matrix OLEDs" by You BH et al. (2004 Sid International Symposium Digest of Technical Papers, Seattle, May 25-27, 2004 ), describes an addressing circuit for improving the operation of its transistors. The circuit comprises two actuating transistors and four switching transistors operating with even and odd mode addressing.

Cependant, le nombre des transistors et le fonctionnement du circuit imposent des modes d'adressage spécifiques et différents pour les transistors. Il en résulte un fonctionnement non optimal du circuit d'adressage et une dégradation des transistors est toujours observée.However, the number of transistors and the operation of the circuit impose specific and different addressing modes for the transistors. This results in a non-optimal operation of the addressing circuit and degradation of the transistors is always observed.

Objet de l'inventionObject of the invention

L'invention a pour but de remédier à ces inconvénients et a pour objet la réalisation d'un circuit d'adressage de pixels permettant d'optimiser la fiabilité des transistors et le fonctionnement dans le temps du circuit d'adressage.The aim of the invention is to overcome these drawbacks and to provide a pixel addressing circuit for optimizing the reliability of the transistors and the time-dependent operation of the addressing circuit.

Le but de l'invention est atteint par les revendications annexées et, plus particulièrement, par le fait que les grilles des premier et second transistors de commutation sont connectées à deux sorties distinctes d'un circuit de commande leur fournissant des tensions d'adressage différentes.The object of the invention is achieved by the appended claims and, more particularly, by the fact that the gates of the first and second switching transistors are connected to two separate outputs of a control circuit providing them with different addressing voltages. .

L'invention a également pour but un procédé de contrôle simple et facile à mettre en oeuvre d'un tel circuit d'adressage.Another object of the invention is to provide a simple and easy control method for implementing such an addressing circuit.

En particulier, le procédé est caractérisé en ce qu'il comporte, pendant une ou plusieurs trames de données, l'application, sur les grilles des premier et second transistors de commutation, des tensions d'adressage, aptes à rendre, respectivement, bloqué et passant les transistors d'actionnement associés, de manière à faire passer l'un des transistors d'actionnement dans une phase d'adressage et de contrôle de la diode et l'autre transistor d'actionnement dans une phase de réparation, et alternativement pendant une ou plusieurs trames de données suivantes.In particular, the method is characterized in that it comprises, during one or more data frames, the application, on the gates of the first and second switching transistors, of addressing voltages, capable of rendering, respectively, blocked and passing the associated operating transistors, so as to pass one of the operation transistors in one addressing and control phase of the diode and the other operating transistor in a repair phase, and alternatively during one or more subsequent data frames.

Description sommaire des dessinsBrief description of the drawings

D'autres avantages et caractéristiques ressortiront plus clairement de la description qui va suivre de modes particuliers de réalisation de l'invention donnés à titre d'exemples non limitatifs et représentés aux dessins annexés, dans lesquels :

  • La figure 1 illustre une structure classique d'un circuit de commande d'un pixel selon l'art antérieur.
  • La figure 2 illustre un mode particulier de réalisation d'un circuit d'adressage de pixels selon l'invention.
  • Les figures 3 et 4 illustrent une matrice de pixels, composée de lignes et de colonnes, commandés chacun par un circuit d'adressage selon la figure 2, respectivement pour une trame de données N et pour une trame de données suivante N+1.
  • Les figures 5 à 10 illustrent en fonction du temps le fonctionnement des transistors à différents points du circuit d'adressage selon la figure 2, lors de deux trames de données successives N et N+1.
Other advantages and features will emerge more clearly from the following description of particular embodiments of the invention given by way of non-limiting example and represented in the accompanying drawings, in which:
  • The figure 1 illustrates a conventional structure of a control circuit of a pixel according to the prior art.
  • The figure 2 illustrates a particular embodiment of a pixel addressing circuit according to the invention.
  • The Figures 3 and 4 illustrate a matrix of pixels, composed of rows and columns, each controlled by an addressing circuit according to the figure 2 respectively for an N data frame and for a next N + 1 data frame.
  • The Figures 5 to 10 illustrate, as a function of time, the operation of the transistors at different points of the addressing circuit according to the figure 2 in two successive data frames N and N + 1.

Description de modes particuliers de réalisationDescription of particular embodiments

Sur la figure 2, le circuit d'adressage 1 d'un pixel comprend un premier circuit de contrôle a, constitué par une structure selon l'art antérieur. Un premier transistor d'actionnement T1a est ainsi connecté en série avec la diode électroluminescente organique D, aux bornes de la tension d'alimentation Vcc. Une tension d'actionnement Vg1 a est appliquée sur la grille du premier transistor d'actionnement T1a. Le premier circuit de contrôle a comprend également un premier condensateur Ca, connecté entre la grille du premier transistor d'actionnement T1a et un potentiel fixe, par exemple la masse, dans le mode particulier de réalisation de la figure 2. Un premier transistor de commutation T2a, commandé par une tension d'adressage Vg2a, entre une position de conduction et une position de blocage, est connecté entre des premiers signaux de données Vda et la grille du premier transistor d'actionnement T1a.On the figure 2 , the addressing circuit 1 of a pixel comprises a first control circuit a constituted by a structure according to the prior art. A first actuating transistor T1a is thus connected in series with the organic light-emitting diode D, across the supply voltage Vcc. An operating voltage Vg1a is applied to the gate of the first actuating transistor T1a. The first control circuit a also comprises a first capacitor Ca, connected between the gate of the first actuating transistor T1a and a fixed potential, for example the ground, in the particular embodiment of the figure 2 . A first switching transistor T2a, controlled by an addressing voltage Vg2a, between a conduction position and a blocking position, is connected between first data signals Vda and the gate of the first actuating transistor T1a.

Le circuit d'adressage 1 comporte un second circuit de contrôle b, de structure identique au premier circuit de contrôle a, comportant un second transistor d'actionnement T1b, connecté en série avec la diode D aux bornes de la tension d'alimentation Vcc. Un second condensateur Cb est connecté entre la grille du second transistor d'actionnement T1b et un potentiel fixe, par exemple la masse. Une tension d'actionnement Vg1b est appliquée sur la grille du second transistor d'actionnement T1b. Le second circuit de contrôle b comprend également un second transistor de commutation T2b, commandé par une tension d'adressage Vg2b, appliquée sur sa grille, et connecté entre des seconds signaux de données Vdb et la grille du second transistor d'actionnement T1b.The addressing circuit 1 comprises a second control circuit b, identical in structure to the first control circuit a, comprising a second actuating transistor T1b, connected in series with the diode D across the supply voltage Vcc. A second capacitor Cb is connected between the gate of the second actuating transistor T1b and a fixed potential, for example ground. An operating voltage Vg1b is applied to the gate of the second actuating transistor T1b. The second control circuit b also comprises a second switching transistor T2b, controlled by an addressing voltage Vg2b applied to its gate, and connected between second data signals Vdb and the gate of the second operating transistor T1b.

Les signaux de données Vda et Vdb et les tensions d'adressage Vg2a et Vg2b des transistors de commutation T2a et T2b sont fournis par un circuit de commande 2 (figure 2), permettant à la fois de contrôler l'adressage de la diode D et alternativement la réparation des transistors d'actionnement T1a et T1b.The data signals Vda and Vdb and the addressing voltages Vg2a and Vg2b of the switching transistors T2a and T2b are supplied by a control circuit 2 (FIG. figure 2 ), allowing both to control the addressing of the diode D and alternatively the repair of the actuating transistors T1a and T1b.

Dans le mode particulier de réalisation de la figure 2, les premier et second transistors de commutation T2a, T2b sont connectés à deux sorties distinctes du circuit de commande 2. Celui-ci peut alors leur fournir, respectivement, des tensions d'adressage Vg2a, Vg2b différentes.In the particular embodiment of the figure 2 , the first and second switching transistors T2a, T2b are connected to two separate outputs of the control circuit 2. This can then provide them, respectively, different addressing voltages Vg2a, Vg2b.

Par ailleurs, dans une variante de réalisation non représentée, les premier et second transistors de commutation T2a, T2b peuvent être alimentés par des signaux de données Vda, Vdb identiques (Vda=Vdb). Une telle configuration permet alors de limiter le nombre de signaux à acheminer dans le circuit d'adressage 1.Furthermore, in a variant embodiment not shown, the first and second switching transistors T2a, T2b can be powered by identical data signals Vda, Vdb (Vda = Vdb). Such a configuration then makes it possible to limit the number of signals to be routed in the addressing circuit 1.

Afin de réparer la dégradation de la tension de seuil observée sur la grille du transistor d'actionnement T1a, une tension apte à bloquer ce transistor est appliquée temporairement, pendant une phase de réparation, sur cette grille. Il faut que cette tension soit inférieure aux tensions au niveau de la source et du drain de ce transistor. À titre d'exemple, une tension négative est appliquée sur la grille du transistor d'actionnement T1a. Ceci provoque l'enlèvement des porteurs qui ont été injectés dans le nitrure.In order to repair the degradation of the threshold voltage observed on the gate of the operating transistor T1a, a voltage capable of blocking this transistor is temporarily applied, during a repair phase, to this gate. This voltage must be lower than the voltages at the source and the drain of this transistor. By way of example, a negative voltage is applied to the gate of the actuating transistor T1a. This causes the removal of carriers that have been injected into the nitride.

Pendant que le transistor d'actionnement T1a est en phase de réparation, la diode D est contrôlée par le second transistor d'actionnement T1b, qui est en phase d'adressage et fonctionne en générateur de courant. Pour cela, il reçoit sur sa grille des signaux d'actionnement Vg1b positifs. Ainsi, tandis que l'un des circuits de contrôle (a ou b) est destiné à l'adressage et au contrôle de la diode D, l'autre circuit de contrôle (b ou a) répare son transistor d'actionnement, non sollicité pour l'adressage et le contrôle de la diode D.While the actuating transistor T1a is in the repair phase, the diode D is controlled by the second actuating transistor T1b, which is in the addressing phase and operates as a current generator. For this, it receives on its grid positive Vg1b actuation signals. Thus, while one of the control circuits (a or b) is intended for the addressing and control of the diode D, the other control circuit (b or a) repairs its operating transistor, unsolicited for addressing and controlling diode D.

Ainsi, lorsque la diode D est adressée et contrôlée par l'intermédiaire du premier transistor d'actionnement T1a, le second transistor d'actionnement T1b est en réparation. Il est alors bloqué et seul un courant très faible, inférieur à 10-10A, circule dans son canal. La tension à ses bornes n'influence alors ni le premier transistor d'actionnement T1a ni le bon fonctionnement de la diode D. Inversement lorsque la diode D est adressée et contrôlée par l'intermédiaire du second transistor d'actionnement T1b, le premier transistor d'actionnement T1a est en réparation et la tension à ses bornes n'influence ni le second transistor d'actionnement T1b ni le bon fonctionnement de la diode D.Thus, when the diode D is addressed and controlled via the first actuating transistor T1a, the second actuating transistor T1b is in repair. It is then blocked and only a very weak current, less than 10 -10 A, flows in its channel. The voltage at its terminals then influences neither the first operating transistor T1a nor the good operation of the diode D. Conversely, when the diode D is addressed and controlled via the second operating transistor T1b, the first transistor T1a is under repair and the voltage at its terminals does not influence the second actuating transistor T1b or the proper operation of the diode D.

Dans le mode de réalisation préférentiel de la figure 2, les grilles des transistors d'actionnement T1a et T1b sont connectées aux tensions Vda et Vdb, respectivement, par l'intermédiaire des premier et second transistors de commutation T2a et T2b. À titre d'exemple, pendant une trame N des signaux de données Vda et Vdb, le circuit de commande 2 applique simultanément une tension de données Vda positive, destinée à contrôler la diode D, sur le drain du transistor de commutation T2a du premier circuit de contrôle a et une tension de données Vdb négative, destinée à la réparation de la grille du transistor d'actionnement T1b, sur le drain du second transistor de commutation T2b du second circuit de contrôle b.In the preferred embodiment of the figure 2 , the gates of the operating transistors T1a and T1b are connected to the voltages Vda and Vdb, respectively, via the first and second switching transistors T2a and T2b. By way of example, during a frame N of the data signals Vda and Vdb, the control circuit 2 simultaneously applies a positive data voltage Vda, intended to control the diode D, to the drain of the switching transistor T2a of the first circuit a control circuit and a negative Vdb data voltage, for the repair of the gate of the actuating transistor T1b, on the drain of the second switching transistor T2b of the second control circuit b.

Lors d'une trame ultérieure, par exemple lors de la trame N+1 suivante, le circuit de commande 2 fournit des signaux de données Vda négatifs et Vdb positifs, afin que le transistor d'actionnement T1a passe en phase de réparation pendant que le second transistor d'actionnement T2b, préalablement réparé, passe alors en phase d'adressage et de contrôle de la diode D.In a subsequent frame, for example in the next N + 1 frame, the control circuit 2 supplies positive Vda and Vdb data signals so that the drive transistor T1a goes into the repair phase while the second actuation transistor T2b, previously repaired, then goes into the addressing and control phase of the diode D.

Un tel circuit d'adressage 1 avec deux circuits de contrôle a et b identiques, associés à une seule diode D, permet donc d'effectuer simultanément, respectivement et alternativement, l'adressage et le contrôle de la diode D et la réparation des transistors d'actionnement T1a, T1b de cette diode D, afin d'améliorer la durée de fonctionnement du circuit d'adressage 1.Such an addressing circuit 1 with two control circuits a and b identical, associated with a single diode D, thus makes it possible to perform simultaneously, respectively and, alternately, the addressing and the control of the diode D and the repair of the operating transistors T1a, T1b of this diode D, in order to improve the duration of operation of the addressing circuit 1.

Sur les figures 3 et 4, une matrice 3, composée d'une pluralité de pixels 4 disposés selon une pluralité de lignes et de colonnes, représente un mode particulier d'agencement de pixels 4. Dans le mode particulier de réalisation représenté sur les figures 3 et 4, chaque pixel 4 est adressé par un circuit d'adressage 1 selon la figure 2 et le circuit de commande 2 de chaque pixel 4 comporte un premier circuit 5a d'adressage des lignes de la matrice 3, disposé, par exemple, à gauche de la matrice 3, et un second circuit 5b d'adressage des lignes de la matrice 3, disposé, par exemple, à droite de la matrice 3.On the Figures 3 and 4 , a matrix 3, composed of a plurality of pixels 4 arranged in a plurality of rows and columns, represents a particular mode of arrangement of pixels 4. In the particular embodiment shown in FIGS. Figures 3 and 4 each pixel 4 is addressed by an addressing circuit 1 according to the figure 2 and the control circuit 2 of each pixel 4 comprises a first circuit 5a for addressing the rows of the matrix 3, arranged, for example, to the left of the matrix 3, and a second circuit 5b for addressing the rows of the matrix 3, arranged, for example, to the right of the matrix 3.

Le circuit de commande 2 comporte également un premier circuit 6a d'adressage des colonnes de la matrice 3, disposé, par exemple, en haut de la matrice 3, et un second circuit 6b d'adressage des colonnes de la matrice 3, disposé, par exemple, en bas de la matrice 3.The control circuit 2 also comprises a first circuit 6a for addressing the columns of the matrix 3, arranged, for example, at the top of the matrix 3, and a second circuit 6b for addressing the columns of the matrix 3 arranged, for example, at the bottom of the matrix 3.

Sur les figures 3 et 4, les circuits 5a et 6a sont respectivement connectés à la grille et au drain du transistor de commutation T2a de chaque pixel 4 et fournissent respectivement les tensions d'adressage Vg2a et les signaux de donnés Vda de chaque pixel 4. De manière analogue, les circuits 5b et 6b sont connectés, respectivement, à la grille et au drain du transistor de commutation T2b de chaque pixel 4 et fournissent respectivement les tensions d'adressage Vg2b et les signaux de données Vdb de chaque pixel 4.On the Figures 3 and 4 the circuits 5a and 6a are respectively connected to the gate and the drain of the switching transistor T2a of each pixel 4 and respectively provide the addressing voltages Vg2a and the data signals Vda of each pixel 4. In a similar way, the circuits 5b and 6b are respectively connected to the gate and the drain of the switching transistor T2b of each pixel 4 and respectively provide the addressing voltages Vg2b and the data signals Vdb of each pixel 4.

Les figures 3 et 4 illustrent l'état de la matrice 3 lors de deux trames successives de fonctionnement. Le circuit 5a d'adressage des lignes et le circuit 6a d'adressage des colonnes sont destinés alternativement à l'adressage et au contrôle des diodes des pixels 4 (figure 3) et à la réparation des transistors d'actionnement T1a des diodes D des pixels 4 (figure 4). Simultanément, le circuit 5b d'adressage des lignes et le circuit 6b d'adressage des colonnes sont destinés, alternativement, à la réparation des transistors d'actionnement T1b des diodes D des pixels 4 (figure 3) et à l'adressage et au contrôle des diodes D des pixels 4 (figure 4).The Figures 3 and 4 illustrate the state of the matrix 3 during two successive operating frames. The circuit 5a for addressing the lines and the circuit 6a for addressing the columns are intended alternatively to the addressing and the control of the diodes of the pixels 4 ( figure 3 ) and the repair of the operating transistors T1a of the diodes D of the pixels 4 ( figure 4 ). At the same time, the row addressing circuit 5b and the column addressing circuit 6b are intended, alternatively, to repair the operating transistors T1b of the diodes D of the pixels 4 (FIG. figure 3 ) and to address and control the diodes D of the pixels 4 ( figure 4 ).

L'utilisation de deux circuits 5a et 5b d'adressage des lignes de la matrice 3 et de deux circuits 6a et 6b d'adressage des colonnes de la matrice 3 représente une solution permettant d'avoir la plus grande latitude de polarisation de la matrice 3. Par ailleurs, la structure particulière des circuits d'adressage 1 facilite l'agencement selon la matrice 3, car il est facile de connecter des transistors supplémentaires à des circuits d'adressage déjà existants.The use of two circuits 5a and 5b for addressing the rows of the matrix 3 and two circuits 6a and 6b for addressing the columns of the matrix 3 represents a solution allowing the greatest latitude of polarization of the matrix. 3. Furthermore, the particular structure of the addressing circuits 1 facilitates the arrangement according to the matrix 3, because it is easy to connect additional transistors to already existing addressing circuits.

Le fonctionnement du circuit d'adressage 1 selon la figure 2 va être décrit plus en détails au regard des figures 5 à 10. Comme décrit ci-dessus, le fonctionnement d'un tel circuit d'adressage 1 consiste à appliquer simultanément, respectivement lors d'une même trame et alternativement lors de deux trames successives, adjacentes ou non, des signaux de polarités opposées sur les grilles des transistors d'actionnement T1a et T1b du circuit d'adressage 1.The operation of the addressing circuit 1 according to the figure 2 will be described in more detail with regard to Figures 5 to 10 . As described above, the operation of such an addressing circuit 1 consists in simultaneously applying, respectively during the same frame and alternately in two successive frames, adjacent or not, signals of opposite polarities on the grids of the actuating transistors T1a and T1b of the addressing circuit 1.

À titre d'exemple, comme représenté sur les figures 5 à 10, le premier circuit de contrôle a est d'abord destiné à l'adressage et au contrôle de la diode D, au cours de la trame N, tandis que le second circuit de contrôle b est simultanément destiné à la réparation de la grille du transistor d'actionnement T1b. Comme représenté aux figures 5 et 6, à un instant t0, la tension Vg2a appliquée sur la grille du premier transistor de commutation T2a est positive, par exemple, de l'ordre de 15V, les signaux de données Vda, appliqués au drain du transistor de commutation T2a, sont de l'ordre de 10V. Au même instant, comme représenté aux figures 8 à 10, tandis que la tension d'actionnement Vg1a (figure 7) appliquée sur la grille du premier transistor d'actionnement T1a est alors de l'ordre de 10V, la tension Vg2b sur la grille du second transistor de commutation T2b et les signaux de données Vdb sont à 0V. La tension d'actionnement Vg1b appliquée sur la grille du second transistor d'actionnement T1b (figure 8) est alors également à 0V.For example, as shown on the Figures 5 to 10 , the first control circuit a is first intended for the addressing and control of the diode D, during the frame N, while the second control circuit b is simultaneously intended for the repair of the gate of the transistor actuator T1b. As represented in Figures 5 and 6 at a time t0, the voltage Vg2a applied to the gate of the first switching transistor T2a is positive, for example of the order of 15V, the data signals Vda applied to the drain of the switching transistor T2a are order of 10V. At the same time, as represented Figures 8 to 10 , while the actuating voltage Vg1a ( figure 7 ) applied on the gate of the first actuating transistor T1a is then of the order of 10V, the voltage Vg2b on the gate of the second switching transistor T2b and the data signals Vdb are at 0V. The operating voltage Vg1b applied to the gate of the second actuating transistor T1b ( figure 8 ) is then also at 0V.

À un instant t1, correspondant au début d'une trame N, le circuit de commande 2 applique une tension, par exemple, de l'ordre de 35V pendant une durée prédéterminée de la trame, jusqu'à un instant t2, rendant conducteur le premier transistor de commutation T2a (figure 5). Les signaux de données Vda (figure 6), qui peuvent osciller entre 15V et 30V, sont alors transmis (Vg1a, figure 7) à la grille du transistor d'actionnement T1a, qui commence alors à contrôler la diode D. En effet, comme représenté sur la figure 7, la tension Vg1a sur la grille du premier transistor d'actionnement T1a passe à 30 V à l'instant t1, correspondant à la valeur des signaux de données Vda pendant la période allant de l'instant t1 à l'instant t2 (figure 6).At a time t1, corresponding to the start of a frame N, the control circuit 2 applies a voltage, for example, of the order of 35V for a predetermined duration of the frame, up to a time t2, making the driver first switching transistor T2a ( figure 5 ). Vda data signals ( figure 6 ), which can oscillate between 15V and 30V, are then transmitted (Vg1a, figure 7 ) to the gate of the actuating transistor T1a, which then starts to control the diode D. Indeed, as shown in FIG. figure 7 , the voltage Vg1a on the gate of the first actuating transistor T1a goes to 30 V at the instant t1, corresponding to the value of the data signals Vda during the period from the instant t1 to the instant t2 ( figure 6 ).

Le retour du transistor de commutation T2a dans sa position bloquée à l'instant t2, lorsque sa tension d'adressage Vg2a redescend à une tension de l'ordre de 15V (figure 5), n'a pas d'influence sur la tension Vg1a appliquée sur la grille du premier transistor d'actionnement T1a (figure 7), grâce au condensateur Ca relié à la grille du transistor d'actionnement T1a. La tension Vg1a reste ainsi à 30V jusqu'à un instant t4 correspondant à la fin de la trame N et au début de la trame N+1. Le transistor d'actionnement T1a reste ainsi en phase d'adressage et de contrôle de la diode D pendant toute la durée (t1 à t4) de la trame N.The return of the switching transistor T2a in its locked position at time t2, when its addressing voltage Vg2a drops back to a voltage of the order of 15V ( figure 5 ), has no influence on the voltage Vg1a applied to the gate of the first actuating transistor T1a ( figure 7 ), thanks to the capacitor Ca connected to the gate of the actuating transistor T1a. The voltage Vg1a thus remains at 30V until a time t4 corresponding to the end of the frame N and at the beginning of the frame N + 1. The actuating transistor T1a thus remains in the addressing and control phase of the diode D during the entire duration (t1 to t4) of the frame N.

Comme représenté sur la figure 8, la tension Vg2b appliquée sur la grille du second transistor de commutation T2b passe à 10V, à l'instant t1, puis à - 10V, à l'instant t2, avant de revenir à 0V à un instant t3 précédent de peu l'instant t4.As shown on the figure 8 the voltage Vg2b applied to the gate of the second switching transistor T2b goes to 10V, at time t1, then to - 10V, at time t2, before returning to 0V at a time t3 just before the moment t4.

Simultanément, comme représenté sur la figure 9, le circuit de commande 2 applique sur le drain du transistor T2b des signaux de données Vdb négatifs, par exemple de l'ordre de -10V, dès le début de la trame N, entre l'instant t1 et l'instant t3. Comme illustré à la figure 10, la tension Vg1b, appliquée sur la grille du second transistor d'actionnement T1b, passe alors à -10V pendant toute la durée (t1 à t4) de la trame N, qui correspond ainsi à la phase de réparation du second transistor d'actionnement T1b, qui reste bloqué pendant toute cette période.Simultaneously, as shown on the figure 9 , the control circuit 2 applies on the drain of the transistor T2b negative Vdb data signals, for example of the order of -10V, from the beginning of the frame N, between the instant t1 and the instant t3. As illustrated in figure 10 the voltage Vg1b, applied on the gate of the second actuating transistor T1b, then goes to -10V for the entire duration (t1 to t4) of the frame N, which thus corresponds to the repair phase of the second actuating transistor T1b, which remains blocked during this entire period.

Peu avant la fin de la trame N, à l'instant t3, les tensions Vg2a (figure 5) et Vg2b (figure 8) appliquées sur les grilles des deux transistors de commutation T2a et T2b passent simultanément à 0V, pour préparer la trame suivante. Sur les figures 6 et 8, les signaux de données Vda du premier circuit de contrôle a restent à 10V, tandis que les signaux de données Vdb du second circuit de contrôle b passent à environ 15V (figure 8). Ces modifications n'ont pas d'influence sur les tensions Vg1a et Vg1b, car les transistors de commutation T2a et T2b sont alors tous deux bloqués.Shortly before the end of the frame N, at time t3, the voltages Vg2a ( figure 5 ) and Vg2b ( figure 8 ) applied to the gates of the two switching transistors T2a and T2b pass simultaneously to 0V, to prepare the next frame. On the figures 6 and 8 , the data signals Vda of the first control circuit a remain at 10V, while the data signals Vdb of the second control circuit b change to approximately 15V ( figure 8 ). These modifications have no influence on the voltages Vg1a and Vg1b, because the switching transistors T2a and T2b are then both blocked.

À l'instant t4, la trame N+1 commence. Comme représenté sur les figures 5 et 6, le circuit de commande 2 fournit alors des signaux de données Vda de l'ordre de -10V et la tension Vg2a appliquée sur la grille du premier transistor de commutation T2a passe à 10V jusqu'à un instant t5. Le transistor T2a est alors conducteur et transmet la tension négative des signaux Vda sur la grille du premier transistor d'actionnement T1a. Comme représenté sur la figure 7, la tension Vg1a appliquée sur la grille du premier transistor d'actionnement T1a prend ainsi rapidement la valeur -10V. Elle est maintenue à cette valeur, grâce au condensateur Ca, jusqu'à la fin de la trame N+1, à savoir à un instant t6, malgré le blocage du premier transistor de commutation T2a, à l'instant t5 où la tension Vg2a passe à une tension de l'ordre de -10V (figure 5).At time t4, the N + 1 frame begins. As shown on Figures 5 and 6 , the control circuit 2 then supplies Vda data signals of the order of -10V and the voltage Vg2a applied to the gate of the first switching transistor T2a goes to 10V up to a time t5. The transistor T2a is then conductive and transmits the negative voltage of the signals Vda to the gate of the first actuating transistor T1a. As shown on the figure 7 , the voltage Vg1a applied to the gate of the first actuating transistor T1a thus quickly takes the value -10V. It is maintained at this value, thanks to the capacitor Ca, until the end of the N + 1 frame, namely at a time t6, despite the blocking of the first switching transistor T2a, to the moment t5 where the voltage Vg2a goes to a voltage of the order of -10V ( figure 5 ).

Simultanément, comme représenté sur les figures 8 à 10, à l'instant t4, le second transistor de commutation T2b devient conducteur, par exemple par application d'une tension Vg2b de l'ordre de 35V, tandis que les signaux de données Vdb sont positifs et peuvent osciller, par exemple, entre 15V et 30V. Le transistor T2b est ainsi conducteur au début de cette trame N+1 et la tension Vg1 b appliquée sur la grille du transistor d'actionnement T1b devient positive, de l'ordre de 30V. Elle conserve cette valeur jusqu'à la fin de la trame N+1, à l'instant t6, grâce à la présence du condensateur Cb. En effet, le retour éventuel du transistor de commutation T2b dans sa position bloquée, à l'instant t5, lorsque la tension Vg2b passe à une valeur de l'ordre de 15 V (figure 8), n'a pas d'influence sur la tension Vg1b appliquée sur la grille du second transistor d'actionnement T1b.Simultaneously, as shown on Figures 8 to 10 at time t4, the second switching transistor T2b becomes conductive, for example by applying a voltage Vg2b of the order of 35V, while the data signals Vdb are positive and can oscillate, for example, between 15V and 30V. The transistor T2b is thus conductive at the beginning of this N + 1 frame and the voltage Vg1b applied to the gate of the operating transistor T1b becomes positive, of the order of 30V. It retains this value until the end of the N + 1 frame at time t6, thanks to the presence of the capacitor Cb. Indeed, the possible return of the switching transistor T2b in its locked position, at time t5, when the voltage Vg2b goes to a value of the order of 15 V ( figure 8 ), has no influence on the voltage Vg1b applied to the gate of the second actuating transistor T1b.

Ainsi, plus généralement, au début de la trame N, les signaux d'adressage Vg2a rendent conducteur le premier transistor de commutation T2a et transmettent ainsi sur la grille du transistor d'actionnement T1a les signaux de données Vda, aptes à faire fonctionner ce transistor en générateur de courant. La tension Vg1 a reste sensiblement constante pendant toute la durée de la trame et contrôle l'éclairage de la diode D. La tension Vg2b appliquée pendant cette trame à la grille du transistor d'actionnement T1b bloque ce transistor et permet la réparation de la grille du transistor d'actionnement T1b.Thus, more generally, at the beginning of the frame N, the addressing signals Vg2a turn on the first switching transistor T2a and thus transmit on the gate of the operating transistor T1a the data signals Vda, able to operate this transistor. in current generator. The voltage Vg1 remains substantially constant throughout the duration of the frame and controls the illumination of the diode D. The voltage Vg2b applied during this frame to the gate of the operating transistor T1b blocks this transistor and allows the repair of the gate of the actuating transistor T1b.

Lors de la trame suivante N+1, adjacente ou non, les transistors de commutation T2a et T2b sont rendus conducteurs, car la tension Vg2a est de l'ordre de 10V et la tension Vg2b est de l'ordre de 35V, tandis que les signaux de données Vdb rendent passant le transistor d'actionnement T1b et les signaux de données Vda rendent bloquant le transistor d'actionnement T1a. Le premier circuit de contrôle a passe alors à son tour en phase de réparation du premier transistor d'actionnement T1a, tandis que le second circuit de contrôle b passe à son tour en phase d'adressage et de contrôle de la diode D.During the next frame N + 1, adjacent or not, the switching transistors T2a and T2b are made conductive because the voltage Vg2a is of the order of 10V and the voltage Vg2b is of the order of 35V, while the Vdb data signals turn on the drive transistor T1b and Vda data signals make blocking the drive transistor T1a. The first control circuit then passes in turn in the repair phase of the first operating transistor T1a, while the second control circuit b in turn goes into the addressing and control phase of the diode D.

Le fonctionnement se poursuit ainsi, chaque circuit de contrôle étant alternativement destiné à la réparation de son transistor d'actionnement et à l'adressage et au contrôle de la diode, pendant la durée d'une ou plusieurs trames. Le fonctionnement est donc très simple et facilité par l'utilisation de circuits d'adressage comportant deux circuits de contrôle identiques.The operation continues thus, each control circuit being alternately intended for the repair of its actuating transistor and the addressing and control of the diode during the duration of one or more frames. The operation is therefore very simple and facilitated by the use of addressing circuits comprising two identical control circuits.

L'invention n'est pas limitée aux différents modes de réalisation décrits ci-dessus. Les valeurs des tensions ne sont pas limitées à celles indiquées ci-dessus et le fonctionnement est identique avec d'autres valeurs compatibles avec le type et les dimensions des transistors d'actionnement T1a et T1b et de commutation T2a et T2b. Les polarités des tensions peuvent éventuellement être modifiées, tant que le principe général du circuit d'adressage 1 est conservé, à savoir avec une phase de réparation et une phase d'adressage et de contrôle de la diode effectuées simultanément, respectivement et alternativement, par chaque circuit de contrôle.The invention is not limited to the various embodiments described above. The values of the voltages are not limited to those indicated above and the operation is identical with other values compatible with the type and the dimensions of the operating transistors T1a and T1b and of switching T2a and T2b. The polarity of the voltages may possibly be modified, as long as the general principle of the addressing circuit 1 is retained, namely with a phase of repair and a phase of addressing and control of the diode performed simultaneously, respectively and alternatively, by each control circuit.

Dans le cas d'un agencement des pixels 4 selon la matrice 3, comme représentée sur les figures 3 et 4, un système de contre-réaction peut être installé en plaçant des photodiodes dans quelques pixels 4, afin de modifier au cours du temps, en fonction de la luminance de l'écran, la valeur de la tension de blocage.In the case of an arrangement of the pixels 4 according to the matrix 3, as represented on the Figures 3 and 4 , a feedback system can be installed by placing photodiodes in a few pixels 4, in order to change over time, depending on the luminance of the screen, the value of the blocking voltage.

Ce type de circuit d'adressage permettant la réparation de transistors en silicium amorphe peut être envisagé dans toute application utilisant ce type de transistors en fonctionnement continu ou quasi continu en générateur de courant, dans un circuit de type analogique. Les principales applications sont, par exemple, l'imagerie médicale, la microfluidique, etc.This type of addressing circuit for the repair of amorphous silicon transistors can be envisaged in any application using this type of transistor in continuous or quasi-continuous operation as a generator. current, in an analog type circuit. The main applications are, for example, medical imaging, microfluidics, etc.

Il pourrait s'appliquer plus généralement à tout type de transistor dont la tension de seuil dérive dans le temps dans ce type de fonctionnement, pour des raisons analogues à celles observées pour des transistors en silicium amorphes.It could be applied more generally to any type of transistor whose threshold voltage drifts over time in this type of operation, for reasons similar to those observed for amorphous silicon transistors.

Claims (10)

  1. Addressing circuit (1) of pixels (4) comprising, for each pixel (4), first (a) and second (b) control circuits respectively comprising:
    - first (T1a) and second (T1b) actuating transistors made from amorphous silicon, each comprising a gate and each connected in series with an organic light-emitting diode (D) to the terminals of a supply voltage,
    - first (T2a) and second (T2b) switching transistors, each comprising a gate and respectively connected between first (Vda) and second (Vdb) data signals and the gate of the associated first (T1a) and second actuating transistors (T1b),
    - first (Ca) and second (Cb) capacitors, respectively connected between the gate of the first (T1a) and second (T1b) actuating transistors and one of the supply voltage terminals,
    the addressing circuit (1) controlling the first (T2a) and second (T2b) switching transistors to simultaneously, respectively and alternately turn the first (T1a) and second (T1b) actuating transistors off and on,
    addressing circuit characterized in that the gates of the first and second switching transistors (T2a, T2b) are connected to two distinct outputs of a control circuit (2) supplying them with different addressing voltages (Vg2a, Vg2b).
  2. Addressing circuit according to claim 1, characterized in that the pixels (4) being arranged in the form of an array (3) of lines and columns, the control circuit (2) comprises:
    - first (5a) and second (5b) line addressing circuits, arranged on each side of the array (3) and respectively connected to the first data signals (Vda) of the first switching transistor (T2a) and to the second data signals (Vdb) of the second switching transistor (T2b),
    - and first (6a) and second (6b) column addressing circuits, arranged on each side of the array (3) and respectively connected to the gate of the first switching transistor (T2a) and to the gate of the second switching transistor (T2b).
  3. Addressing circuit according to one of claims 1 and 2, characterized in that the first (T2a) and second (T2b) switching transistors are supplied by identical data signals (Vda, Vdb).
  4. Method for controlling an addressing circuit (1) according to any one of claims 1 to 3, characterized in that it comprises application, during one or more data frames (N), of the addressing voltages (Vg2a, Vg2b) to the gates of the first (T2a) and second (T2b) switching transistors, which voltages are able to turn the associated actuating transistors (T1a, T1b) respectively off and on so as to make one of the actuating transistors (T1a, T1b) switch to an addressing and control phase of the diode (D) and to make the other actuating transistor (T1a, T1b) switch to a repair phase, and alternately during one or more subsequent data frames (N+1).
  5. Method according to claim 4, characterized in that, during a first predetermined period corresponding to the beginning of a frame, the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) on takes a first positive value, greater than the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) off.
  6. Method according to claim 5, characterized in that the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) on is about 35V and the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) off is about 10V.
  7. Method according to one of claims 5 and 6, characterized in that the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) on takes a second positive value during a second predetermined period.
  8. Method according to claim 7, characterized in that the addressing voltage (Vg2a, Vg2b) applied to the gate of the switching transistor (T2a, T2b) able to turn the associated actuating transistor (T1a, T1b) off simultaneously takes a negative value during said second predetermined period.
  9. Method according to claim 8, characterized in that said second positive value is about 15V and said negative value is about -10V.
  10. Method according to any one of claims 4 to 9, characterized in that the addressing voltages (Vg2a, Vg2b) applied to the gates of the first (T2a) and second (T2b) switching transistors are simultaneously equal to zero during a third predetermined period corresponding to the end of a frame.
EP06709335A 2005-02-21 2006-02-16 Pixel addressing circuit and method of controlling such circuit Not-in-force EP1851747B1 (en)

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FR0501731A FR2882457B1 (en) 2005-02-21 2005-02-21 PIXEL ADDRESSING CIRCUIT AND METHOD FOR CONTROLLING SUCH CIRCUIT
PCT/FR2006/000363 WO2006087477A1 (en) 2005-02-21 2006-02-16 Pixel addressing circuit and method of controlling one such circuit

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JP2008216542A (en) * 2007-03-02 2008-09-18 Seiko Epson Corp Organic semiconductor device driving method, electro-optical device, electro-optical device driving method, and electronic apparatus
US20100141646A1 (en) * 2007-07-23 2010-06-10 Pioneer Corporation Active matrix display device
WO2009098802A1 (en) * 2008-02-08 2009-08-13 Sharp Kabushiki Kaisha Pixel circuit and display device
KR101374443B1 (en) * 2008-10-10 2014-03-17 엘지디스플레이 주식회사 Organic Light Emitting Diode Display
JP2010224033A (en) * 2009-03-19 2010-10-07 Toshiba Corp Display device and driving method of display device
JP5282970B2 (en) * 2009-07-14 2013-09-04 ソニー株式会社 Display device, driving method thereof, and electronic apparatus
TWI571058B (en) 2011-05-18 2017-02-11 半導體能源研究所股份有限公司 Semiconductor device and method of driving the same
JP5930654B2 (en) * 2011-10-17 2016-06-08 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． Electro-optical device and driving method of electro-optical device
TWI708234B (en) * 2018-12-25 2020-10-21 友達光電股份有限公司 Display device and driving method thereof
CN109859682B (en) * 2019-03-28 2021-01-22 京东方科技集团股份有限公司 Driving circuit, driving method thereof and display device
JP2021071593A (en) 2019-10-30 2021-05-06 キヤノン株式会社 Display device, information display device, and electronic device
CN114627804B (en) * 2022-03-28 2023-08-01 武汉华星光电技术有限公司 Pixel circuit and display panel
CN115294934B (en) * 2022-10-09 2023-01-06 惠科股份有限公司 Display panel, display module and display device

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ATE463819T1 (en) 2010-04-15
JP2008532061A (en) 2008-08-14
FR2882457B1 (en) 2007-09-21
FR2882457A1 (en) 2006-08-25
WO2006087477A1 (en) 2006-08-24

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