EP1737239A2

EP1737239A2 - Data deinterleaver in a digital television signal decoding system

Info

Publication number: EP1737239A2
Application number: EP06021202A
Authority: EP
Inventors: John Sidney Stewart
Original assignee: Thomson Consumer Electronics Inc
Current assignee: Technicolor USA Inc
Priority date: 1994-11-30
Filing date: 1995-11-22
Publication date: 2006-12-27
Also published as: JP4105245B2; JP4986190B2; EP1737239A3; EP2111040A2; JPH08223505A; EP0715468A3; AU3910595A; BR9505549A; JP2012075184A; JP2012105314A; MY115379A; JP2012075183A; JP2010200372A; CN1126925A; JP4605615B2; CN1147135C; EP0715468A2; CA2161468A1; CA2161468C; KR960020466A

Abstract

A television signal receiving system includes a deinterleaving network (18) containing first and second deinterleaving functions associated with respective memory address controllers (20, 25). One or the other of the deinterleaving functions is selected for use by a multiplexer (30) in response to a Deinterleaver Select control signal. Deinterleaving is accomplished by controlling the read/write addressing of a memory (35) by the selected deinterleaving function.

Description

This invention is related to the field of digital signal processing, and more particularly to a video signal deinterleaver included in a system for decoding a television signal such as a high definition television signal.
Advanced video signal processing systems such as high definition television (HDTV) systems typically use digital signal processing. As part of such digital signal processing, data is typically rearranged in a prescribed sequence prior to transmission, followed by restoration to the original sequence upon reception. This operation serves to spread or disperse the data in time in a predetermined sequence, such that a data loss during transmission does not result in a loss of contiguous data. Instead, any data lost is dispersed and is therefore more easily concealed or corrected. Apparatus used to rearrange the original data sequence prior to transmission is commonly referred to as an interleaver, and apparatus used to restore the original data sequence upon reception is referred to as a deinterleaver. The interleaving/deinterleaving process is well known. Scrambling, in contrast to interleaving, has as its main goal the randomizing of data and the dispersal of transmitter signal energy. This helps to minimize co-channel interference and enhance timing recovery in the receiver. Scrambling also facilitates channel distortion compensation by an equalizer in the receiver.
Different interleaving/deinterleaving algorithms are known. For example, European satellite systems currently employ an algorithm proposed by Forney as described in "Burst-Correcting Codes for the Classic Bursty Channel," IEEE Transactions on Communications Technology, vol. COM-19, Oct. 1971 . A different algorithm proposed by Ramsey as described in "Realization of Optimum Interleavers," IEEE Transactions on Information Theory, vol. IT-15, May 1970, is commonly used in the United States.
From US-A-4 063 533 a reconfigurable deinterleaver is known, comprising a memory array, a memory for storing predetermined deinterleaver parameters a controller and column and row selector means. The predetermined deinterleaver parameters define the number and length of the interleaved code words to be deinterleaved. The controller is responsive to the deinterleaver parameters for controlling the writing of interleaved code words into the memory array and for reading deinterleaved code words from the memory array.
From EP-A-0 582 827 the structures of an interleaver and a corresponding deinterleaver are known in which the information is processed in pseudorandom order. Synchronization for the deinterleaving operation occurs when a synchronization code is detected at a plurality of ouput ports of the deinterleaver.
The present inventor has recognized that a single signal processing device, such as an integrated circuit (IC), can advantageously accommodate multiple deinterleaving functions within the context of an advanced television signal processing system, for example. In accordance with the principles of the invention, a digital signal processing network contains an adaptive deinterleaving network incorporating different types of deinterleaving functions. In a disclosed embodiment, a selected deinterleaving function controls read/write addressing of a single memory. This reduces the cost and complexity of the network, and facilitates the implementation of a deinterleaving network containing different deinterleaving functions within an IC. The deinterleaving function to be used in a given application may be selected by means external to the device containing the deinterleaving network, or by a programmed controller, for example. Further, which of the particular deinterleaving functions is selected is determined by the type of system in which the deinterleaver is used. The system type varies because of the different types of television signal transmission methods used. For example, a different type of broadcast satellite systems is used for carrying advanced television information in the United States than is used in Europe.
Figure 1 is a block diagram of a portion of a HDTV receiver system including deinterleaving apparatus in accordance with the principles of the present invention.
Figure 2 shows an alternative implementation of deinterleaving apparatus according to the present invention.
Figure 1 is a block diagram of a portion of a HDTV receiver including a deinterleaving network 18 according to the principles of the present invention. A transmitted HDTV signal received by an antenna 10 is applied to an input processor 12. Input processor 12 typically includes a tuner and IF stage for down-converting the received signal to a lower frequency band. It also may include automatic gain control, filtering, timing/clock recovery networks and other circuitry as known. The output signal from unit 12 is equalized and demodulated by unit 14. The equalization process compensates for distortions in the data channel as known. The demodulator function recovers the baseband interleaved data from the modulated input signal. Such equalizer and demodulator functions are well known and are described, for example, in the reference text Digital Communication, Lee and Messerschmidt (Kluwer Academic Press, Boston, MA, USA, 1988).
The interleaved data from equalizer/demodulator 14 is applied to a synchronizer circuit 27 within deinterleaving network 18, and to a signal input of memory 35. Synchronizer circuit 27 detects sync words in the interleaved data signal and provides output signals synchronized to the data indicating when the data starts. The sync words are not themselves interleaved, but occur at periodic intervals in time. As an example, the interleaved data may consist of repeated data blocks containing a sync word followed by 15 data words. The synchronization function is accomplished, for example, by sync detection circuitry incorporating byte recognition logic and a phase-locked loop. The byte recognition logic recognizes the sync byte pattern, and the phase-locked loop tracks the sync bytes and indicates when a sync byte is expected. Therefore, synchronizer circuit 27 is able to provide output signals to first and second address and memory controllers 20 and 25 for synchronizing address signals applied to memory 35 via a multiplexer 30, with the input interleaved data applied to the signal input of memory 35.
Deinterleaving network 18 is configured such that controller 20 contains one deinterleaving function in the form of an algorithm, and controller 25 contains a different deinterleaving function also in the form of an algorithm. For example, controller 20 may implement the Ramsey deinterleaving function and controller 25 the Forney deinterleaving function. These deinterleaving functions may be implemented as logic state machines, i.e. as a cyclic sequence of logic operations, each assigned a state with the sequence being potentially responsive to inputs. Outputs generated by the state machine operation are a function of any combination of state, previous or present input signal or previous or present output signal. The required logic equations to implement the state machine operation are programmed into a logic structure acting as a memory using well known methods.
In this system only one of the two deinterleaving functions operates at a time, depending on the state of a Deinterleaver Select control signal. The Deinterleaver Select signal may be provided by various sources. Preferably this control signal is provided by a programmed microprocessor. Such a microprocessor has not been shown in Figure 1 in order to simplify the drawing. The control signal may also be provided by a manually operated switch source, for example, located in the HDTV receiver and external to deinterleaving network 18. In that case the switch source applies a selected binary logic level directly to a designated input of deinterleaving network 18. Alternatively, the control signal may be decoded from a received interleaved data stream.
Controllers 20 and 25 produce a sequence of read and write addresses and associated memory control signals (such as read, write and output enable) which are passed via multiplexer 30 to memory 35. Memory 35 is essentially a shared memory which services whichever one of the two (or more) deinterleaving functions is selected. The addresses and associated memory control signals from controllers 20 and 25 are synchronized to the interleaved data input to memory 35 by the synchronization signals from synchronizer 27. The state of the Deinterleaver Select control signal input to multiplexer 30 determines which one of memory controller units 20 and 25 supplies memory address control signals to memory 35. Controllers 20, 25 produce respective memory write address control signals such that the input interleaved data is written into memory locations of memory 35 in the order in which the input interleaved data is received. Controllers 20 and 25 also produce respective memory read address signals to enable data to be read out of memory 35 in the desired deinterleaved order. This may be achieved, for example, by the state machine for the selected deinterleaver control unit producing the required sequence of addresses for reading the data out of memory 35. Thus in this example output data from memory 35 corresponding to the original (deinterleaved) data is produced as a function of a memory read process. The deinterleaving function may also be accomplished as a function of a memory write process, or as a function of both read and write processes.
The disclosed deinterleaver network 18 realizes an advantage by using a plurality of address and memory controllers with an associated (shared) memory. That is, only a single shared memory is required, regardless of the number of deinterleaver functions that are implemented and available for selection
The deinterleaved data output from memory 35 is descrambled by unit 38. Descrambling, as distinct from deinterleaving, has as its main goal the de-randomizing of data. The randomizing of the data is performed prior to transmission to disperse the transmitter signal energy. This helps to minimize co-channel interference and enhance timing recovery in the receiver. It also facilitates channel distortion compensation by an equalizer in the receiver. The descrambled output of unit 38 is decoded by decoder 40, which may be a Reed-Solomon decoder, for example. Corrected data packets from unit 40 are applied to a transport processor 44, which examines the header of each data packet to identify audio and video data. Transport processor 44 conveys the audio and video output data to appropriate decoders within unit 46. Decoded audio and video signals from unit 46 are respectively applied to an audio processor 52 and to a television video processor 50. Processors 50 and 52 format the audio and video signals in a manner appropriate for reproduction by unit 55.
Another embodiment of the invention is disclosed in Figure 2. In this embodiment data needed to configure a memory controller to provide a desired deinterleaving function is contained within a memory 70. Memory 70 may contain more than one deinterleaving function. This data, e.g. an algorithm, is loaded into a memory controller 80 by a data loader 75. This may be performed, for example, by data loader 75 reading data from memory 70 and writing this data to memory locations within controller 80. Data loader 75 selects which deinterleaving function to load in response to a Deinterleaver Select control signal. This control signal may be provided from a variety of sources as mentioned in connection with the embodiment of Figure 1. Data loader 75 initiates the load operation upon power-up of the system, or upon a change in the logic level of the Deinterleaver Select control signal.
Interleaved input data is applied to a synchronizer 73. Synchronizer 73 conveys sync signals to controller 80 for enabling controller 80 to synchronize memory address generation with the input interleaved data. The synchronization function is as described in connection with Figure 1. Controller 80 produces write addresses so that the input interleaved data is written into the memory 85 in interleaved form. In addition, controller 80 produces read addresses to enable the stored data to be read out of memory 85 in the original deinterleaved order. That is, the read addressing of memory 85 is a function of deinterleaving data obtained from unit 70. The address generation function of controller 80 operates in the same way as described for controllers 20 and 25 in connection with Figure 1.
Although the invention has been described in the context of a HDTV video signal processing system, it should be understood that the invention is applicable to other systems where different deinterleaving functions may be used, such as satellite and terrestrial broadcast systems. It should also be recognized that elements described in connection with Figures 1 and 2 may be arranged in various ways. For example, controllers 20, 25 and 80 may be implemented with microcontrollers or with discrete logic networks. In addition, the controllers 20 and 25 of Figure 1 may share circuitry. Further, controllers 20, 25 and 80 of Figures 1 and 2 and may implement the deinterleaving address sequencing function in various ways. The deinterleaving function may be performed during the write cycle instead of during the read cycle described for the embodiment of Figure 1. This write cycle deinterleaving is accomplished by writing the data to memory 35 or 85 locations in deinterleaved order, followed by reading the data from consecutive locations for output. Alternatively, the controllers may partially deinterleave the data during the write operation, while performing the remainder of the deinterleaving function during the read operation.
The Deinterleaver Select control signal may be used to disable the unused controller in Figure 1. This may be desirable to reduce noise or power dissipation. The control signal may also be used to disable the outputs of the controller not in use, for example, by disabling output signal tri-state buffers of the controller not in use. In this case the output signal tri-state buffers of the controller in use are enabled, and the buffers of the controllers not in use are disabled. Multiplexer 30 would not be needed in this case.
More than one Deinterleaver Select control signal may be used. This may occur, for example, where two separate buffered versions of the same control signal are used by controllers 20 and 25. It may also occur when there are more than two address and memory controllers (each containing a different deinterleaving function) available for selection within deinterleaving network 18.

Claims

Apparatus for receiving a signal representative of interleaved digital video data consisting of data blocks, comprising an input processor (10-14) having an input for receiving said signal representative of interleaved digital video data and for providing an interleaved data output; an output signal processor (38-35) for processing a deinterleaved output signal, and a deinterleaving network (18) interposed between said input processor and said output signal processor, wherein said deinterleaving network (18) contains a single memory unit (35), characterized in that said deinterleaving network (18) performs one of a plurality of different deinterleaving algorithms on said interleaved data output to produce said deinterleaved output signal, and comprises a first memory controller (20) controlling read and write addressing of said single memory unit (35) to implement a first deinterleaving algorithm after receiving said data blocks; a second memory controller (25) controlling read and write addressing of said single memory unit (35) to implement a second distinct and different deinterlaving algorithm after receiving said data blocks; and a source of deinterleaving control signal for disabling one or the other of said first and second memory controllers (20, 25) to dispose the single memory unit (35) to implement a given one of said distinct and different deinterleaving algorithms after receiving said data blocks, wherein only a single deinterleaving algorithm is operable at a time based on the deinterleaving control signal, and wherein the first and second memory controllers produce a sequence of read and write addresses and associated memory control signals to service whichever one of the deinterleaving algorithms is used.
Apparatus according to claim 1, wherein said memory controllers (20, 25) perform a given deinterleaving algorithm during the read addressing.
Apparatus according to claim 1, wherein said memory controllers (20, 25) perform a given deinterleaving algorithm during the write addressing.
Apparatus according to one of claims 1 to 3, wherein said input processor (10-14) includes a demodulator network (14); and said output processor (38-55) includes a decoder (40) and a video processor (50) responsive to decoded signals for said decoder (40).
Apparatus according to one of the preceding claims, further comprising a synchronizer (27) receiving said interleaved data and for providing synchronization signals to synchronizing inputs of said first and second memory controllers (20, 25) for synchronizing said read and write addressing from said interleaved data.
Apparatus according to one of claims 1 to 5, wherein the input processor (10-14) comprises a decoder that generates the deinterleaving control signal from the received interleaved data stream.