EP1537486A1 - Reconfigurable sequencer structure - Google Patents

Abstract

The invention relates to a cellular element field for data processing, with functional cell means for carrying out algebraic and/or logical functions and memory cell means for receipt, storage and/or output of information. Functional cell/memory cell combinations are thus formed whereby a control connection is run from the functional cell means to the memory cell means.

Description

Title: Reconfigurable sequencer structure

description

The present invention relates to a line element array and a method for operating the same. The present invention deals in particular with reconfigurable data processing architectures.

A reconfigurable architecture is understood to mean, among other things, building blocks (VPU) which have a large number of elements which are variable in function and / or networking in operation. The elements can include arithmetic logic units, FPGA areas, input / output cells, memory cells, analog modules, etc. Blocks of this type are known, for example, under the name VPU. This typically comprises arithmetic and / or logical and / or analog and / or storage and / or networking modules and / or communicative peripheral modules (IO), which are referred to as PAEs and are arranged in one or more dimensions and are connected to one another directly or by one or more bus systems , The PAEs are arranged in any configuration, mixture and hierarchy, the arrangement being referred to as a PAE array or PA for short. A configuration unit can be assigned to the PAE array. In principle, in addition to VPU modules, systolic arrays, neural networks, multiprocessor systems, processors with several arithmetic units and / or logic cells, networking and network components such as crossbar circuit etc. are known, as are FPGAs, DPGAs, transputers etc. Please note that essential aspects of VPU technology include: B. are described in the following property rights of the same applicant and the associated subsequent applications for the listed property rights:

P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT / DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT / EP 00/10516, EP 01 102 674.7, DE 102 06 856.9 , 60 / 317,876, DE 102 02 044.2, DE 101 29 237.6-53, DE 101 39 170.6.

It should be noted that the aforementioned documents are included for disclosure purposes, in particular with regard to the special features and details of networking, configuration, design of architectural elements, trigger processes, etc.

The architecture has considerable advantages over conventional processor architectures insofar as data processing is carried out in a manner that has a high proportion of parallel and / or vectorial data processing steps. However, the advantages of the architecture compared to other processor, coprocessor or generally data processing units become less if the advantages of networking and the given special processor architecture can no longer be fully realized.

This is particularly the case when data processing steps are to be processed that are conventionally best mapped to sequencer structures. It is desirable It is worth seeing that the reconfigurable architecture is designed and used in such a way that data processing steps that are typically particularly easy to process with sequencers can be processed particularly quickly and efficiently.

The object of the present invention is to provide something new for commercial use.

The solution to this problem is claimed independently. Preferred embodiments can be found in the subclaims.

According to a first essential aspect of the invention, in the case of a cell element field which is reconfigurable in function and / or networking, in particular at runtime without disturbance, for data processing, in particular with coarse-granular functional cell means for performing algebraic and / or logical functions and memory cell means for receiving information , to save and / or to output, it is proposed that function cell / memory cell combinations are formed in which a control connection is made from the function cell means to the memory cell means. This control connection serves to make the address and / or data input / output from the memory controllable by the assigned function cell, typically an ALU-PAE. For example, it can be specified whether the next transmitted information is to be treated as an address or as data and whether read and / or write access is required. This transfer of data from the memory cell or the memory cell means, which may be a RAM-PAE, to the functional cell means, which may be an ALU-PAE, then allow new ones from the ALU be executed Commands can be loaded into this. It should be pointed out that functional cell means and memory cell means can be combined by integration into a structural unit. In such a case, it is possible to use a single bus connection to introduce data into the memory cell means and / or the ALU. Suitable input registers and / or output registers can then be provided and, if desired, different additional data and / or configuration registers as memory cell means.

It should also be mentioned that it is possible to build up a cell element field which contains a multiplicity of different cells or cell groups, stripes or the like preferably being provided with the different cells since this enables a very regular arrangement to simplify hardware engineering and operation equally. With such a strip-like or other regular structure made up of a small plurality of different cell elements, elements with integrated functional cell medium-memory cell medium combinations, i.e. cells in which functional cell and memory cell means according to the invention are integrated, can be provided centrally in the field, where typically only a few Different program steps within a sequencer structure have to be processed because, as was recognized, this gives very good results for conventional data stream applications, while more complex sequencer structures can be built up at the field edges, for example an ALU-PAE that has a separate one Unit represents, in addition to a separate RAM-PAE and possibly a series of I / O-PAEs using or arranging appropriate control lines or connections The same can be arranged because more memory is often required there, for example in order to temporarily store results generated in the field central area of the cell field and / or to pre-store and / or prepare the data required for the data flow through them.

If, for example in the middle of the field, cells are provided which integrate memory cell means and functional cell means, then a small memory can be provided therein for various commands to be executed by the functional cell means such as the ALU. It is in particular possible here to separate the command or configuration memory from a data memory, and it is possible to make the function memory large enough that one of several, for example two, different sequences can alternatively be processed. The sequence to be processed can take place in response to results generated in the cell and / or control signals entering the cell from the outside, such as carry, overflow, etc. trigger signals. In this way, this arrangement can also be used for wave reconfiguration processes.

In this way, it is possible to set up a sequencer structure in a row element field with only two elements, which are connected via suitable buses, simply by providing a dedicated and dedicated function cell-controlled control connection between the function cell or function cell means and the memory cell or memory cell means, without any further Measures and / or structural changes are required. Data, addresses, program steps etc. can be stored in the memory cell in a manner known per se from conventional processors. Because both Elements can also be used in another way with a corresponding configuration, which results in a particularly efficient construction which can be adapted particularly well to sequencer structures as well as vectorial and / or parallelizable structures. In this way, parallelizations can be supported solely by suitable PAE configurations, for example by providing PAEs working in two different spatial directions and / or by cell units provided with data feed-through registers.

It is clear that by using only two cells in a row element field, namely the functional cell and the information supply cell, a large number of sequencer-like structures can be built up in the reconfigurable cell element field. This is advantageous insofar as a number of different tasks that are different from one another per se must often be processed during data processing, for example in a multitasking operating system. A large number of such tasks can then be effectively processed simultaneously in a single line element field. The advantages for real-time applications are obvious. Furthermore, it is also possible to operate the individual sequencer structures, which are set up in a cell element field with the control connection according to the invention, at different clock rates, for example in order to reduce the power consumption in that tasks with a lower priority are processed more slowly. It is also possible to execute sequencer-like program parts in the field in parallel or vectorially when executing largely parallel algorithms per se and vice versa. Typically, however, it will be preferred that sequencer-like structures in the cell element field, be it sequencer-like structures in an area connected by connection with neighboring cells or buses, or combinations of spatially distinguishable, separate and also separately usable functional cell elements, such as ALU-PAEs and memory cell elements such as RAM -PAEs to be clocked higher. This has the advantage that sequential program parts, which are very difficult to parallelize at best, can be used in general data flow processing without the overall data processing being impaired. Examples of this are given, for example, by HUFFMANN coding, which can be processed much better sequentially than in parallel and which also plays an important role for applications such as MPEG4 coding, but the essential other parts of MPEG4 coding can be easily parallelized. Parallel data processing is then used for most parts of an algorithm and a sequential processing block is provided therein. Typically, increasing the clock frequency in the sequencer area by a factor of 2 to 4 will be sufficient.

It should be mentioned that instead of a strip-like arrangement of different cell elements, another, in particular multidimensional grouping can also be selected.

The cell element field with the cells that can be configured in function and / or networking can, of course, form a processor, a coprocessor and / or a microcontroller, or a parallel plurality or combinations thereof. The function cells are typically formed as arithmetic logic units, whereby they represent in particular coarse-grained elements, but which, for. B. can be provided with a fine-grained state machine. In a particularly preferred exemplary embodiment, the ALUs are so-called extended ALUs (EALU), as described in the earlier applications of the present applicant. An extension can include, in particular, the control line control, command decoding unit, etc., if necessary.

The memory cells can store data and / or information in a volatile and / or non-volatile manner. If information stored in the memory cells, be it program steps, addresses for accessing data or data stored in register or heap-like form as volatile data, complete reconfiguration can take place during operation. Alternatively, it is possible to provide non-volatile memory cells. The non-volatile memory cells can be provided, for example, as an EE prom area and the like, in which a rudimentary bios program is stored, which is to be executed when the arrangement is started up. In this way, a data processing device can be started up without additional components. A non-volatile data memory can also be provided if, for reasons of cost and / or space, it is decided that the same program parts are to be executed again and again, whereby it is also possible to switch under such fixed program parts, for example according to the type of WAVE reconfiguration. The possibilities of providing and using such non-volatile memories are the subject of other protective rights of the applicant. It is possible to store both volatile and non-volatile data in the memory cells, for example by to save a bios program f.est and still be able to use the memory cell for other purposes.

The memory cell is preferably designed such that it can store a sufficient number of data to be processed and / or program parts to be processed. It should be noted that these program parts can be designed both as program steps, each of which specifies what an individual, in particular the assigned PAE, in particular the function cell controlling the memory cell, has to do in the next step, as well as entire configurations for field areas or other fields. In such a case, it is easily possible for the built-up sequencer structure to issue a command, on the basis of which a reconfiguration of row element field areas takes place. The functional cell that triggers this configuration then also works as a charging logic. It should be pointed out that the configuration of other cells can in turn take place in such a way that sequencer-like data processing takes place there, and it is in turn possible in these fields to configure or reconfigure other cells in the course of the program processing. This results in an iterative configuration of line element areas and it is possible to nest programs with sequencer and parallel structures that are nested one inside the other like a babushka. It should be pointed out that access to further row element fields outside of a single integrated module can take place here in particular through input / output cells, which can massively increase the overall computing power. In particular, it is possible, when configurations occur in a code part of a sequencer structure configured in a cell element field, either to carry out the configuration requests on an assigned cell element field that is managed solely by the respective sequencer structure and / or such requests can be made to a configuration master unit to ensure that all cell elements are evenly assigned. This results in a quasi subroutine call by transferring the required configurations to cells or loading logic. This is considered worthy of protection in itself. It should also be pointed out that the cells, provided that they themselves are responsible for the configuration of other cell element field areas, can be provided with FILMO structures and the like implemented in the manner of hardware or software, in order to ensure proper reconfiguration. Attention is drawn to the possibility of describing the memory cells during the processing of commands in such a way that the code to be processed or the program to be processed changes. In a particularly preferred variant, this type of self-modification (SM) is suppressed by a corresponding control via the functional cell.

It is possible that the information stored in the memory cell, upon activation of the function cell controlling it, gives directly or indirectly to a bus leading to the function cell. Indirect output can take place in particular when the two cells are adjacent and the information requested by the control must arrive at the ALU-PAE via a bus segment that cannot be connected directly to the output of the memory cell. In such a case, the memory cell can output data on this bus system in particular via a backward register. It is therefore preferred if at least one of the

ιo - cher cell and / or functional cell has such a backward register, which can be arranged in the information path between the memory cell and the functional cell. In such a case, these registers do not necessarily have to be provided with further functionalities, although this is the case, for example, when data is requested from the memory cell for further processing, in accordance with a conventional LOAD command from a typical microprocessor, in order to change the data before it is loaded into the PAE is easily conceivable to z. B. to implement a LOAD ++ command. The data transmission through reverse-working ALUs and the like having PAEs should be mentioned.

The memory cell will preferably be arranged to receive information from the functional cell controlling it, it also being possible to store information via an input-output cell and / or a cell that does not control the memory cell. In particular, if data are to be written from an input / output cell to the memory cell, it is preferred if this input / output cell (I / O-PAE) is also controlled by the function cell. In this case, for example, the address at which information to be written into the memory cell or possibly also directly transmitted to the function cell (PAE) can be read to the I / O-PAE from the ALU-PAE. In this context, it should be pointed out that this address can be defined in the I / O-PAE via an address translation table, an address translation buffer or an MMU-like structure. In such a case, the full functionalities of typical microprocessors result. That there is also an I / O functionality with a functional cell medium, a memory cell medium and / or Function cell agent-memory cell agent combination can be integrated, should be mentioned.

The combination of function cells and memory cells, be it as an integrated function cell and memory cell combination or as a function cell and memory cell combination made up of separate units, is therefore assigned in a preferred variant at least one input / output means, with which an external device is then assigned Unit, another function cell, function cell-memory cell combination and / or memory cells information can be sent and / or received by this.

The input / output unit is preferably also designed to receive control commands from the functional cell or from the functional cell means.

In a preferred variant, the control connection is designed to transmit at least some and preferably all of the following commands:

OPCODE FETCH,

DATA WRITE INTERNAL,

DATA WRITE EXTERNAL, DATA READ INTERNAL,

EXTERNAL DATA READ,

ADDRESS POINTER WRITE INTERNAL,

ADDRESS POINTER WRITE EXTERN,

ADDRESSPOINTER READ INTERNAL, ADRESSPOINTER READ EXTERN,

PROGRAM POINTER WRITE INTERNAL,

PROGRAM POINTER WRITE EXTERN, PROGRAM POINTER READ INTERNAL,

PROGRAM POINTER READ EXTERN,

STACKPOINTER WRITE INTERNAL,

STACKPOINTER WRITE EXTERN,

STACKPOINTER READ INTERNAL,

STACKPOINTER READ EXTERN,

PUSH,

POP,

PROGRAM POINTER INCREMENT.

This can be done by a corresponding bit width of the control line and an assigned decoding at the receivers. The control and decoding means required in each case can be provided easily and inexpensively. As can be seen, the commands result in a practically complete sequencing capability of the arrangement. It should be mentioned that a general-purpose processor data processing unit is obtained in this way.

The arrangement will typically be selected such that the functional cell can access the control connection and / or a bus segment or bus system serving as a control connection as the sole master. The result is an arrangement in which the control line acts as a command line, as is provided in conventional processors.

The functional cell and the memory cell or I / O cell are preferably arranged adjacent. Neighboring can, as preferred, mean that the cells are arranged directly next to one another. Immediately means in particular a combination of such cells to form integrated units that are repeated on the cell element field or as part be provided to form the field. This can mean an integral unit of memory and logic cells. Alternatively, they are at least close together. The arrangement of the function and memory cells in an integrated or close proximity to one another ensures that no, at least no significant, latency times occur between activation and data input of the requested information in the function cell, simply because the connections between the cells are too long. This should be understood as "direct". If latency times have to be taken into account, pipelining can also be provided in the sequencer structures. This becomes particularly important in the case of very high-clocked arrangements to provide clocked cell units which, as is known per se in the prior art, can also correspondingly quickly access suitable memory cells, even in such a case, for example if known architectural elements are used for the functional cells, at the same time the functional cell element and the associated ones can be reconfigured In a particularly preferred variant, the function cells, the information provision cells such as memory cells, I / O cells and the like are arranged in a multidirectional manner, in particular in the manner of a matrix or on grid points of a one-dimensional grid, etc. If a regular As is the case there, a cell is typically supplied with information, ie operands, configurations, trigger signals, etc. from a first row, while data, trigger signals and other information are emitted in a row below. In such a case, it will be preferred if the cells are in the same row and the information can then tion transfer from the information supply cell into the required input of the function cell via a backward register. The possibility of using the registers for pipeline is mentioned.

Protection is also claimed for a method for operating a cell element field, in particular multidimensional cell element field with functional cells for performing algebraic and / or logical functions and information provision cells, in particular memory cells and / or

Input / output cells for receiving and / or outputting information and / or storing the same, at least one of the function cells issuing control commands to at least one information supply cell, information is provided there for the function cell in response to the control commands, and the function cell is designed to carry out the further data processing in response to the information provided, in order to at least temporarily process data in the manner of a sequencer.

In a reconfigurable field, the output of the control commands to the memory cell of a sequencer structure thus enables sequencer-like data processing. The commands that can be issued as control commands by the functional cell enable sequential operation, as is known from conventional processors. It should be pointed out that it is readily possible to implement only parts of the above-mentioned commands and still guarantee complete sequencer-like data processing. The invention is described below and, for example, with reference to the drawings. This is shown by:

Fig. 1 a cell element field according to the invention,

Fig. 2a a detail of this,

Fig. 2b, c the detail of Fig. 2a during various

Data processing times,

Fig. 3 shows an alternative embodiment of the detail from FIG. 2,

FFiigg .. 44 a particularly preferred variant of the

details,

Fig. 5 shows an example of the functional folding onto a functional cell / memory cell combination of the invention, FIG. 6a shows an example of a sequentially parallel one

Data processing, FIG. 6b a particularly preferred exemplary embodiment of the invention, FIG. 7 an alternative to a function folding unit.

1, a cell element field, generally designated 1, for data processing 1 comprises functional cell means 2 for performing arithmetic and / or logical functions and memory cell means 3 for receiving, storing and / or outputting information, a control connection 4 from functional cells 2 to the memory cells 3 is performed.

The cell element field 1 is freely configurable in the networking of the elements 2, 3, 4, and specifically without disrupting the line element parts that are not to be reconfigured during operation. The connections can be configured by switching bus systems 5 as required. The respective function cells 2 can also be configured. The function cells are arithmetic logic units that are expanded by certain circuits that enable reconfiguration, such as state machines, interface circuitry for communication with the external charging logic 6, etc. Reference is made to the applicant's corresponding advance registrations.

The cell elements 2, 3 of the cell element array 1 are arranged two-dimensionally in rows and columns, a memory cell 3 lying directly next to a function cell 2 and here three rows of memory cells and function cells each in which the function and memory cells are located Control connections 4 are interconnected. The function and memory cells 2, 3, or the combination thereof, have inputs which can be connected to the bus system above the row in which the respective cell elements are located in order to receive data therefrom. Furthermore, the cells 2, 3 have outputs which output data to the bus system 5 below the row. As will be explained further, each memory cell 3 is also provided with a backward register (BW), through which data can be passed through from the bus below a row to the bus above the respective row.

The memory cell means 3 also preferably has at least 3 memory areas, namely a so-called data area, a program memory area and a stack area, etc. However, in other variants of the invention it may be sufficient to provide only two areas, namely a data memory and a program memory area, each of which can form part of a memory cell means. In particular, it is possible not simply to separate a memory which is homogeneous per se and which is identical in terms of hardware into different areas, but rather to actually provide memory areas which are physically or hardware-technically separate. In particular, an adaptation of the storage width and / or depth to the respective requirements can also be provided. When designing a memory such that it has a program area and a data area during operation, it will be preferred to design this memory or memory area for simultaneous access to data and program memory areas, for example as a dual-port memory. It may also be possible to provide closely coupled memory areas, in particular within a memory cell means-functional cell means combination, which is formed to form an integrated area, as a pure cache memory, in which data from more distant memory locations in particular for quick access during data processing be preloaded.

With the exception of the control connections 4 and the associated circuits within the functional cells (ALU in FIG. 2) or memory cells (RAM in FIG. 2), the cell element field for data processing from FIG. 1 is a conventional cell element field, as is the case with reconfigurable ones Data processing arrangements, for example a VPU according to the applicant's XPP technology, are common and known. In particular, the cell element field of FIG. 1 can be operated as is known, that is to say it has corresponding circuits for wave reconfiguration, for debugging, transmission of trigger signals, etc. The first peculiarities of the cell element field of the present invention result from the control connection 4 and the associated circuitry, which will be described in more detail below with reference to FIGS. 2a-c. It should be mentioned that while in FIG. 1 a control connection 4 is always led from a functional cell element located further to the left to a memory cell located further to the right, and only and precisely to such a memory cell, it is evidently possible also for the control lines to provide configurable networking in order either to address memory cells located elsewhere and / or to be able to address more than one memory cell if necessary, for example if there is a large amount of memory required for information to be received, stored and / or output from the memory cells is. For the sake of clarity, reference is only made in FIGS. 1 and 2 to fixedly provided individual control connections, which makes understanding of the invention considerably easier. The control connection can, if necessary, be replaced by conventional lines, provided the appropriate protocols are used.

2, the function cell 2 is referred to as an ALU and the function cell 3 as a RAM. Above the row in which the cells are located is the bus 5a, which connects the backward register 3a already mentioned to the inputs 3b of the memory cell and 2b of the ALU. The bus system running below the row is designated 5b and only the relevant segments of the bus system 5a, 5b are drawn. It can be seen that the bus system 5b alternatively receives data from an output 2c of the ALU 2, an output 3c of the RAM 3 and that it feeds data into the input 3al of the backward register. The ALU 2 also has further inputs and outputs 2a, 2a2, which can be connected to other bus segments and via which the ALU receives data such as operands or outputs results.

The control connection 4 is permanently under the control of the extended circuits of the ALU and here represents a connection via which a large number of bits can be transmitted. The width of the control connection 4 is selected such that at least the following control commands can be transmitted to the memory cell: DATA WRITE, DATA READ, ADRESSPOINTER WRITE, ADRESSPOINTER READ, PROGRAMMPOINTER WRITE, PROGRAMMPOINTER READ, PROGRAMMPOINTER INCREMENT, STACKPOINTER WRITE, STACKPOINTER , PUSH, POP. The memory cell 3 also has at least three memory areas, namely a so-called stack area, a heap area and a program area. Each area is assigned its own pointer, which is used to determine which area of the stack, the heap and the program area is read or write accessed.

Bus 5a is shared by units 2 and 3 in time division. This is indicated in FIGS. 2b, 2c. 2b shows a situation in which data can be sent from the output 2a2 of the ALU-PAE via the backward register to the input of the RAM cell, whereas the connection which exists at the same time, but is not used, between the output 3c of the RAM to the bus 5b and the connection between the output of the backward register BW to the input 2b of the ALU-PAE is of no importance at the time of FIG. 2b, which is why they are indicated by dashed lines. 2c, however, shows a time at which the Memory cell 3 feeds the information via the backward register to input 2b of ALU-PAE 2 via its output 3c from the memory area stack, heap or program determined via control line 4, while the output of ALU-PAE 2c is inactive and on Input 3b of the RAM-PAE no signal is received. For this reason, the corresponding connections are dash-dotted and are therefore shown as inactive.

A circuit 3d is provided within the RAM cell 3, in which the information received via the control line 4 or the control line bus segment 4 is decoded.

The invention is used as follows:

First, the ALU 2 receives configuration information from a central loading logic, as is already known in the prior art. The information transmission can be done in a manner known per se using the RDY / ACK protocol and the like. Provided, etc. to the possibility for the PLU a FIL MO memory to proper configurations ^"ration of the arrangement to allow is pointed.

The data for the configuration of the ALU 2 is also used to transmit a series of data from the loading logic, which represents a program or program part to be processed sequentially. For this purpose, reference is made only by way of example to FIG. 6a, in which the HUFFMANN coding is shown as a central sequential part of an MPEG4 coding which is per se data flow-like. The ALU therefore issues a corresponding command on line 4 during its configuration, which sets the program pointer for writing to a predetermined value within the RAM. After that, the Charging logic at the ALU receives data received via output 2c via bus 5bl and backward register 3a and from there it arrives at input 3b of RAM-PAE 3. From unit 3d, data is then sent to control line 4 in accordance with the control command written to the specified program memory space. This is repeated until all program parts received by the loading logic during configuration are stored in memory cell 3. When the configuration of the ALU is then completed, it will request the next program steps to be processed by it by issuing the corresponding commands on the control line 4 and via the output 3c, the bus 5b, the backward register of the RAM-PAE 3 and receive the bus 5a at its entrance. During program execution, situations can arise in which jumps within the program memory area are required, data are loaded into the ALU-PAE from the RAM-PAE, data must be stored in the stack, etc. The relevant communication between ALU-PAE and RAM -PAE takes place via the control line 4, so that the ALU-PAE can carry out the decoding at any time. In addition, as with a conventional microprocessor, data can also be received from a stack or another RAM memory area and data can also be received from outside as operands in the ALU-PAE.

The program sequence that was preconfigured in the RAM-PAE by the loading logic takes place. In the ALU-PAE, command decoding is carried out at the same time, as required per se. This is done with the same circuits per se, which are already used for decoding the commands received from the loading logic. The control line 4 is checked at all times via the ALU that the RAM cell always follows the type of memory access which is specified by the ALU. In this way it is ensured that regardless of the time-multiplex use of the bus elements 5a, b, the elements present in the sequencer structure are predetermined at any time whether there are addresses on the buses for data or codes to be fetched and / or to be written or whether and if so where to write data etc.

The arrangement shown in relation to FIG. 2 can be expanded or changed in different ways. The variants shown in FIGS. 3, 4 and 6 are particularly relevant.

3, not only is there a backward register on the RAM-PAE for connecting upper and lower buses, but there are also a forward register on the RAM-PAE and forward and backward registers on the ALU-PAE available. As indicated by the multiple arrows, these can serve to receive and receive data from other units, such as external hosts, external peripheral devices such as hard disks, main memory and the like and / or from other sequencer structures, PAEs, RAM-PAEs etc. to send to them. If a corresponding request command for new program parts is sent from the sequencer structure which is formed by the ALU-PAE and the RAM-PAE, it is possible to process program blocks in the sequencer structure which are far larger than those which are in the RAM PAE can be saved. This is a massive advantage, especially for complex data processing tasks, jumps over wide areas, especially in subroutines, etc. A further preferred variant is shown in FIG. 4. Here, the ALU-PAE not only communicates with a RAM-PAE, but also with an input / output-PAE, which is designed to provide an interface circuit for communication with external components, such as hard disks, other XPP-VPUs, and others Processors and coprocessors, etc. Again, the ALU-PAE is the unit that acts as the master for the control connection referred to as "CMD", and again the buses are used in a multiplexed manner. Again, data transfer from the bus can be under the row into the bus above the row through the backward register.

The arrangement shown in FIG. 4 makes it particularly easy to make external access to information that cannot be stored in the RAM-PAE memory cell and thus enables the sequencer structure to be adapted to an even greater extent to existing, conventional CPU technologies and their operating methods than address translation means, memory management units (MMU functions) and the like can now be implemented in the input / output cell. The RAM-PAE can serve as a cache, but in particular as a preloaded cache.

It should be noted that several sequencer structures can be configured into one and the same field at the same time, that function cells, memory cells and possibly input / output cells can optionally be configured for sequencer structures and / or in a conventional manner for XPP technology, and that it can be easily done it is possible that an ALU outputs data to another ALU, which they configure in a sequencer manner and / or to part of a cell make field with which a certain configuration is processed. In this way, the charging logic may then also be unnecessary.

According to FIG. 6, two embodiments of the invention are combined in one and the same cell element field, namely at the edges of two PAEs each, namely a sequencer formed from one RAM and one ALU-PAE, and inside with integrated RAM-ALU-PAEs as integrated Function cell memory cell units are formed sequencers, it being possible to form only a part of the cells inside the field as combination cells.

FIG. 5 shows on the right (FIG. 5c) a combination of functional cells and memory cells.

5c, a function cell / memory cell means combination, generally designated 50, comprises bus connections or inputs 51 for the input of operand and configuration data and, as is particularly preferred here, also trigger signals (not shown) and the like and a bus output 52 for the output of corresponding data or signals. An ALU 53 is provided within the functional cell means-memory cell means combination, as well as input registers RiO to Ri3 for operand data and trigger signal input register (not shown). The configuration data registers RcO to Rc7 for configuration data or ALU opcode data, result data register RdO ^ -RS and output registers RoO to Ro3 for results or trigger signals to be output. The registers Rc and Rd for the configuration data or opcode data are controlled by the ALU 53 via control command lines 4 and feed data via suitable data lines into the ALU or received from this result data. It is also possible to feed information from the bus 51 or the input registers Ri directly to the output register or the bus 52, just as information can be fed not only to the ALU but also to the output registers from the data registers RdO. If necessary, connections can be provided between the memory areas Rd and Rc, for example to implement the possibility of self-modifying codes.

The configuration data area RcO to Rc7 has a controller which allows work to be carried out on parts of the area, in particular repeatedly cyclically and / or by means of jumps. This makes it possible, for example in a first partial configuration, to repeatedly process commands which are in RcO to Rc3 and, alternatively, for example on receipt of a corresponding other trigger signal via bus line 51, to process configuration commands which are in Rc4 to Rc7. This ensures that a wave configuration can be executed. It should be noted that the configuration commands stored typically only represent instructions to the ALU, but do not define complete bus connections, etc.

The above-described unit shown in FIG. 5 is designed here to be operated at four times the clock rate, like a normal PAE without memory cell means and / or control signal lines 4.

In order to process data in a data flow like a sequencer on the function-folding unit formed in this way, data are first Flow graphs or areas according to Fig. 5a created. Memory areas RcO are then assigned to each operation to be processed in the graph, the data flowing into the graph subarea are assigned to internal input registers RiO, the intermediate results are assigned to memories RdO to Rd3 and the output results are assigned to registers Ro. With this assignment, the graph area is assigned to the function Folding unit can be processed. A data flow sequencer transformation takes place through this hardware.

It should be mentioned in this context that it will be generally preferred to use the arrangement of the present invention in such a way that a data flow and a control flow graph are first created for a data processing program with a compiler, and then a corresponding partitioning to carry out, wherein the pieces obtained by the partitioning can then be processed in whole or in part for processing on sequencer units, such as may be formed according to the present invention. In this way, data flow-like data processing is achieved as it progresses from one cell to the next, but a sequential processing is effected within the cell (s). This is advantageous if, due to the very high computing power of an arrangement, the clock frequency is to be increased in order in return to be able to reduce the area or number of cells. It should also be mentioned here that it is possible to carry out this transformation-like transition from purely data flow-type data processing to data flow processing with locally sequential parts in such a way that an iterative process is carried out, for example in such a way that a first partitioning is carried out first and then, should follow the the "rolling together" of the partitioned parts on sequencer units shows that, for example, the resources available on the sequencers or other places are not sufficient to carry out another partitioning which takes this into account and a new "rolling together". If the function folding units are to be used intensively, the number of registers can be increased if necessary.

It should also be pointed out that in the present case the registers are understood as memory cell means or parts thereof. It is clear that by enlarging the memory cell areas, more complex tasks can be arranged in a sequence-like manner, but that with the small sizes specified, essential parts of important algorithms can be processed with high efficiency.

In the present example, the function folding units are preferably formed in such a way that data can be switched through them without being processed in the ALU. This can be used to achieve path balancing, in which, for example, data packets have to be processed via different branches and then (again) merged without using forward registers, as are known from the applicant's architecture. At the same time and / or alternatively, it is possible not to allow the data flow direction in the cell element field to run strictly in one direction by appropriately aligning some functional cell means, memory cell means, function folding units, but in two opposite directions. So get z. For example, in every even row, the ALUs receive their input operands from the left and in every odd row, the ALUs receive their input operands from the right. If data has to be sent through the field several times, such an arrangement is advantageous, for example with rolled-out loop bodies etc. The alternating arrangement does not have to be strict. Other geometries can be selected for certain applications. In the middle of the field, a different direction of travel than at the edges could be selected, etc. The arrangement of functional cell units with the same direction of travel next to one another can be advantageous with regard to the bus connections. It should be pointed out that the opposing arrangement of a plurality of directional functional cells in a field and the resulting improved data processing, regardless of the provision of a control line or the like, are regarded as inventive.

An alternative to the functional folding unit shown in FIG. 5 is shown in FIG. 7.

Claims

claims

1. Cell element field for data processing with function cell center for executing algebraic and / or logical

Functions and memory cell means to receive, store and / or output information, characterized in that function cell-memory cell combinations are formed in which a function connection leads to the memory cell means from the function cell center.

2. Cell element field according to the preceding claim, characterized in that a processor, coprocessor and / or microcontroller with a plurality of functionally and / or networking reconfigurable and / or specifiable units such as functional cells and / or memory cells.

3. Cell element field according to one of the preceding claims, characterized in that the functional cells are formed as arithmetic logic units.

4. cell element field according to the preceding claim, characterized in that the arithmetic logic units are formed as extended ALUs.

5. Cell element field according to one of the preceding claims, characterized in that the memory cells are designed for volatile and / or non-volatile data storage.

6. Cell element field according to one of the preceding claims, characterized in that the memory cells are designed to store data to be processed and / or program steps to be processed.

7. Cell element field for data processing, characterized in that the memory cells are designed to directly and / or indirectly transfer stored information to a bus leading to the functional cell upon activation of the functional cell controlling it.

8. Cell element field according to one of the preceding claims, wherein at least one memory cell and / or functional cell are assigned registers, in particular a backward register, which is arranged in the information path between the memory cell and functional cell.

9. cell element field according to one of the preceding claims, characterized in that the memory cell is arranged to receive information from the function cell controlling it, an input-output cell and / or a cell not controlling it with an arithmetic logic unit.

10. Cell element field according to one of the preceding claims, characterized in that the function cell / memory cell combination is assigned at least one input / output means in order to send information to an external unit and / or another function cell, function cell / memory cell combination and / or send and / or receive memory cell.

11. cell element field according to the preceding claim, characterized in that the input-output means is also designed to receive control commands from the functional cell.

12. Cell element field according to one of the preceding claims, characterized in that the controller is designed to transmit at least some, preferably all, of the subsequent commands and / or the memory cell or input / output cell is designed to decode the following commands : DATA WRITE / READ, ADDRESS POINTER WRITE / READ, PROGRAMMPOINTER WRITE / READ, PROGRAMMPOINTER INCREMENT, STACKPOINTER WRITE / READ, the aforementioned commands in each case in particular for internal and / or external access, PUSH, POP, OPCODE, FETCH.

13. Cell element field according to one of the preceding claims, characterized in that the functional cell can access the control connection and / or the bus segment serving as the control connection as the sole master.

14. Cell element field for data processing according to one of the preceding claims, characterized in that the functional cell is arranged adjacent to at least one of the memory cell and the input / output cell.

15. Cell element field according to one of the preceding claims, characterized in that the cell elements are arranged multidimensionally, in particular matrix-like, the functional cell and / or the adjacent memory or. I / O cell can receive data from an upper row and output data to a lower row, where are provided in a row and the functional cell and at least one memory and / or input / output cell are in the same row.

16. Method for operating a cell element field, in particular a multidimensional cell element field with function cells for performing algebraic and / or logical functions and information provision cells, in particular memory cells and / or input / output cells for receiving and / or outputting information and / or

Saving the same, characterized in that at least one of the function cells issues control commands to at least one information supply cell, is processed there in response to the control command information for the function cell and the function cell is designed to carry out further data processing in response to information provided from the information supply cell to process data in a sequential manner.

17. The method according to any one of the preceding claims, characterized in that the function cell is designed to at least some of the control commands OPCODE FETCH, DATA WRITE INTERN, DATA WRITE EXTERN, DATA READ INTERN, DATA READ EXTERN, ADRESSPOINTER WRITE INTERN, ADRESSPOINTER WRITE EXTERN, ADDRESSPOINTER READ INTERNAL, ADRESSPOINTER READ EXTERN, PROGRAM POINTER WRITE INTERNAL,

PROGRAM POINTER WRITE EXTERN,

PROGRAM POINTER READ INTERNAL,

PROGRAM POINTER READ EXTERNAL, STACKPOINTER WRITE INTERNAL,

STACKPOINTER WRITE EXTERN,

STACKPOINTER READ INTERNAL,

STACKPOINTER READ EXTERN,

PUSH, POP,

Outputs PROGRAMMPOINTER INCREMENT and outputs at least some, in particular all, of the above-mentioned control commands as required in the course of cell element operation.