EP1535348A2 - Method for producing an integrated pin diode and corresponding circuit - Google Patents

Abstract

The invention relates to, inter alia, a method for producing an integrated PIN photodiode comprising a buried region (20) and a connection region (32) which leads towards the buried region (20). Said method enables the PIN photodiode (14) to be integrated in a simple manner. Furthermore, process steps for producing said PIN diode can also be carried out for the production of screening troughs (22, 56).

Description

description

Method for producing an integrated pin diode and associated circuit arrangement

The invention relates to a method in which a pin diode carried by a carrier substrate is produced. The pin diode contains a doped region of a first conductivity type close to the substrate with respect to the substrate, a doped region of another conductivity type remote from the substrate than the region close to the substrate and an undoped or arranged in comparison to the doping of the substrate close and in comparison to the doping of the substrate close Region or the region remote from the substrate provided with weak doping intermediate regions. Further areas can be arranged between the intermediate area and the area close to the substrate or between the intermediate area and the area remote from the substrate in order to improve the electrical properties of the pin diode.

A pin diode is a diode with a layer sequence p, i and n, where p is a highly p-doped region, i is an intrinsically conductive or intrinsic or only weakly n- or p-doped region and n is a highly n-doped region Name the area. The pin junction differs from a pn junction primarily by the intrinsic or the weakly doped intermediate region. Because of their electrical properties, pin diodes are used as rectifier diodes for reverse voltages above one hundred volts. Another area of application is fast switching diodes in the microwave range. Because the reverse current of the pin diode mainly depends on the charge generation in the i-zone, this diode is also used as a radiation detector, e.g. in nuclear technology, or as a pin photodiode, especially for detecting light in the wavelength range between approximately four hundred nanometers - tern to about a micrometer. In particular, they have pin diodes high sensitivity and high acquisition speeds.

Integrated pin diodes have a higher detection sensitivity and a higher frequency bandwidth than single semiconductor components because they are monolithically connected directly to integrated circuits.

It is an object of the invention to provide a simple method for producing an integrated pin diode. In addition, an associated integrated circuit arrangement is to be specified.

The object related to the method is achieved by the method steps specified in claim 1. Further developments are specified in the subclaims.

The invention is based on the consideration that the integrated pin diode should be produced using a method which can be easily embedded in the overall process for producing an integrated circuit arrangement and which, if possible, also contains method steps which can also be used to generate others effective structures in the integrated circuit arrangement.

In the method according to the invention, at least one electrically conductive connection region is produced, which leads to the region close to the substrate. The connection region is arranged in a layer containing the intermediate region and, in one embodiment, penetrates this layer from its interface remote from the substrate to its interface close to the substrate. In such a method, the region close to the substrate with respect to the layer containing the intermediate region is a so-called "buried" region, which is also referred to as a buried layer. In contrast to a so-called mesa layer stack, the method for producing a buried area is simpler. In addition, The method according to the invention does not connect the pin diode via the substrate, but rather via at least one separate connection area. This creates degrees of freedom for the integration of the pin diode in the integrated circuit arrangement. In addition, it becomes possible to manufacture other structures of the integrated circuit arrangement simultaneously with the pin diode, for example shielding troughs for certain parts of the integrated circuit arrangement. This possibility is explained in more detail below.

In a further development of the method according to the invention, a doped decoupling area is generated simultaneously with the area near the substrate. A circuit arrangement carried by the carrier substrate is produced in such a way that the decoupling area extends between a part of the components and the carrier substrate. In contrast, there is no decoupling area between the other part of the components and the carrier substrate. This measure makes it possible to generate a decoupling area without additional process engineering effort, which, for example, shields circuit parts of the integrated circuit arrangement which cause interference from other circuit parts. On the other hand, particularly sensitive circuit parts can also be shielded from the rest of the circuit. In the first case, parasitic currents cannot, for example, be impressed into the substrate by capacitive coupling. In the second case, parasitic currents or voltages, for example, do not reach the sensitive circuit parts by capacitive coupling from the substrate. A combination of both measures leads to improved shielding. Highly disruptive circuit parts are, for example, digital

Circuits or power amplifiers. Particularly sensitive circuit parts are, for example, preamplifiers.

In a next development of the method for producing a pin diode, a connection area leading to the decoupling area is produced simultaneously with the connection area leading to the layer of the pin diode close to the substrate. This means that no additional process steps are required for the production of the decoupling area connection area. The decoupling area can be set to a predetermined potential via the decoupling area connection area. In addition, so-called suction diodes can be generated via the decoupling area connection area, which draw interference voltages and interference currents from the integrated circuit arrangement. This possibility is explained in more detail below.

In a next development, the decoupling area connection area and the decoupling area form a shielding trough, which completely or partially surrounds an area encompassed by the shielding trough, or at least fifty percent or even at least seventy-five percent in relation to the side surfaces and the base area of the encompassed area. The more completely the enclosed area is enclosed, the greater the shielding effect. However, interruptions in the shielding are also possible, for example to enable simple process control for other reasons.

In a next development, areas lying outside of these areas are provided with a doping of another conductivity type in the plane or in the layer in which the region of the pin diode and the decoupling area are located. In this way, the area near the substrate and the decoupling area or individual decoupling areas in the plane or layer can be isolated from one another in a simple manner. In one embodiment, an oxide covering the area near the substrate and an oxide covering the decoupling area are used to mask an implantation. Compared to a lithography process, the process is simplified.

In a next development, the connection area leading to the region of the pin diode close to the substrate and the Coupling area-connecting area created to produce a deep trench, which is preferably at least twice as deep as wide. For example, the trench has a depth of over ten micrometers, over fifteen micrometers or even over twenty micrometers. The trench has a width of less than five micrometers, for example. Alternatively, the connection regions are produced with the aid of a diffusion process in which dopants diffuse on an area remote from the substrate as far as the layer close to the substrate or up to the decoupling layer. With a diffusion length of ten micrometers, for example, the connection regions have a width of seven micrometers, for example. In comparison to the area occupied by the pin diode, however, such a width is an acceptable value with respect to the circuit area required. Methods with implantations of one or more micrometers depth are also used to produce the connection areas.

In another development, the layer containing the intermediate region is produced using an epitaxy process. At the same time, in one embodiment, the epitaxy process generates base material for at least one embedding area, which is used to embed components of the integrated circuit arrangement. The embedding area is also referred to as a so-called bulk. An epitaxial process is an easy way to create layers covering buried layers. However, there are other options, such as high-energy ion implantation. Doped semiconductor regions can also be produced in a simple manner by an epitaxy process, for example by in-situ doping when the epitaxial layer is grown.

In the case of further training with an epitaxy process, the epitaxy process is carried out at least in two stages. Epitaxial growth is interrupted at the end of the first stage. Another process is then carried out that is not associated with epitaxial growth. With a design This is a doping process for producing a doping that differs from the doping of the epitaxial layer. This measure allows additional buried regions to be produced in a simple manner in addition to the region of the pin diode close to the substrate and to the decoupling region. After the other process has been carried out, the epitaxial layer continues to grow. With this procedure, previously customary methods for manufacturing the components of the integrated circuit arrangement can still be used unchanged.

In a next development, the connection region leading to the region of the pin diode close to the substrate completely comprises the intermediate region in the lateral direction. This measure allows the intermediate region to be electrically isolated in a simple manner from the other components of the integrated circuit arrangement.

In a next development, the layer containing the intermediate area is a semiconductor layer, which preferably has areas with different conductivity types. For example, the semiconductor layer is based on a single crystalline material, e.g. on single crystal silicon. However, solid-state semiconductors, such as gallium arsenide, are also used.

In a next development, the decoupling area borders on material with a different electrical conductivity type than the decoupling area. This measure creates pn diodes or np diodes, which have the function of suction diodes and suck off disruptive charge carriers or interference currents from the area adjacent to the decoupling area or prevent the currents from passing through to the area to be shielded due to a blocking effect.

The invention also relates to an integrated circuit arrangement with a PIN diode, which is produced with the method according to the invention or with one of its developments leaves. The technical effects mentioned above also apply to the circuit arrangement and its further developments.

Exemplary embodiments of the invention are explained below with reference to the accompanying drawings. In it show:

Figure 1 shows an integrated circuit arrangement with pin diode • and shielding trough, and

Figure 2A to 2D

Manufacturing stages in the manufacture of the integrated circuit arrangement.

FIG. 1 shows an integrated circuit arrangement 10 which contains a p-doped substrate 12, a pin photodiode 14, a shielded region 16 or more shielded regions and a circuit region 18 or more unshielded circuit regions.

The substrate 12 is, for example, part of a semiconductor wafer, ie a wafer. On the substrate 12, a buried n ⁺ region 20 and a buried n ⁺ region 22 were, for example, with the illustrated below with reference to Figure 2A process produces wherein n ⁺ denotes a high impurity concentration of dopants, resulting in an n-type conductivity , ie for example of arsenic or phosphorus. Between the regions 20 and 22 there are buried p ⁺ regions 24, 26 and 28 lying in the same plane. The region 20 belongs to the photodiode 14, which is shown laterally interrupted in FIG. For example, the photodiode 14 has an extension of fifty micrometers. Above the area 20 there is an intermediate area 30 of the photodiode 14 which is weakly n-doped, ie n ^~ . The intermediate region 30 is completely laterally surrounded by an, for example, annular connection region 32, which is n-doped, but with a higher dopant concentration than that Intermediate region 30. The connection region 32 is n ⁺ -doped at its section 34 remote from the substrate to ensure a low contact resistance. Conductors 36 and 38 penetrate one or more metallization layers 40 of the integrated circuit arrangement 10 and lead to the section 34 of the connection area 32.

A p ⁺ -doped region 42, which forms the anode of the photodiode 14, is located on the intermediate region 30. An interconnect 44 penetrates the metallization layers 40 and is connected to the area 42.

A recess 46 is located in the metallization layers 40 above the area 42. Light can reach the photodiode 14 through the recess 46 in order to influence its electrical properties. The recess 46 is designed such that incident light can penetrate the photodiode 14 as completely as possible, e.g. due to the use of an anti-reflection layer.

P-doped regions 48 to 54 of a layer 55, which also contains the intermediate region 30, are located in the same plane as the intermediate region 30. The areas 48 and 50 adjoin the connection area 32 outside the photodiode 14. The area 52 forms a so-called bulk or circuit substrate and is part of the shielded area 16. On the side, the area 52 is delimited by a connection area 56, which is also ring-shaped, for example, which extends to the decoupling area 22 and the area 52 from the area 50 and 54 separates.

The connection area 56 and the area 22 form a shielding trough, which provides functions of a suction diode operated in the blocking direction. Within the shielded area 16 there are components with strong interference radiation, for example an npn transistor 58 and further components 60, for example CMOS components (complementary metal oxide semiconductor) or with one or more passive components, such as coils. The npn transistor 58 and devices 60 have been fabricated using standard manufacturing techniques.

For example, the npn transistor 58 contains a buried collector connection region 62, which is heavily n-doped, ie n ⁺ , and leads to a collector region 64. The collector region 64 is weakly n-doped, ie n ^" . Above the collector region 64 there is a base region 66 which is heavily p-doped and an emitter region 68 which is heavily n-doped. The metallization layers 40 are in the region of the transistor 58 for example penetrated by interconnects 70, 72 and 74, which lead in this order to the base region 66, to the emitter region 68 and to the collector connection region 62.

The connection region 56 is likewise n-doped and has a section 76 which is remote from the substrate and is n ⁺ -doped. Conductors 78 and 80 lead to the connection area 56 and serve, for example, to apply a positive operating voltage potential UP to the connection area 56 and thus also to the layer 22, which form the cathode of a suction diode operated in the reverse direction. The suction diode completely shields noise currents that could get into the substrate 12.

The areas 52 and 54 are also referred to as p-well.

The area 18 of the integrated circuit arrangement contains a large number of electronic components 82, which are indicated by three points in FIG. Interferences generated by the transistor 58 and the components 60 cannot penetrate to the components 82 due to the shielding through the shielding trough formed from the connection region 56 and the region 22. FIG. 1 also shows so-called field oxide regions 84 to 100, which consist for example of silicon dioxide and electrically isolate individual components or functional units of components from one another.

In another exemplary embodiment, the interconnects in the metallization layers 40 connect different components of the integrated circuit arrangement 10, e.g. the photodiode 14 with a transistor.

FIG. 2A shows a first production stage in the production of the integrated circuit arrangement 10. A silicon dioxide layer 110 is first produced on the substrate 12, for example by thermal oxidation. The thickness of the silicon dioxide layer 110 is, for example, fifty nanometers. A silicon nitride layer 112 is then deposited, which for example also has a thickness of fifty nanometers.

A lithography process is then performed to create an implantation mask for implanting dopants for layers 20 and 22. For this purpose, a photoresist layer 114 is applied over the entire surface and structured in a subsequent exposure and development step in such a way that cutouts 116 and 118 arise above the areas in which the areas 20 and 22 are to be produced; The silicon nitride layer 112 is then selectively removed from the silicon dioxide layer 110 in the areas not covered by the photoresist 114, for example in a dry etching process. After structuring the silicon nitride layer 112, an ion implantation is carried out, for example in order to implant arsenic or antimony ions, see arrows 120.

Thereafter, as shown in FIG. 2B, the remaining portion of the photoresist layer 114 is removed. Local oxidation is then carried out, thicker oxide regions 130 being found in the exposed regions of the silicon dioxide layer 110. be fathered. The dopants in regions 20 and 22 are also activated during the oxidation.

As shown in FIG. 2C, the residues of the nitride layer 112 are then removed, for example with the aid of an etching process. The regions 24 to 28 are then generated with the aid of an ion implantation 140. For example, boron is implanted. The energy during implantation is such that the boron ions do not penetrate the oxide regions 130. In contrast, regions of the silicon dioxide layer 110, the thickness of which did not change when the oxidation regions 130 were produced, are penetrated by the boron ions.

As shown in FIG. 2D, the oxide regions 130 and the remaining regions of the silicon dioxide layer 110 are subsequently removed. A layer 55 is applied to the layers 20 and 22 and the regions 24, 26 and 28 using an epitaxy method. Layer 55 is weakly n-doped, for example. In the exemplary embodiment, the layer 55 has a thickness of ten micrometers. The dopant concentration in layer 55 is, for example, 5-10 ¹³ particles per cubic centimeter.

A thin silicon dioxide layer 152 is then applied to the layer 55. A photoresist layer 154 is then applied in a lithography process and structured as a mask for a subsequent ion implantation. Recesses 156 to 162 are produced in the photoresist layer 154 at the regions lying above the edges of the regions 20 and 22. An ion implantation is then carried out, for example with phosphorus ions. The energy at the

Ion implantation is dimensioned such that the phosphorus ions do not penetrate the photoresist layer 154. Thus, the phosphorus ions only reach the original doping regions 164 to 170 directly under the cutouts 156 to 162. For example, the dopant concentration in the original doping regions 164 to 170 is 10 ¹⁶ dopant particles per cubic Centimeter. The ion implantation is represented by arrows 172 in FIG. 2D.

Thereafter, residues of the photoresist layer 154 are removed. With the help of a photo technique, a new photoresist mask is created, which has cutouts in areas in which the layer 55 is to be p-doped. The regions 48, 50, 52 and 54 below the silicon dioxide layer 152 are then doped with the aid of an ion implantation, for example with boron ions.

A diffusion process is then carried out, for example using a diffusion furnace. On the one hand, the dopants diffuse from the original doping regions 164 to 170 to the regions 20 and 22, the connection regions 32 and 56 being formed. The dopants, which lead to a p-type conduction in these regions 48, 50, 52 and 54, are also distributed within the regions 48, 50, 52 and 54.

In another process variant of the method explained with reference to FIG. 2B, an additional lithography method is carried out instead of the local oxidation. In this case, no silicon nitride layer 112 has to be applied. When using a lithography method it can also be achieved that, for example, only regions 24 and 26, but not region 28, are generated.

In a next process variant, a phosphor glass coating is used instead of the ion implantation in order to generate the doping regions.

In another process variant, the connection regions 32 and 56 are not produced by diffusion, but rather by producing deep trenches, into which doped polysilicon or a metal is then introduced.

Claims

claims 1. A method for producing an integrated pin diode (14), in particular a pin photodiode (14), with the steps carried out without limitation by the specified order: Generating a doped region (20) of a conduction type close to the substrate with respect to a carrier substrate, Producing a doped region (42) further away from the carrier substrate (12) than the region (20) near the substrate and of a different conduction type than the conduction type of the region (20) near the substrate, Producing an intermediate region (30) which is arranged between the region (20) close to the substrate and the region (42) remote from the substrate and which is undoped or provided with a weak doping compared to the doping of the region close to the substrate (20) and the doping of the region (42) remote from the substrate and generating at least one electrically conductive connection region (32), which leads to the region (20) close to the substrate, in a layer (55) containing the intermediate region (30). 2. The method according to claim 1, characterized in that the connection region (32) penetrates the layer (55) from its interface remote from the substrate to its interface close to the substrate. 3. The method according to claim 1 or 2, characterized by the steps: Producing a doped decoupling region (22) simultaneously with the production of the region (20) close to the substrate, and generating a circuit arrangement (10) carried by the carrier substrate with at least two components (58, 60, 82), the decoupling region (22) preferably between a part of the components (58, 60) and the carrier substrate (12) and not between the other part of the components (82) and the carrier substrate (12). 4th Method according to claim 3, g e k e n n z e i c h n e t d r c h the step: Generating an electrically conductive decoupling area connection area (56) simultaneously with the creation of the connection area (32) leading to the area near the substrate (20). 5. The method according to claim 4, characterized by the fact that the decoupling area connection area (56) and the decoupling area (22) form a shielding trough which completely or in relation to the side surfaces and the base of the at least fifty percent or at least seventy-five percent. 6. The method according to any one of claims 3 to 5, so that the layer (55), in which the substrate-near region (20) and the decoupling region (22) are arranged, regions outside this region (20, 22) are provided with a doping of another conductivity type, an oxide (130) covering the region near the substrate (20) and the decoupling region (22) preferably being used to mask an implantation (140), or that in the layer (55) in which the substrate-near region (20) and the decoupling region (22) are arranged, regions outside these regions (20) are undoped or are selectively doped. 7. The method according to any one of the preceding claims, characterized in that the connection region (32, 56) is produced by producing a trench which is preferably at least twice as deep as it is wide, or that the connection area (32, 56) is produced with the aid of a diffusion process in which dopants diffuse from an area remote from the substrate to the layer (20) close to the substrate, and / or that the connection region (32, 56) is generated with an implantation method, preferably with a high-energy one. 8. The method according to any one of the preceding claims, characterized by the fact that the layer (55) containing the intermediate region (30) is produced using an epitaxial method, and / or that in the epitaxial process at the same time Base material for an embedding area (52, 54) is generated, which is used for embedding components (58, 60, 82) of an integrated circuit arrangement (10). 9. The method according to claim 8, characterized in that an epitaxial process for producing an epitaxial layer is carried out at least in two stages, interrupting epitaxial growth, wherein at least one other process is carried out after the interruption, preferably a doping process for producing a doping that differs from a doping of the epitaxial layer, and wherein after performing the other process, the epitaxial layer continues to grow. 10. The method according to any one of the preceding claims, characterized in that the connection region (32) leading to the region near the substrate (20) laterally encompasses the intermediate region (30), preferably completely. 11. The method as claimed in one of the preceding claims, characterized in that the layer (55) containing the intermediate region (30) is a semiconductor layer which preferably contains regions with different conductivity types. 12. The method according to any one of the preceding claims, characterized in that the decoupling area (22) adjoins material (12, 52, 54) with a different line type or is surrounded by material with a different line type, preferably apart from one or more decoupling area connection area. (56) on all sides. 13. Integrated circuit arrangement (10) with pin diode (14), in particular with pin photodiode (14), with a carrier substrate (12) which carries a region sequence of a pin diode (14), with a doped region (20) of a conductivity type contained in the region sequence, with a doped region (42) which is remote from the substrate and is contained in the region sequence and is of a different conduction type than the conduction type of the region (20) near the substrate, with an undoped intermediate region (30) arranged between the region (20) close to the substrate and the region remote from the substrate (42) or weakly doped compared to the doping of the region close to the substrate (20) and the doping of the region remote from the substrate (42), and with an electrically conductive connection region (32) which leads to the region (20) close to the substrate and is arranged in a layer (55) which contains the intermediate region (30). 14. Circuit arrangement (10) according to claim 13, so that the connection area (32) penetrates the layer (55) from its interface remote from the substrate to its interface close to the substrate. 15. The circuit arrangement (10) according to claim 13 or 14, characterized by a circuit arrangement (10) carried by the carrier substrate (12) and containing at least two electronic components (58, 60, 82), and by means of a doped decoupling region (22) of the same conduction type arranged between the one component (58) and the carrier substrate (12) as the region (20) near the substrate and / or the same dopant concentration as the region (20) near the substrate and / or arranged in a plane with the region close to the substrate (20). 16. The circuit arrangement (10) as claimed in claim 15, characterized by an electrically conductive decoupling area connection area (56) which leads to the decoupling area (22) and / or which has the same material composition as the connection area (20) leading to the substrate area (20). 32) has. 17. Circuit arrangement (10) according to one of claims 13 to 16, so that the circuit arrangement (10) has been produced by a method according to one of claims 1 to 12.