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EP1428367A2 - Hierarchical modulation - Google Patents

Hierarchical modulation

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Publication number
EP1428367A2
EP1428367A2 EP02762167A EP02762167A EP1428367A2 EP 1428367 A2 EP1428367 A2 EP 1428367A2 EP 02762167 A EP02762167 A EP 02762167A EP 02762167 A EP02762167 A EP 02762167A EP 1428367 A2 EP1428367 A2 EP 1428367A2
Authority
EP
European Patent Office
Prior art keywords
data
bit
bits
digital word
mapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02762167A
Other languages
German (de)
French (fr)
Inventor
Octavian V. Sarca
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Redline Communications Inc
Original Assignee
Redline Communications Inc
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Filing date
Publication date
Application filed by Redline Communications Inc filed Critical Redline Communications Inc
Publication of EP1428367A2 publication Critical patent/EP1428367A2/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/32Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488Multiresolution systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/183Multiresolution systems

Definitions

  • the present invention relates to wireless communications and is particularly concerned with modulation schemes for digital data.
  • Fig. 1 shows the typical block diagram of a transmitter for wireless communications.
  • the process that transforms the input data 10 into an RF signal involves scrambling and forward-error-correction (FEC) encoding 12, interleaving 14,
  • FEC forward-error-correction
  • Gray encoding 16 symbol mapping 18, wave mapping, up-conversion and amplification 20.
  • Fig. 2 shows the typical block diagram of corresponding receiver for wireless communications with the transmitter of Fig. 1.
  • the process that transforms the received RF signal into received data in made of the inverses of the operations in the transmit chain, placed in reversed order: amplification, down-conversion, wave de- mapping 22, symbol de-mapping 24, gray decoding 26, de-interleaving 28, FEC decoding and de-scrambling 30.
  • Fig. 2 does not include channel estimation or equalization functions.
  • the scrambler 12 randomizes the input data to remove repetitive and constant sequences, and to ensure a uniform, white-noise like spectrum at the output.
  • the de- scrambler provides the inverse operation, thereby returning the scrambled signal to its original form.
  • Forward-error-correction (FEC) encoding 12 adds redundancy to the input data stream that is used by FEC decoding in the receiver to detect and correct transmission errors.
  • Interleaving 14 spreads the data quasi-randomly in time and, for multi-carrier modulations, in frequency. It also spreads data bits among different modulation levels: c n- ⁇ , ..., ci, c ⁇ Interleaving 14 and de-interleaving 28 ensure that error bursts (errors located close in time or frequency) in the received data are spread in such a way that FEC decoding 30 can correct them with similar performance as uniform errors.
  • Gray encoding 16 maps n binary inputs c n- ⁇ , ..., ci, c 0 into n binary outputs b n- i, ..., bi, bo using formulas:
  • Gray decoding 26 performs the inverse operation using formulas:
  • Gray encoding 16 and decoding 26 ensure that the noise in the received signal causes the minimum number of bit errors. More details are given herein below.
  • Symbol mapping 18 transforms n binary inputs b n- ⁇ , ..., bi, b 0 in one analog output y.
  • Symbol de-mapping 24 performs the inverse operation - it extracts n binary outputs b n _ ⁇ , ..., bj, b 0 from one analog input y. More details are given herein below.
  • Wave mapping 20 takes the stream of symbols y(k) and constructs a baseband signal. Some modulations, usually called quadrature modulations, transform each pair of two real symbols y(2k) and y(2k+l) into a complex symbol
  • Wave de-mapping 22 performs the inverse operation extracting the stream of symbols y(k) from the received baseband signal.
  • the up-conversion shifts 20 the spectrum of the modulated signal from baseband to RF.
  • the down-conversion 22 provides the inverse operation.
  • amplification is needed to obtain the desired power at the antenna.
  • amplification is needed to compensate the losses in the channel and to rise the signal level to the point where the following blocks can process it.
  • Symbol mapping 18 transforms n binary inputs b n- ⁇ , ..., b ⁇ , bo in one analog output y using formula:
  • y (2° xo + 2 1 x, + ... + 2 ⁇ -' x n-1 )/sqrt(2° + 2 2 + ... + 2 2 n'1 )
  • Fig. 3 shows a typical implementation of symbol mapping 18.
  • Fig. 4 shows a typical implementation of symbol de-mapping.
  • Symbol de- mapping 24 performs the inverse operation where n binary outputs b route.
  • the analog input y at input 44 is first multiplied 46 by the weighting factor sqrt(2° + 2 2 + ... + 2 2(n"1) ) at 49 and then passed through an n- bit slicer 50 to produce the bipolar number [x n- ⁇ ...xiXo] at 52.
  • the slicer operation 50 is similar to rounding: it chooses [x n-1 ...x ⁇ x 0 ] to be the closest to y-sqrt(2° + 2 2 + ... + 2 2(n-1) ).
  • the symbol value is shown in first column, the bipolar number in the second, the binary number in third, the Gray- coded bit vector in fourth and the bit vector before Gray coding in fifth.
  • the distance between two consecutive symbols is constant for a given n.
  • the distance between two consecutive symbols depends on n. For each additional bit the distance approximately halves which means that noise sensitivity is worsened by approximately 6dB for each additional bit.
  • Transitions between two consecutive symbols may cause one bit bi to change but may also cause all n bits bj to change (e.g. when [x n- ⁇ ...x ⁇ Xo] changes from -1 to 1). Due to Gray encoding, all one-symbol transitions cause only one bit c,- to change, all two-symbol transitions cause two bits to change and so.
  • the interleaving/de-interleaving scheme is used in an attempt ti mitigate the difference in error probability between levels.
  • the invention describes the method and apparatus to provide hierarchical modulation of data at transmission and hierarchical demodulation of data in the receiver.
  • Hierarchical modulation a number n of distinct data streams are encoded in a single symbol stream and subsequently into a single RF signal.
  • hierarchical demodulation extracts n data streams from the same RF signal.
  • Each data stream will provide a different level of protection against noise and interference.
  • the difference between data streams can be controlled using a single parameter a.
  • Fig. 1 illustrates a block diagram of a known transmitter for wireless data communications
  • Fig. 2 illustrates a block diagram of a known receiver for wireless data communications
  • Fig. 3 illustrates a typical implementation of symbol mapping
  • Fig. 4 illustrates a typical implementation of symbol de-mapping
  • Fig. 5 illustrates a block diagram of a hierarchical transmitter in accordance with an embodiment of the present invention
  • Fig. 6 illustrates a block diagram of a hierarchical receiver in accordance with an embodiment of the present invention
  • Fig. 7 illustrates an implementation of hierarchical symbol mapping of Fig. 5; and Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig. 6.
  • the hierarchical transmitter 60 includes a plurality of data inputs 62a-62n, a plurality of scrambling and FEC encoding blocks 64a-64n, and a plurality of interleaving blocks
  • a wave mapping up-conversion and amplification block 78 converts the analog symbols y to RF for output at 80 to antenna 82.
  • Each of the n input data streams (62a-n) is processed separately through independent scrambling, FEC encoding and interleaving.
  • Scrambling, FEC encoding and interleaving applied to each data stream are functionally similar to the blocks with the same name from known transmitters (Fig.l), except that they each operate on only 1/n-th part of the data.
  • Gray encoding, wave mapping, up-conversion and amplification are functionally similar to the blocks with the same name from known transmitters (Fig.l). Symbol mapping from known transmitters may also be used in a hierarchical transmitter, but an improved hierarchical symbol mapping described herein below is recommended.
  • the hierarchical receiver 90 includes an antenna 92 for receiving an RF signal at 94, an amplification, down-conversion, wave demapping block 96 for deriving a symbol y at 98, a symbol demapping block 100 having a plurality of outputs 102a-102n, a gray decoding block 104 having a plurality of outputs 106a-106n and a plurality of series connected de- interleaving (108a-n), de-scrambler and FEC decoding and data outputs HOa-n.
  • the receiver 90 performs the inverses of the operations in the transmit chain of Fig.
  • the received RF signal 94 is first passed through amplification, down-conversion, wave de-mapping 96, symbol de-mapping 100 and Gray decoding 104.
  • Amplification, down-conversion, wave de-mapping and Gray decoding are functionally similar to the blocks with the same name from known receivers (Fig.2). Symbol de-mapping can be either known or hierarchical depending what is used in the transmitter.
  • the n-bit data stream at the output of Gray-decoding 104 is split into n separate bit streams 106(a-n).
  • Each bit stream is then processed separately through de-interleaving 108(a-n), FEC decoding and de-scrambling 110(a- n) to produce n separate output data streams 112a-n.
  • De-interleaving, FEC decoding and de-scrambling applied to each bit stream are functionally similar to the blocks with the same name from known receivers, except that they each operate on only 1/n- th part of the data.
  • Hierarchical symbol mapping transforms n binary inputs b n- ⁇ , ..., bi, bo in one analog output y using formula:
  • FIG. 7 illustrates a implementation of hierarchical symbol mapping of Fig. 5.
  • the binary vector [b n- ⁇ ...b ⁇ bo] at 72a-72n is first serialized by a block 120 in order b n- ⁇ , ..., b ⁇ ,bo (b n- ⁇ first) at output 122.
  • the register 132 contains zero.
  • the register 132 is clocked n-times (one clock for each bit) before its contents will passed to the second multiplier 142.
  • One can easily verify that the content of the register 142 is x n- ⁇ after the first clock, x n-2 +ax n - ⁇ after the second, x n-3 +ax n-2 +a x n- ⁇ after third and so on up to a 0 xo+a 1 x ⁇ +...+a n"1 x n- ⁇ after n clocks.
  • This result is finally passed through the second multiplier 142 that applies the weighting factor at 144 of l/sqrt(a° + a 2 + ... + a 2(n - 1) ).
  • the hierarchical mapping requires only few low-cost components: one parallel to series converter 120, one adder 128, one register
  • the constant a can be approximated without any impact on the system performance since the same approximation can be used in de-mapping (see below).
  • Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig.
  • Hierarchical symbol de-mapping performs the inverse of the mapping of the transmitter, if operated with the same constant a.
  • the de-mapping extracts n binary outputs b n -i, ..., bi, bo from a single analog input y.
  • the analog input y at 98 is first multiplied 150 by the weighting factor sqrt(a° + a 2 + ... + a 2 1"0 )/a n" ' at input 152.
  • the register 160 and the serial-to-parallel converter 170 must be clocked n times for each input value y.
  • the switch 156 is positioned as depicted allowing the weighted input to be clocked into the register.
  • the switch 156 connects the register 160 input to the second multiplier 166.
  • the 1-bit slicer 162 outputs +1 if its input is greater than zero and -1 otherwise.
  • the slicer will output x n- ⁇ , which is converted to b n- ⁇ by the bipolar-to-binary converter 168 and loaded into the serial-to-parallel converter 170.
  • x n- ⁇ is subtracted at 164 from the register output and the result is multiplied by a at 166.
  • the symbol value is shown in first column, the Gray-coded bit vector in second and the bit vector before Gray coding in third.
  • n and a can be trimmed to obtain the desired number of levels and the desired range, respectively.
  • PAPR peak to average power ratio
  • the number bits is usually chosen adaptively according to the channel characteristics, i.e. to the achievable signal to noise ratio (SNR).
  • SNR signal to noise ratio
  • the receiver replies with an automatic retransmission request (ARQ) for each packet lost.
  • ARQ automatic retransmission request
  • the transmitter estimates the average packet-error-rate (PER) based on the number of ARQ received per quantity of packets sent and adjusts the number of bits per symbol n accordingly.
  • the receiver periodically reports the average SNR to the transmitter. For slowly varying channels both methods gives good and reliable results.
  • n-i provides reliable communication under worst channel conditions
  • these parameters can be used for all transmissions.
  • packets will be transmitted successfully via one or more data streams.
  • the ARQ will still be used to retransmit the unsuccessful packets.
  • retransmissions may only be performed on higher levels in the hierarchy to reduce the number of retransmissions per each particular packet (i.e. to reduce the delay).
  • n and a are chosen ensures that at least one data stream is reliable under all situations and that the bandwidth is effectively and efficiently used.
  • Hierarchical modulation ensures better utilization of the channel because it makes effective use of temporary SNR improvements.
  • Hierarchical modulation provides a smooth degradation of the overall data rate with the degradation of the SNR. This is because, as the SNR degrades, the number of successful data streams decreases. With known non-hierarchical modulation, degradation is sharp. In other words, either all data stream are successful or none.
  • the hierarchical modulation is more reliable than the known modulation because higher levels are better protected to noise.
  • Hierarchical modulation provides more robust error detection. It is known that error detection codes can misdiagnose packets with many errors. With hierarchical modulation, once one level is detected to have errors, all the Tower levels in the hierarchy can be declared unreliable because they are much more sensitive to noise. With known modulation, all levels are mixed together so there is no hierarchy to help the error detection.
  • Hierarchical modulation allows vital (e.g. management and control) information to be sent with higher reliability than data while preserving the nominal data rate (number of bits/symbol).
  • the higher reliability can only be achieved by decreasing the data rate, i.e. the number of bits/symbol.
  • BS base-station
  • SS subscriber-stations
  • the BS must adjust its number of bits per symbol according to the channel to a particular SS, e.g. it will transmit with more bits for near SS's and less bits for far SS's.
  • the vital management and control information is sent in such situations with minimum number of bits/symbol in order to ensure reliable reception by all SS's.
  • the BS will waste precious bandwidth in order to reach the far SS's.
  • the BS can send packets for near stations on lower levels and packets for far stations on higher levels.
  • This we define this as hierarchy- division-multiplexing (HDM).
  • HDM hierarchy- division-multiplexing
  • the BS does not need to decrease the data rate to reach the far SS's since their designated information is encoded in most robust levels of the hierarchy. As the far stations ignore lower levels, it is of no consequence that the lower levels will be received with errors. However, near SS's will be able to decode correctly the lower levels where their designated information is placed.
  • HDM has the following advantages: a) HDM ensures better utilization of the channel because it effectively uses the SNR differences. b) HDM allows vital (e.g. management and control) information to be transmitted with higher reliability without wasting bandwidth. This is because vital information can be encoded in the most reliable level while other levels are used for data. HDM also provides more robustness to burst noise and narrow band interference because the control data is spread both in time and frequency instead of being concentrated. c) HDM is very flexible and permits different combinations of a and n to be chosen according to each particular set of SS's to which the packets are designated.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Noise Elimination (AREA)

Abstract

A method of hierarchically modulating and demodulating data, whereby a number of distinct data streams are encoded in a single symbol stream and subsequently into a single RF signal. At reception, hierarchical demodulation extracts these distinct data streams from the same RF signal. Each data stream provides a different level of protection against noise and interference and the difference between data streams can be controlled using a single parameter.

Description

HIERARCHICAL MODULATION
Field of the Invention
The present invention relates to wireless communications and is particularly concerned with modulation schemes for digital data.
Background of the Invention
Wireless communication systems for digital data transmission and reception are known.
Fig. 1 shows the typical block diagram of a transmitter for wireless communications. The process that transforms the input data 10 into an RF signal involves scrambling and forward-error-correction (FEC) encoding 12, interleaving 14,
Gray encoding 16, symbol mapping 18, wave mapping, up-conversion and amplification 20.
Fig. 2 shows the typical block diagram of corresponding receiver for wireless communications with the transmitter of Fig. 1. The process that transforms the received RF signal into received data in made of the inverses of the operations in the transmit chain, placed in reversed order: amplification, down-conversion, wave de- mapping 22, symbol de-mapping 24, gray decoding 26, de-interleaving 28, FEC decoding and de-scrambling 30. For simplicity, Fig. 2 does not include channel estimation or equalization functions.
The scrambler 12 randomizes the input data to remove repetitive and constant sequences, and to ensure a uniform, white-noise like spectrum at the output. The de- scrambler provides the inverse operation, thereby returning the scrambled signal to its original form. Forward-error-correction (FEC) encoding 12 adds redundancy to the input data stream that is used by FEC decoding in the receiver to detect and correct transmission errors.
Interleaving 14 spreads the data quasi-randomly in time and, for multi-carrier modulations, in frequency. It also spreads data bits among different modulation levels: cn-ι, ..., ci, c< Interleaving 14 and de-interleaving 28 ensure that error bursts (errors located close in time or frequency) in the received data are spread in such a way that FEC decoding 30 can correct them with similar performance as uniform errors.
Gray encoding 16 maps n binary inputs cn-ι, ..., ci, c0 into n binary outputs bn- i, ..., bi, bo using formulas:
• bn-l = Cπ-l
• bj = Cj θ Ci+i for i = 0, 1, ..., n-2
Gray decoding 26 performs the inverse operation using formulas:
• cn-ι = bn-ι • Cj = bj θ bi+i for i = 0, 1, ..., n-2
Gray encoding 16 and decoding 26 ensure that the noise in the received signal causes the minimum number of bit errors. More details are given herein below.
Symbol mapping 18 transforms n binary inputs bn-ι, ..., bi, b0 in one analog output y. Symbol de-mapping 24 performs the inverse operation - it extracts n binary outputs bn_ι, ..., bj, b0 from one analog input y. More details are given herein below.
Wave mapping 20 takes the stream of symbols y(k) and constructs a baseband signal. Some modulations, usually called quadrature modulations, transform each pair of two real symbols y(2k) and y(2k+l) into a complex symbol
(y(2k)+jy(2k+l))/sqrt(2) before constructing the signal, where sqrt(.) denotes the square root function. Some modulations map real or complex symbols in time only (single-carrier systems like QAM, 8VSB) while others map the symbols both in time and frequency (multi-carrier systems e.g. OFDM). Wave de-mapping 22 performs the inverse operation extracting the stream of symbols y(k) from the received baseband signal.
The up-conversion shifts 20 the spectrum of the modulated signal from baseband to RF. The down-conversion 22 provides the inverse operation.
At transmission, amplification is needed to obtain the desired power at the antenna. At reception, amplification is needed to compensate the losses in the channel and to rise the signal level to the point where the following blocks can process it.
Symbol mapping 18 transforms n binary inputs bn-ι, ..., b\, bo in one analog output y using formula:
y = (2° xo + 21 x, + ... + 2π-' xn-1)/sqrt(2° + 22 + ... + 22 n'1 ) where sqrt(.) denotes square root function and each Xj , i = 0, 1, ..., n-1 is the result of binary-to-bipolar conversion of data bit bj defined by Xj = 2b; -1 (some systems may use Xi = 1 - 2bj) with bi 6 {0, 1} and Xi e {-1, 1}.
Fig. 3 shows a typical implementation of symbol mapping 18. In the Fig. 3, the binary number: [bn-ι...bjb0] = 2° b0 + 21 bi + ... + 2"*1 bn-ι at 32 is first transformed by 34 to a bipolar number 36 using a formula: [xn-ι...XιXo] = 2[bn- i ...bιbo]-(2n-l). Then, the bipolar number 36 is multiplied 38 by the weighting factor l/sqrt(2° + 22 +...+ 22(n'°) at 40 to produce y at 42.
Fig. 4 shows a typical implementation of symbol de-mapping. Symbol de- mapping 24 performs the inverse operation where n binary outputs b„.|, ..., bi, bo are extracted from an analog input y. The analog input y at input 44 is first multiplied 46 by the weighting factor sqrt(2° + 22 + ... + 22(n"1)) at 49 and then passed through an n- bit slicer 50 to produce the bipolar number [xn-ι ...xiXo] at 52. The slicer operation 50 is similar to rounding: it chooses [xn-1...xιx0] to be the closest to y-sqrt(2° + 22 + ... + 22(n-1) ). Finally, the bipolar number [xn-( ...xiXo] is converted at 54 to a binary number [bn-i ...bibo] = ([xn-i . ■ .xιx0]+2π-l)/2 at output 56.
Table A, Table B, Table C and Table D give examples of mapping/de- mapping for n=l , 2, 3 and 4 bits/symbol. In each table, the symbol value is shown in first column, the bipolar number in the second, the binary number in third, the Gray- coded bit vector in fourth and the bit vector before Gray coding in fifth. We note the following:
The distance between two consecutive symbols is constant for a given n. The distance between two consecutive symbols depends on n. For each additional bit the distance approximately halves which means that noise sensitivity is worsened by approximately 6dB for each additional bit.
Transitions between two consecutive symbols may cause one bit bi to change but may also cause all n bits bj to change (e.g. when [xn-ι ...xιXo] changes from -1 to 1). Due to Gray encoding, all one-symbol transitions cause only one bit c,- to change, all two-symbol transitions cause two bits to change and so.
Even with Gray coding, the bits have different probability of error. The most significant bit cn-ι has only one transition that causes its value to change, while cn-2 has two, cn-3 has three and so on. Consequently, the probability of having an error on level i (i.e. on Cj) approximately doubles for every decrement in i.
Typically, the interleaving/de-interleaving scheme is used in an attempt ti mitigate the difference in error probability between levels.
Table A: Symbol mapping for n=l bit/symbol
[xixo] [bibo bi 1bD,0 CiCo
Table B: Symbol mapping for n=2 bits/symbol
Table C: Symbol mapping for n=3 bits/symbol
Table D: Symbol mapping for n=4 bits/symbol Summary of the Invention
The invention describes the method and apparatus to provide hierarchical modulation of data at transmission and hierarchical demodulation of data in the receiver.
With hierarchical modulation a number n of distinct data streams are encoded in a single symbol stream and subsequently into a single RF signal. At reception, hierarchical demodulation extracts n data streams from the same RF signal.
Each data stream will provide a different level of protection against noise and interference. The difference between data streams can be controlled using a single parameter a.
Efficient implementations for hierarchical modulation and for hierarchical demodulation are described.
Application of hierarchical modulation to wireless communications in fast changing channels is described and shown to give significant improvements over • traditional methods.
Application of hierarchical modulation to wireless point to multi-point (PMP) is described and shown to give significant improvements over known methods.
Brief Description of the Drawings
The present invention will be further understood from the follow detailed description in which:
Fig. 1 illustrates a block diagram of a known transmitter for wireless data communications;
Fig. 2 illustrates a block diagram of a known receiver for wireless data communications;
Fig. 3 illustrates a typical implementation of symbol mapping; Fig. 4 illustrates a typical implementation of symbol de-mapping; Fig. 5 illustrates a block diagram of a hierarchical transmitter in accordance with an embodiment of the present invention;
Fig. 6 illustrates a block diagram of a hierarchical receiver in accordance with an embodiment of the present invention;
Fig. 7 illustrates an implementation of hierarchical symbol mapping of Fig. 5; and Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig. 6.
Detailed Description of the Preferred Embodiment
Referring to Fig. 5 there is illustrated in a block diagram a hierarchical transmitter in accordance with an embodiment of the present invention. The hierarchical transmitter 60 includes a plurality of data inputs 62a-62n, a plurality of scrambling and FEC encoding blocks 64a-64n, and a plurality of interleaving blocks
66a-66n, each series connected with its corresponding adjacent block, to a gray encoding block 68 having a corresponding plurality of inputs 70a-70n and a corresponding plurality of outputs 72a-72n applied as inputs to a symbol mapping block 74 having an output 76 for y. A wave mapping up-conversion and amplification block 78 converts the analog symbols y to RF for output at 80 to antenna 82. Each of the n input data streams (62a-n) is processed separately through independent scrambling, FEC encoding and interleaving. Scrambling, FEC encoding and interleaving applied to each data stream are functionally similar to the blocks with the same name from known transmitters (Fig.l), except that they each operate on only 1/n-th part of the data. The n separate bit streams at outputs (70a-n) of interleavers
(66a-n) are transformed into a single n-bit data stream at the input to the Gray encoding block 68. The joined data stream is then processed through Gray encoding 68, symbol mapping 74, wave mapping, up-conversion and amplification 78 to produce the RF signal 80. Gray encoding, wave mapping, up-conversion and amplification are functionally similar to the blocks with the same name from known transmitters (Fig.l). Symbol mapping from known transmitters may also be used in a hierarchical transmitter, but an improved hierarchical symbol mapping described herein below is recommended.
Referring to Fig. 6, there is illustrated in a block diagram a hierarchical receiver in accordance with an embodiment of the present invention. The hierarchical receiver 90 includes an antenna 92 for receiving an RF signal at 94, an amplification, down-conversion, wave demapping block 96 for deriving a symbol y at 98, a symbol demapping block 100 having a plurality of outputs 102a-102n, a gray decoding block 104 having a plurality of outputs 106a-106n and a plurality of series connected de- interleaving (108a-n), de-scrambler and FEC decoding and data outputs HOa-n. The receiver 90 performs the inverses of the operations in the transmit chain of Fig. 5, placed in reverse order. The received RF signal 94 is first passed through amplification, down-conversion, wave de-mapping 96, symbol de-mapping 100 and Gray decoding 104. Amplification, down-conversion, wave de-mapping and Gray decoding are functionally similar to the blocks with the same name from known receivers (Fig.2). Symbol de-mapping can be either known or hierarchical depending what is used in the transmitter. The n-bit data stream at the output of Gray-decoding 104 is split into n separate bit streams 106(a-n). Each bit stream is then processed separately through de-interleaving 108(a-n), FEC decoding and de-scrambling 110(a- n) to produce n separate output data streams 112a-n. De-interleaving, FEC decoding and de-scrambling applied to each bit stream are functionally similar to the blocks with the same name from known receivers, except that they each operate on only 1/n- th part of the data.
Hierarchical symbol mapping transforms n binary inputs bn-ι, ..., bi, bo in one analog output y using formula:
y = (a0 xo + a1 x, + ... + a"-1 xn.1)/sqrt(a° + a2 +.... + a2(n_I) ) where sqrt(.) denotes square root function and each x, , i = 0, 1, ..., n-1 is the result of binary-to-bipolar conversion of data bit bi defined by x; = 2b j -1 (x; = 1 - 2b j is also possible) with b,- e {0, 1} and x; e {-1, 1}. Note that for a=2 hierarchical symbol mapping performs the same operation as known symbol mapping. Fig. 7 illustrates a implementation of hierarchical symbol mapping of Fig. 5. In the figure, the binary vector [bn-ι...bιbo] at 72a-72n is first serialized by a block 120 in order bn-ι, ..., bι,bo (bn-ι first) at output 122. Each bit is then transformed from binary to bipolar by a block 124 using x; = 2bj-l (can be also j = 1- 2b;) and output at
126. By the moment Xj arrives at the input of the adder 128 the register 132 contains zero. The register 132 is clocked n-times (one clock for each bit) before its contents will passed to the second multiplier 142. One can easily verify that the content of the register 142 is xn-ι after the first clock, xn-2+axn-ι after the second, xn-3+axn-2+a xn-ι after third and so on up to a0xo+a1xι+...+an"1xn-ι after n clocks. This result is finally passed through the second multiplier 142 that applies the weighting factor at 144 of l/sqrt(a° + a2 + ... + a2(n-1)).
Compared to known mapping, the hierarchical mapping requires only few low-cost components: one parallel to series converter 120, one adder 128, one register
132 and one multiplier by constant a 136. As opposed to the weighting factor, the constant a can be approximated without any impact on the system performance since the same approximation can be used in de-mapping (see below).
Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig.
6. Hierarchical symbol de-mapping performs the inverse of the mapping of the transmitter, if operated with the same constant a. The de-mapping extracts n binary outputs bn-i, ..., bi, bo from a single analog input y. The analog input y at 98 is first multiplied 150 by the weighting factor sqrt(a° + a2 + ... + a2 1"0 )/an"' at input 152. To extract n binary outputs, the register 160 and the serial-to-parallel converter 170 must be clocked n times for each input value y. For the first clock, the switch 156 is positioned as depicted allowing the weighted input to be clocked into the register. For the other n-1 clocks, the switch 156 connects the register 160 input to the second multiplier 166. The 1-bit slicer 162 outputs +1 if its input is greater than zero and -1 otherwise. Following the first clock, the slicer will output xn-ι, which is converted to bn-ι by the bipolar-to-binary converter 168 and loaded into the serial-to-parallel converter 170. On the feedback path 172, xn-ι is subtracted at 164 from the register output and the result is multiplied by a at 166. One can easily verify that the slicer outputs xn-2 on second clock, xn- on third clock and so on until it outputs x0 on the n- th clock.
For n=l or a=2, the hierarchical symbol mapping is equivalent to known mapping. Table E, Table F, and Table G give examples of mapping/de-mapping for n=2, 3 and 4 bits/symbol and a=3. In each table, the symbol value is shown in first column, the Gray-coded bit vector in second and the bit vector before Gray coding in third. The tables are used only to illustrate several properties of hierarchical mapping/de-mapping. Embodiments of the invention are not limited to a=3 and they are not limited to an integer constant a. Any modulation with a≠2 should be considered embodiments of the present invention.
Table E: Hierarchical symbol mapping for n=2 bits/symbol and a=3
Table F: Hierarchical symbol mapping for n=3 bits/symbol and a=3
Table G: Hierarchical symbol mapping for n=4 bits/symbol and a=3
The distance between two consecutive symbols is not constant and depends on which bit Ci is changed by moving from one symbol to another. However, for all transitions causing bit Cj to change, the distance is constant. For example, if n=2 and a=3, the transitions on bit Co have an associated distance of 2 /sqrt(lθ) while the transition on bit ci has a double distance 4/sqrt(10).
Table H: Distance between consecutive symbols for a=3 and a=2
Table H compares symbol mappings with a=3 and a=2 (known) for n=2, 3 and 4 bits/symbol. We note that the distance between consecutive symbols in hierarchical mapping is smaller for lower levels (minimum for Co) and higher for upper levels (maximum for cn-ι) than the distance in known mapping. This means that with hierarchical modulation, lower levels will be more sensitive to noise than in the known mapping but upper levels will be more robust than in the known mapping. For example, with n=2 bits/carrier and a=3, Co is approximately 3dB more sensitive and ci is approximately 3dB more robust than in known mapping.
The distance between consecutive symbols decreases with n but, as opposed to known mapping, the levels are affected differently. With hierarchical mapping (a=3), increasing n with 1 bit symbol makes Co be approximately 9.5dB more sensitive to noise but affects c0 with less than ldB. With known mapping (a=2), increasing n with 1 bit/symbol makes all levels be approximately 6dB more sensitive to noise. The larger the a the more protected are the upper levels and the more affected are the lower levels. One can adjust a to obtain virtually any desired protection for upper levels.
One can easily prove that the distance on level Cj is dj = 2(a1"1 -2 -a°)
/sqrt(a° + a2 + ... + a ^"^ ). It can be easily verified that dj is constant for a=2 and that dj is monotonic with i for a>2. Thus bits encoded in Ci will be more reliable than those encoded in Cj.i and so on.
It can be also shown that the range of dj, i=0, 1, ..., n-1, is monotonic with a. Therefore, n and a can be trimmed to obtain the desired number of levels and the desired range, respectively.
The peak to average power ratio (PAPR) of the mapped symbols is smaller with a=3 than with a=2 (known). Table I summarizes PAPR for a=2, 3 and n=l, 2, 3, 4 bits/symbol. It can be shown that, for any n>l, mappings with a>2 always have lower PAPR than the known mapping. Lower PAPR means that a smaller amplifier can be eventually used in the final RF stages. This may lead to important cost savings.
Table I: PAPR for a=3 and a=2
With known modulation increasing the number of bits per symbol reduces the receiver tolerance for noise with approximately 6dB for each added bit. Therefore, in wireless communications the number bits is usually chosen adaptively according to the channel characteristics, i.e. to the achievable signal to noise ratio (SNR). Typically, the receiver replies with an automatic retransmission request (ARQ) for each packet lost. The transmitter estimates the average packet-error-rate (PER) based on the number of ARQ received per quantity of packets sent and adjusts the number of bits per symbol n accordingly. In other scenarios, the receiver periodically reports the average SNR to the transmitter. For slowly varying channels both methods gives good and reliable results.
However, there are many situations when the channel is changing very fast, virtually from one packet to another. For example, in mobile communications the path loss and consequently the received SNR varies dramatically. Another critical example is the operation in the license-exempt frequency bands where the interference is unpredictable because it is caused by similar devices sharing the same bandwidth hence the SNR can change by tens of dB from transmission to transmission. In such channels the above discussed known methods will choose the number bits per symbol n according to the minimum SNR to achieve reliable communication. However, with this procedure, the wireless system wastes a lot of bandwidth since it constantly uses an n adapted to worst channel conditions and consequently it does not effectively use the moments when the channel characteristics are good.
With hierarchical modulation one can choose n and a such as: Cn-i provides reliable communication under worst channel conditions
(minimum SNR) and
Co provides reliable communication under best channel conditions (maximum
SNR).
Then, these parameters can be used for all transmissions. Depending on particular channel conditions, packets will be transmitted successfully via one or more data streams. The ARQ will still be used to retransmit the unsuccessful packets.
However, retransmissions may only be performed on higher levels in the hierarchy to reduce the number of retransmissions per each particular packet (i.e. to reduce the delay). Hence, the way in which n and a are chosen ensures that at least one data stream is reliable under all situations and that the bandwidth is effectively and efficiently used. Hierarchical modulation ensures better utilization of the channel because it makes effective use of temporary SNR improvements.
Hierarchical modulation provides a smooth degradation of the overall data rate with the degradation of the SNR. This is because, as the SNR degrades, the number of successful data streams decreases. With known non-hierarchical modulation, degradation is sharp. In other words, either all data stream are successful or none.
For the same number of bits per symbol the hierarchical modulation is more reliable than the known modulation because higher levels are better protected to noise.
Hierarchical modulation provides more robust error detection. It is known that error detection codes can misdiagnose packets with many errors. With hierarchical modulation, once one level is detected to have errors, all the Tower levels in the hierarchy can be declared unreliable because they are much more sensitive to noise. With known modulation, all levels are mixed together so there is no hierarchy to help the error detection.
Hierarchical modulation allows vital (e.g. management and control) information to be sent with higher reliability than data while preserving the nominal data rate (number of bits/symbol). With known, non-hierarchical modulation, the higher reliability can only be achieved by decreasing the data rate, i.e. the number of bits/symbol.
In point to multi-point (PMP) communications a base-station (BS) must send both common and distinct information to subscriber-stations (SS) that are situated at different distances from BS. Multiplexing the SS's is typically performed with one of the following methods:
TDM/TDMA = time-division-multiplexing/multiple-access FDMA = frequency-division-multiple-access OFDMA = orthogonal- frequency-division-multiple-access
The different distances together with other channel conditions such as interference and line/non-line of sight (LOS/NLOS) may cause huge variations in achievable SNR from one SS to another SS. With any non-hierarchical modulation scheme, the BS must adjust its number of bits per symbol according to the channel to a particular SS, e.g. it will transmit with more bits for near SS's and less bits for far SS's. The vital management and control information is sent in such situations with minimum number of bits/symbol in order to ensure reliable reception by all SS's. Thus, the BS will waste precious bandwidth in order to reach the far SS's.
With hierarchical modulation, the BS can send packets for near stations on lower levels and packets for far stations on higher levels. We define this as hierarchy- division-multiplexing (HDM). When using HDM, the BS does not need to decrease the data rate to reach the far SS's since their designated information is encoded in most robust levels of the hierarchy. As the far stations ignore lower levels, it is of no consequence that the lower levels will be received with errors. However, near SS's will be able to decode correctly the lower levels where their designated information is placed.
HDM has the following advantages: a) HDM ensures better utilization of the channel because it effectively uses the SNR differences. b) HDM allows vital (e.g. management and control) information to be transmitted with higher reliability without wasting bandwidth. This is because vital information can be encoded in the most reliable level while other levels are used for data. HDM also provides more robustness to burst noise and narrow band interference because the control data is spread both in time and frequency instead of being concentrated. c) HDM is very flexible and permits different combinations of a and n to be chosen according to each particular set of SS's to which the packets are designated.

Claims

What is claimed is:
1. A method of modulation of data for a wireless communication system comprising the steps of:
a) separately encoding a plurality of data streams;
b) forming digital words, each word with one bit from each of the plurality of data streams, with each bit of given significance therein corresponding to the same data stream; and
c) mapping the digital word to a symbol so that the spacing between symbols is greater for bits of greater significance.
2. A method as claimed in claim 1 further comprising the step of assigning data with a higher priority for delivery to a data stream whose bits have a higher significance within the digital word.
3. A method as claimed in claim 2 wherein each data stream has a hierachical priority.
4. A method as claimed in claim 3 wherein the step of assigning data, assigns each of the plurality of data streams in order of data priority.
5. A method as claimed in claim 4 wherein the most significant bit of the digital word is assigned to system control data.
6. Apparatus for modulation of data for a wireless communication system comprising:
a) means for separately encoding a plurality of data streams;
b) means for forming digital words, each word with one bit from each of the plurality of data streams, with each bit of given significance therein corresponding to the same data stream; and
c) means for mapping the digital word to a symbol so that the spacing between symbols is greater for bits of greater significance.
7. Apparatus as claimed in claim 6 further comprising means for assigning data with a higher priority for delivery to a data stream whose bits have a higher significance within the digital word.
8. Apparatus as claimed in claim 7 wherein each data stream has a hierachical priority.
9. Apparatus as claimed in claim 8 wherein the means for assigning data, assigns each of the plurality of data streams in order of data priority.
10. Apparatus as claimed in claim 9 wherein the most significant bit of the digital word is assigned to system control data.
11. A method of transmitting data for a wireless communication system comprising the steps of: a) separately encoding a plurality of data streams;
b) forming digital words, each word with one bit from each of the plurality of data streams, with each bit of given significance therein corresponding to the same data stream; and
c) mapping the digital word to a symbol so that the spacing between symbols is greater for bits of greater significance.
12. A method as claimed in claim 11 further comprising the step of assigning data with a higher priority for delivery to a data stream whose bits have a higher significance within the digital word.
13. A method as claimed in claim 12 wherein each data stream has a hierachical priority.
14. A method as claimed in claim 13 wherein the step of assigning data, assigns each of the plurality of data streams in order of data priority.
15. A method as claimed in claim 14 wherein the most significant bit of the digital word is assigned to system control data.
16. A method as claimed in claim 14 wherein the wireless communications system provides reliable communications under worst channel conditions for the most significant bit.
17. A method as claimed in claim 14 wherein the wireless communications system provides reliable communications under best channel conditions for the least significant bit.
18. A method as claimed in claim 14 wherein the wireless communications system communicates with subscriber stations that are near and far and the more significant bits of the digital word is assigned to far subscriber stations.
19. A method as claimed in claim 14 wherein the wireless communications system communicates with subscriber stations that are near and far and lesser significant bits of the digital word is assigned to near subscriber stations.
20. Apparatus for transmitting data for a wireless communication system comprising:
a) means for separately encoding a plurality of data streams;
b) means for forming digital words, each word with one bit from each of the plurality of data streams, with each bit of given significance therein corresponding to the same data stream; and
c) means for mapping the digital word to a symbol so that the spacing between symbols is greater for bits of greater significance.
21. Apparatus as claimed in claim 20 further comprising means for assigning data with a higher priority for delivery to a data stream whose bits have a higher significance within the digital word.
22. Apparatus as claimed in claim 21 wherein each data stream has a hierarchical priority.
23. Apparatus as claimed in claim 22 wherein the means for assigning data, assigns each of the plurality of data streams in order of data priority.
24. Apparatus as claimed in claim 23 wherein the most significant bit of the digital word is assigned to system control data.
25. Apparatus as claimed in claim 20 wherein the wireless communications system includes parameters set to provide reliable communications under worst channel conditions for the most significant bit.
26. Apparatus as claimed in claim 20 wherein the wireless communications system includes parameters set to provide reliable communications under best channel conditions for the least significant bit.
27. Apparatus as claimed in claim 20 wherein the wireless communications system communicates with subscriber stations that are near and far and includes means for assigning more significant bits of the digital word is assigned to far subscriber stations.
28. Apparatus as claimed in claim 20 wherein the wireless communications system communicates with subscriber stations that are near and far and includes means for assigning lesser significant bits of the digital word is assigned to near subscriber stations.
EP02762167A 2001-09-13 2002-09-12 Hierarchical modulation Withdrawn EP1428367A2 (en)

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US20050113040A1 (en) * 2003-11-26 2005-05-26 Walker Glenn A. Method to minimize compatibility error in hierarchical modulation using variable phase
US7725799B2 (en) 2005-03-31 2010-05-25 Qualcomm Incorporated Power savings in hierarchically coded modulation
EP2139179A1 (en) * 2008-06-26 2009-12-30 THOMSON Licensing Method and apparatus for reporting state information
US8379769B2 (en) 2010-03-10 2013-02-19 Delphi Technologies, Inc. Communication system utilizing a hierarchically modulated signal and method thereof
FR2969449B1 (en) * 2010-12-17 2013-03-22 Thales Sa METHOD AND SYSTEM FOR TRANSMISSION USING ADAPTIVE AND PROGRAMMABLE HIERARCHICAL MODULATION
CN104333436A (en) * 2014-11-04 2015-02-04 杭州电子科技大学 M-QAM (M-ary Quadrature Amplitude Modulation) signal iterative decoding method for hierarchical coding modulation

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