EP1265288A2 - Semiconductor structure with buried conductive lines and method of electrically contacting of buried conductive lines - Google Patents

Abstract

Semiconductor structure comprises first parallel conducting pathways (303) arranged in a semiconductor substrate (301); second parallel conducting pathways (304) arranged on the substrate, isolated from the first conducting pathways and forming a grid with the first conducting pathways; and third conducting pathways arranged parallel with the first conducting pathways partially covering the second conducting pathways and isolated from the second conducting pathways. An electrical contact is provided between neighboring second conducting pathways and between the first and third conducting pathways. An Independent claim is also included for a process for electrically contacting conducting pathways provided in a semiconductor substrate. Preferred Features: A transistor is formed between neighboring first conducting pathways and second conducting pathways lying above. An oxide-nitride-oxide layer succession is arranged on the substrate below the second conducting pathways between neighboring first conducting pathways.

Description

The invention relates to a semiconductor structure buried conductor tracks and a method for electrical Contacting the buried conductor tracks.

According to the prior art, memory cell arrangements, for example, flash memory, as a large matrix Memory fields made of transistors. Both for Saving as well as reading out the memory cells is one certain arrangement of conductor tracks necessary. Doing so part of the conductor tracks as space optimization Bit lines (buried bitlines) in a semiconductor substrate diffused. However, diffused bit lines bring the problem with that the electrical resistances of the diffused bit lines are higher than the electrical Resistance of conductor tracks in metallization levels.

The level of resistance values of the diffused Bit lines are limited due to the resulting RC time constant hence the signal runtime. Under the term Signal runtime is the time required to understand can be written into memory cells or these can be read out. According to the prior art to reduce the signal runtime parallel to the diffused bit lines each a metallic Conductor used. These are metallic traces at regular intervals by means of contacts, so-called Stitch contacts, with the diffused bit lines electrically connected. This can increase the resistance effect of the diffused bit lines and thus the signal delay be reduced. For illustration is in Fig.1 and 2 shows a semiconductor structure, which one Represents memory cell arrangement.

1 shows a top view of a semiconductor structure 100 according to the prior art.

In a semiconductor substrate 101 is at one Substrate surface 102 a group of first conductor tracks 103 integrated. The first conductor tracks 103 are parallel arranged side by side and close with the Substrate surface 102 is essentially flush. The first conductor tracks 103 are usually formed by means of Diffusion of electrically conductive ions into the Semiconductor substrate 101 manufactured. The first conductor tracks 103 can be buried bit lines (buried bitlines) can be provided.

Furthermore, is located on the substrate surface 102 of the Semiconductor substrate 101 a group of second conductor tracks 104, which on the substrate surface 102 in parallel side by side and electrically insulated from the first conductor tracks 103 are arranged. The second conductor tracks 104 form together a regular grid with the first conductor tracks 103. The second conductor tracks 104 are usually formed by means of Common processes for the production of metallization levels generated.

Two adjacent first conductor tracks 103 and one each second conductor track 104 lying above form one Transistor. The first two conductor tracks 103 take over in Transistor area the function of the two transistor electrodes "Source" and "Drain", which is why the first conductor tracks 103 as Bit lines are called. The second interconnect 104 takes over the function of Transistor electrode "gate", which is why the second conductor tracks 104 are referred to as word lines.

An oxide-nitride-oxide layer sequence (not shown) made of silicon dioxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) is located on the substrate surface 102 in each transistor region between the first conductor tracks 103 and below every second conductor track 104, wherein in the silicon nitride layer can be stored up to two bits.

To reduce the electrical resistance, the first conductor tracks 103 by means of self-adjusting contacts 105 connected to metallic bit lines 106. This metallic bit lines 106 run parallel over the first conductor tracks 103, bridge the second conductor tracks 104 and are electrical to the second conductor tracks 104 isolated. There is a contact between the first Conductor tracks 103 and the metallic bit lines 106 in Direction of the metallic bit lines 106 by means of the self-adjusting contacts 105 after every four second Conductor tracks 104 are provided.

FIG. 2 shows a section of a cross section through the semiconductor structure 100 from FIG. 1 along the section line AA.

Above the substrate surface 102 and thus above that in the Semiconductor substrate 101 integrated first conductor tracks 103 there is a first insulation layer 201. The first Insulation layer 201 is for electrical insulation between the second conductor tracks 104 and the first Conductor tracks 103 are provided. Furthermore, the second are Conductor tracks 104 from a second insulation layer 202 encapsulated and fills a third insulation layer 203 empty areas between the second conductor tracks 104 to electrical insulation of the second conductor tracks 104 the self-adjusting contacts 105 and the metallic ones To ensure bit lines 106.

To generate the self-adjusting contacts 105 Usually the following process sequence is used: After the Creation of the first insulation layer 201 and the second Conductor tracks 104 become the second conductor tracks 104 of encapsulated in a second insulation layer 202. This will first one insulation material over the second Conductor tracks 104 deposited. Over the second conductor tracks 104, an etching mask is subsequently applied and the Insulation material in exposed areas, which are not from of the etching mask are covered up to the substrate surface 102 away. The etching mask is then removed again.

The third insulation layer 203 is then produced in the exposed openings between the second conductor tracks 104. An insulation material which can be etched selectively to the insulation material of the second insulation layer 202 is usually used as the material for the third insulation layer 203. For example, silicon nitride (Si ₃ N ₄ ) can be used for the second insulation layer 202 and silicon dioxide (SiO ₂ ) can be used for the third insulation layer 203.

For the final creation of the self-adjusting contacts 105 now becomes the third insulation layer at certain points 203 removed and thus the first conductor tracks 103 unearthed locally. These particular posts will be then with an electrically conductive material, for example tungsten, filled until the second Insulation layer 202, the remaining third Insulation layer 203 and the electrically conductive Material filled certain places a common Have surface 204 parallel to substrate surface 102. Those determined with electrically conductive material Positions now take over the function of self-adjusting Contacts 105.

Finally, they are located on the common surface 204 nor the metallic bit lines 106, which are used for coupling of electrical signals into the semiconductor structure 100 are necessary. Furthermore, the metallic Bit lines 106 a way to contact the integrated first conductor tracks 103 over several self-adjusting contacts 105.

As already mentioned above, it is used to reduce the Signal runtime according to the prior art parallel to the diffused bit lines each a metallic Bit line used. The metallic bit lines are in the Distance of four word lines using the self-adjusting Electrical contacts with the diffused bit lines connected. The contacts only adjust themselves perpendicular to the second conductor tracks.

With the described manufacturing process for the self-adjusting contacts is not an adjustment parallel to the second conductor tracks possible. It exists hence the risk of one contact being parallel to the second Printed conductor tracks is produced. Such a thing shifted contact can lead to an electrostatic Influencing the semiconductor substrate, causing it to an electrical short circuit between neighboring ones diffused bit lines can come. Such a Short circuit inevitably leads to failure of the direct adjacent transistors. Maybe all of them are Transistors of the bit lines involved from this disturbance affected. Thus, when manufacturing the etching mask during the manufacturing process of each individual contact the etching mask can be positioned very precisely and with great effort.

The invention is therefore based on the problem of a Semiconductor structure and a method for electrical Specify contacting at which the signal transit times in the semiconductor structure can be further reduced and a safer contacting is guaranteed.

The problem is compounded by a semiconductor structure as well Process for electrical contacting with the features solved according to the independent claims.

A semiconductor structure essentially has several parallel first conductor tracks, which in a semiconductor substrate are provided. Furthermore points the semiconductor structure several substantially in parallel mutually extending second conductor tracks, which are located on the semiconductor substrate, the first Traces are insulated and together with the first Conductor tracks form a grid. In addition, the Semiconductor structure on several third conductor tracks, which in Arranged essentially parallel above the first conductor tracks partially cover and close the second conductor tracks the second conductor tracks are insulated. Finally is between two adjacent second conductor tracks electrical contact between every first conductor track and the provided respective third conductor track above.

In a process for electrical contacting of several essentially parallel to each other first conductor tracks, which are in a semiconductor substrate are provided, several are essentially parallel mutually extending second conductor tracks on the Semiconductor substrate applied that the second conductor tracks form a grid together with the first conductor tracks and that the second traces to the first traces be isolated. Furthermore, several thirds Traces essentially parallel across the first Conductor tracks and partly over the second conductor tracks applied, being between the third conductor tracks and the second conductor tracks produces electrical insulation becomes. In addition, between two neighboring an electrical contact to the second conductor tracks electrical contacting of the first interconnects between every first conductor track and the respective one above it third trace generated.

An advantage of the invention can be seen in the fact that Problem of long signal propagation times in the semiconductor structure is reduced by appropriate contacting of the first conductor tracks, each of which is essentially parallel third conductor track arranged above by means of one each Contact between two neighboring second Conductor tracks is ensured. The can for the respective first conductor track provided by means of contacts a single continuous etching mask, which essentially is aligned parallel to the first conductor track become.

Another advantage of the invention is that due to the Multitude of contacts the contacts perpendicular to the first Conductors narrower than the contacts of the state of the Technology can be made and still no increase the signal runtime takes place. Because of the narrower contacts in the semiconductor structure according to the invention itself lack of precision in the position of the etching mask successful establishment of contacts possible. Besides, can with suitable structuring of the contact part of the Manufacturing process can be saved, from which a significant reduction in process costs results.

The contacting of the first interconnects between each two adjacent second conductor tracks also has the Advantage that all places on every first trace be contacted in the same way and in all places the same electrical of every first conductor track Properties are present. Thus, every first trace instructs all digits have the same signal runtime.

In the semiconductor structure according to the invention, preferred the first conductor tracks each have a first width and the electrical contacts each have a second width. The Both widths are parallel to the first conductor tracks and perpendicular to the longitudinal direction of the first conductor tracks aligned. The second width is preferably smaller than the first width.

In the semiconductor structure according to the invention, each of two adjacent first conductor tracks and one above lying second conductor track preferably a transistor educated. The semiconductor structure according to the invention provides thus preferably represents a transistor arrangement.

Furthermore, the semiconductor structure according to the invention has preferably under the second conductor between adjacent ones an oxide-nitride-oxide layer sequence on the first conductor tracks the semiconductor substrate.

In a preferred embodiment of the invention Semiconductor structure is the transistor, which each of two adjacent first conductor tracks and one above lying second conductor track is formed, a 2-bit memory transistor. Thus, the transistor arrangement as Memory cell arrangement can be used.

Preferably, the electrical contacts bridge the semiconductor structure according to the invention the second conductor tracks isolated. Furthermore, the invention Semiconductor structure preferably formed such that electrical contacts, which over a single one of the first Conductors are adjacent, overlap and thus even the form third conductor tracks. This creates a continuous, continuous series of contacts. On a independent metallization level, in which the third Conductor tracks are arranged, can be omitted. This not only reduces the number of layers required on the semiconductor substrate but also the material costs for the semiconductor structure according to the invention.

In a preferred development of the invention The first conductor tracks are each method with a first width and the electrical contacts each with a second width. The two widths have one Alignment parallel to the first conductor tracks as well perpendicular to the longitudinal direction of the first conductor tracks. The second width is preferably smaller than the first Width.

The second conductor tracks are preferably such over the first conductor tracks that creates two adjacent first conductor tracks and a second one above Conductor form a transistor. From the first Conductor tracks and the second conductor tracks is thus preferably generates a transistor arrangement.

Preferably, before generating the second conductor tracks an oxide-nitride-oxide layer sequence between adjacent first conductor tracks generated on the semiconductor substrate.

In a preferred development of the invention Process is the transistor, each of two adjacent first conductor tracks and one above second conductor track is formed, such that it is produced as 2-bit memory transistor can be used.

The electrical contacts are preferably such trained that these bridge the second conductor tracks and that there are electrical contacts, which over a individual ones of the first conductor tracks are adjacent, overlap and thus form the third conductor tracks themselves. So can on the elaborate production of an independent Metallization level in which the third conductor tracks are arranged to be dispensed with. This diminishes on the one hand the number of required process steps in the Manufacturing process and, on the other hand, the process costs.

Embodiments of the invention are in the figures shown and are explained in more detail below. there the same reference numerals designate the same components.

Figur 1

eine Draufsicht auf eine Halbleiterstruktur gemäß dem Stand der Technik;

Figur 2

einen Ausschnitt eines Querschnitts durch die Halbleiterstruktur aus Fig.1 entlang der Schnittlinie A-A;

Figur 3

eine Draufsicht auf eine Halbleiterstruktur gemäß einem ersten Ausführungsbeispiel der Erfindung;

Figur 4

einen Ausschnitt eines Querschnitts durch die Halbleiterstruktur aus Fig.3 entlang der Schnittlinie B-B;

Figur 5

eine Draufsicht auf eine Halbleiterstruktur gemäß einem zweiten Ausführungsbeispiel der Erfindung; und

Figur 6

einen Ausschnitt eines Querschnitts durch die Halbleiterstruktur aus Fig.5 entlang der Schnittlinie C-C.

Show it

Figure 1

a plan view of a semiconductor structure according to the prior art;

Figure 2

a section of a cross section through the semiconductor structure of Figure 1 along the section line AA;

Figure 3

a plan view of a semiconductor structure according to a first embodiment of the invention;

Figure 4

a section of a cross section through the semiconductor structure of Figure 3 along the section line BB;

Figure 5

a plan view of a semiconductor structure according to a second embodiment of the invention; and

Figure 6

a section of a cross section through the semiconductor structure of Figure 5 along the section line CC.

3 shows a top view of a semiconductor structure 300 according to a first exemplary embodiment of the invention.

In the first embodiment of the invention is in one Semiconductor substrate 301 on a substrate surface 302 a Group of first conductor tracks 303 integrated. The first Conductor tracks 303 are essentially parallel to one another arranged and close with the substrate surface 302 in Essentially flush. Usually the first Conductor tracks 303 by means of electrical diffusion conductive ions are produced in the semiconductor substrate 301.

The first conductor tracks 303 can be, for example, as buried bitlines can be provided.

Furthermore, is located on the substrate surface 302 of the Semiconductor substrate 301 a group of second conductor tracks 304, which on the substrate surface 302 to each other Substantially parallel and to the first conductor tracks 303 are arranged electrically insulated. The second conductor tracks 304 form together with the first conductor tracks 303 Basically a regular grid. Usually the second conductor tracks 304 using common methods for Production of metallization levels generated.

Two adjacent first conductor tracks 303 and one each Second conductor track 304 lying above form one Transistor. The first two conductor tracks 303 take over in Transistor area the function of the two transistor electrodes "Source" and "Drain", which is why the first conductor tracks 303 as Bit lines are called. The second trace 304 takes over the function of Transistor electrode "gate", which is why the second conductor tracks 304 are referred to as word lines.

An oxide-nitride-oxide layer sequence (not shown) made of silicon dioxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) is located on the substrate surface 302 in each transistor region between the first conductor tracks 303 and below every second conductor track 304, wherein in the silicon nitride layer can be stored up to two bits.

The first conductor tracks 303 are self-adjusting Contacts 305 to metallic contact lines 306 connected, which in turn with metallic Bit lines 307 are coupled. The metallic Contact lines 306 and metallic bit lines 307 run essentially parallel to the first Interconnects 303, bridge the second interconnects 304 and are electrically isolated from the second conductor tracks 304. The metallic contact lines 306 have the task of self-adjusting contacts 305 with the metallic To connect bit lines 307 electrically.

The first conductor tracks 303 have a conductor track width 308 and the self-adjusting contacts 305 a contact width 309 on. Because the contact width 309 is narrower than that Trace width 308, can meet the requirements of the Precision of the contact position in the manufacture of the self-adjusting contacts 305 compared to the state of the Technology can be reduced. This will save the effort during the production of the semiconductor structure 300 according to the invention significantly reduced.

Between each two adjacent second conductor tracks 304 there is always a self-adjusting contact 305 between the respective first conductor track 303 and the one above it lying metallic contact line 306. According to this Embodiment exist the self-adjusting contacts 305 and the metallic contact lines 306 made of tungsten and are in a common metallization process manufactured. This is done in places of the emerging Semiconductor structure 300 on which no self-aligning Contacts 305 and no metallic contact lines 306 a protective layer may be applied. The in the Protective layer remaining openings are then to Formation of self-adjusting contacts 305 and metallic contact lines 306 filled with metal. Finally the protective layer is removed.

In Figure 4 a detail is shown of a cross section through the semiconductor structure 300 of Figure 3 taken along section line BB.

Above the substrate surface 302 and thus above that in the Semiconductor substrate 301 integrated first conductor tracks 303 there is a first insulation layer 401. The first Insulation layer 401 is for electrical insulation between the second conductor tracks 304 and the first Conductor tracks 303 are provided. Furthermore, the second are Conductor tracks 304 from a second insulation layer 402 encapsulated to provide electrical insulation to the second Traces 304 to the self-adjusting contacts 305 and to ensure the metallic contact lines 306.

In order to encapsulate the second conductor tracks 304, an insulation material is first deposited flat over the second conductor tracks 304. An etching mask is subsequently applied over the second conductor tracks 304, which covers the second conductor tracks 304 and a region near the conductor track between adjacent second conductor tracks 304. The insulation material is now removed at exposed locations, which are not covered by the etching mask, up to the substrate surface 302. The etching mask is then removed again. In this exemplary embodiment of the invention, silicon nitride (Si ₃ N ₄ ) is used for the second insulation layer 402.

The exposed openings between the second conductor tracks 304 are then filled with an insulation material which can be selectively etched to the insulation material of the second insulation layer 402. In this exemplary embodiment of the invention, silicon dioxide (SiO ₂ ) is used as the insulation material between the second conductor tracks 304.

In order to produce the self-adjusting contacts 305, the silicon dioxide (SiO ₂ ) is now removed by means of an etching mask in narrow but long areas, which are aligned essentially parallel to the first conductor tracks 303, above the respective first conductor tracks 303. Both the etching mask and the openings that are created have the desired contact width 309. The first conductor tracks 303 are thus locally exposed again. The exposed first conductor tracks 303 are then covered with an electrically conductive material, in accordance with this exemplary embodiment with tungsten, until the electrically conductive material forms a common surface 403 with the second insulation layer 402 substantially parallel to the substrate surface 302.

Now the openings of the etching mask are over the common one Surface 403 also with the electrically conductive Material stuffed, causing the metallic contact lines 306 are formed. The etching mask can then be used again be removed.

Finally are on the metallic Contact lines 306 still the metallic bit lines 307, which are used to couple electrical signals into the Semiconductor structure 300 are necessary.

5 shows a top view of a semiconductor structure 500 according to a second exemplary embodiment of the invention.

The second embodiment of the invention differs different from the first embodiment of the invention only in that the metallic contact lines 306 and the metallic bit lines 307 to metallic Contact and bit lines 501 can be combined.

This can be achieved, for example, as follows: First, the self-adjusting Contacts 305 necessary etching mask on the emerging Semiconductor structure 500 with a greater thickness than according to the generated first embodiment of the invention. Will now after generating the self-adjusting contacts 305 the remaining openings of the etching mask completely with the filled electrically conductive material and the etching mask then removed, metallic contact lines are formed 306, which at the same time serve as metallic bit lines 307 can be used. Hence result Combined metallic contact and bit lines 501.

Due to the saving of the last metallization level, in which is the stand-alone metallic bit lines 307 there could have been a significant reduction according to the manufacturing cost of the semiconductor structure 500 achieved the second embodiment of the invention become. This can reduce the total manufacturing costs by up to be reduced to 10%.

FIG. 6 shows a section of a cross section through the semiconductor structure 500 from FIG. 5 along the section line CC.

This illustration clearly shows the existence of combined metallic contact and bit lines 501. For for further details, reference is made to the description of FIG. 4.

LIST OF REFERENCE NUMBERS

100

State of the art semiconductor structure

101

Semiconductor substrate

102

substrate surface

103

first trace

104

second conductor track

105

self-adjusting contact

106

metallic bit line

201

first insulation layer

202

second insulation layer

203

third insulation layer

204

common surface

300

Semiconductor structure according to the first exemplary embodiment of the invention

301

Semiconductor substrate

302

substrate surface

303

first trace

304

second conductor track

305

self-adjusting contact

306

metallic contact line

307

metallic bit line

308

Track width

309

contact width

401

first insulation layer

402

second insulation layer

403

common surface

500

Semiconductor structure according to the second exemplary embodiment the invention

501

metallic contact and bit line

Claims (12)

Semiconductor structure with a plurality of first conductor tracks which run essentially parallel to one another and which are provided in a semiconductor substrate, with a plurality of second conductor tracks running essentially parallel to one another, which are located on the semiconductor substrate, which are insulated from the first conductor tracks and which form a grid together with the first conductor tracks, and with a plurality of third conductor tracks which are arranged essentially in parallel above the first conductor tracks, which partially cover the second conductor tracks and which are insulated from the second conductor tracks, wherein an electrical contact is provided between each two adjacent second conductor tracks between each first conductor track and the respective third conductor track above it. Semiconductor structure according to claim 1,
in which the first conductor tracks each have a first width and the electrical contacts each have a second width, the two widths being aligned parallel to the first conductor tracks and perpendicular to the longitudinal direction of the first conductor tracks and wherein the second width is smaller than the first width. Semiconductor structure according to claim 1 or 2,
in which a transistor is formed in each case by two adjacent first conductor tracks and an overlying second conductor track. Semiconductor structure according to one of Claims 1 to 3,
in which an oxide-nitride-oxide layer sequence is provided on the semiconductor substrate under the second conductor track between adjacent first conductor tracks. Semiconductor structure according to one of Claims 1 to 4,
where the transistor is a 2-bit memory transistor. Semiconductor structure according to one of Claims 1 to 5,
in which the electrical contacts bridge the second conductor tracks in an isolated manner and are designed such that electrical contacts which are adjacent over a single one of the first conductor tracks overlap and thus themselves form the third conductor tracks. Method for the electrical contacting of a plurality of essentially mutually parallel first conductor tracks which are provided in a semiconductor substrate, in which a plurality of second conductor tracks running essentially parallel to one another are applied to the semiconductor substrate such that the second conductor tracks form a grid together with the first conductor tracks and that the second conductor tracks are insulated from the first conductor tracks, in which a plurality of third conductor tracks are applied essentially in parallel over the first conductor tracks and partially over the second conductor tracks, electrical insulation being generated between the third conductor tracks and the second conductor tracks, and in which an electrical contact for electrically contacting the first conductor tracks between each first conductor track and the respective third conductor track lying above it is produced between two adjacent second conductor tracks. Method according to claim 7,
in which the first conductor tracks are each produced with a first width and the electrical contacts are each produced with a second width, the two widths being aligned parallel to the first conductor tracks and perpendicular to the longitudinal direction of the first conductor tracks, and wherein the second width is smaller than the first width is. Method according to claim 7 or 8,
in which the second conductor tracks are generated above the first conductor tracks in such a way that two adjacent first conductor tracks and a second conductor track above them form a transistor. Method according to one of claims 7 to 9,
in which an oxide-nitride-oxide layer sequence is generated on the semiconductor substrate between the generation of the second conductor tracks between adjacent first conductor tracks. A method according to claim 9 or 10,
in which the transistor is produced in such a way that it can be used as a 2-bit memory transistor. Method according to one of claims 7 to 11,
in which the electrical contacts are designed such that they bridge the second conductor tracks and that electrical contacts which are adjacent over a single one of the first conductor tracks overlap and thus form the third conductor tracks themselves.

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