[go: up one dir, main page]

EP1252554A1 - Nonlinear image distortion correction in printed circuit board manufacturing - Google Patents

Nonlinear image distortion correction in printed circuit board manufacturing

Info

Publication number
EP1252554A1
EP1252554A1 EP00969787A EP00969787A EP1252554A1 EP 1252554 A1 EP1252554 A1 EP 1252554A1 EP 00969787 A EP00969787 A EP 00969787A EP 00969787 A EP00969787 A EP 00969787A EP 1252554 A1 EP1252554 A1 EP 1252554A1
Authority
EP
European Patent Office
Prior art keywords
layer
pattern
image data
conductive material
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00969787A
Other languages
German (de)
English (en)
French (fr)
Inventor
Itzhak Taff
Yossef Atiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kodak IL Ltd
Original Assignee
Kodak IL Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kodak IL Ltd filed Critical Kodak IL Ltd
Priority claimed from PCT/IL2000/000667 external-priority patent/WO2002033492A1/en
Publication of EP1252554A1 publication Critical patent/EP1252554A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits

Definitions

  • Post-etch punching of inner layers offered the following advantages as compared to pre-exposure methods:
  • the tooling pattern is punched in the inner layer after etching. All material movement resulting from artwork instability, etching, black oxidizing, etc. is compensated for by offset and global scale.
  • linear scaling error may be characterized by a single correction factor per axis for a given type of layer
  • non-linear scaling errors require a more complex correction scheme.
  • second order non-linearity which requires two correction factors through higher degrees of non-linearity, which require a number of correction factors equal to the degree of non-linearity to the most complex case where the required correction factor is as complex as the image file itself.
  • An actual conductor pattern (produced from an initial map or stored image data, and produced by a defined process on defined apparatus) on at least one inner layer (artificially termed "a first inner layer,” even though it does not have to be the first layer) is scanned by an image scanner to produce a scanned map or scanned image data.
  • the information from the scanned image of the first inner layer includes either the entire pattern of the conductor pattern, substantially all areas of the conductor pattern which contain conductor sites, or a segmented (discontinuous) pattern identifying the location of all conductor sites in the first inner layer, or a preselected portion of conductor sites.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Image Processing (AREA)
EP00969787A 2000-10-19 2000-10-19 Nonlinear image distortion correction in printed circuit board manufacturing Withdrawn EP1252554A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IL2000/000667 WO2002033492A1 (en) 1999-07-06 2000-10-19 Nonlinear image distortion correction in printed circuit board manufacturing

Publications (1)

Publication Number Publication Date
EP1252554A1 true EP1252554A1 (en) 2002-10-30

Family

ID=11043004

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00969787A Withdrawn EP1252554A1 (en) 2000-10-19 2000-10-19 Nonlinear image distortion correction in printed circuit board manufacturing

Country Status (5)

Country Link
EP (1) EP1252554A1 (zh)
JP (1) JP4791681B2 (zh)
KR (1) KR20020074163A (zh)
CN (1) CN1434932A (zh)
AU (1) AU2000279433A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108901119A (zh) * 2018-06-22 2018-11-27 广州兴森快捷电路科技有限公司 用于测量激光钻机孔位精度的治具及方法
CN116362957A (zh) * 2021-12-27 2023-06-30 广州镭晨智能装备科技有限公司 Pcb板卡图像对齐的方法、装置、介质和电子设备
CN117141037A (zh) * 2023-10-30 2023-12-01 山西昌鸿电力器材有限公司 一种电力金具加工工艺

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100526035B1 (ko) * 2003-05-07 2005-11-08 홍성국 메탈 마스크 검사 장치 및 그의 검사 방법
EP1804278A4 (en) * 2004-09-14 2011-03-02 Nikon Corp CORRECTION METHOD AND EXPOSURE DEVICE
US7368207B2 (en) * 2006-03-31 2008-05-06 Eastman Kodak Company Dynamic compensation system for maskless lithography
EP2539773B1 (en) * 2010-02-26 2014-04-16 Micronic Mydata AB Method and apparatus for performing pattern alignment
CN111694226B (zh) * 2020-05-25 2022-05-17 合肥芯碁微电子装备股份有限公司 水平度测量方法和直接式成像设备
KR102385554B1 (ko) * 2020-06-16 2022-04-13 재단법인 아산사회복지재단 나노구조체 기반의 표면증강라만 기판 및 그 제조 방법
CN114485409A (zh) * 2022-04-18 2022-05-13 深圳市元硕自动化科技有限公司 原料板质量检测方法、装置、设备及可读存储介质
CN119967731B (zh) * 2025-04-10 2025-07-15 惠州威尔高电子有限公司 基于防偏定位的厚铜电源板压合控制方法及系统

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3291176B2 (ja) * 1995-05-15 2002-06-10 松下電工株式会社 回路パターンの検査方法および検査装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0233492A1 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108901119A (zh) * 2018-06-22 2018-11-27 广州兴森快捷电路科技有限公司 用于测量激光钻机孔位精度的治具及方法
CN116362957A (zh) * 2021-12-27 2023-06-30 广州镭晨智能装备科技有限公司 Pcb板卡图像对齐的方法、装置、介质和电子设备
CN116362957B (zh) * 2021-12-27 2024-05-14 广州镭晨智能装备科技有限公司 Pcb板卡图像对齐的方法、装置、介质和电子设备
CN117141037A (zh) * 2023-10-30 2023-12-01 山西昌鸿电力器材有限公司 一种电力金具加工工艺
CN117141037B (zh) * 2023-10-30 2024-02-02 山西昌鸿电力器材有限公司 一种电力金具加工工艺

Also Published As

Publication number Publication date
CN1434932A (zh) 2003-08-06
KR20020074163A (ko) 2002-09-28
JP4791681B2 (ja) 2011-10-12
JP2004512678A (ja) 2004-04-22
AU2000279433A1 (en) 2002-04-29

Similar Documents

Publication Publication Date Title
US6165658A (en) Nonlinear image distortion correction in printed circuit board manufacturing
US7283660B2 (en) Multi-layer printed circuit board fabrication system and method
EP2539773B1 (en) Method and apparatus for performing pattern alignment
CA2078930C (en) Register mark
KR101058160B1 (ko) 땜납 인쇄 검사 장치 및 부품 실장 시스템
US4536239A (en) Multi-layer circuit board inspection system
JPH0445043B2 (zh)
KR101480589B1 (ko) 묘화 데이터의 보정 장치 및 묘화 장치
KR100890133B1 (ko) 노광장치
JP2008016758A (ja) 多層回路基板製造におけるマーキング装置
EP1252554A1 (en) Nonlinear image distortion correction in printed circuit board manufacturing
US7058474B2 (en) Multi-layer printed circuit board fabrication system and method
US20040081351A1 (en) Multi-layer printed circuit board fabrication system and method
FI81690C (fi) Foerfarande av en jaemn foerdelningstaethet.
JP3711804B2 (ja) 回路板の製造方法及びマスクフィルム用取付孔穿設装置
CN119767579B (zh) Hdi线路板的加工对位方法及hdi线路板
JP2004252313A (ja) 露光装置
KR19980021238A (ko) 반도체장치의 마스크 정렬 방법
JPH1117292A (ja) プリント基板とこの基板に部品を実装する部品実装機
Patek et al. Rule-based inspection of printed green ceramic tape
TW202319841A (zh) 直接描繪裝置及其控制方法
JPS6080298A (ja) 混成集積回路の製造方法
JP2001007496A (ja) スクリーン印刷方法および装置
TW201208506A (en) Method for manufacturing printed circuit board

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20030513

RBV Designated contracting states (corrected)

Designated state(s): AT BE CH DE FR GB LI

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060501