EP1193742A2 - Method for fabricating integrated circuits, corresponding circuits, particularly tunnel contacts - Google Patents

Abstract

The invention relates, inter alia, to a method in which an electrically non-conductive mask layer (16) is applied to an electrically conductive contact layer carried by a substrate layer (12). A free space is introduced into the mask layer (16). Subsequently, several layers (52 to 60) are electrochemically deposited in the free space. Layers (72 and 76) are then applied above the last deposited layer (60). In a removal process, the mask layer (16) is then removed down to the level of the top layer (76). <IMAGE>

Description

The invention relates to a method in which an electrical conductive contact layer carried by a substrate layer e.g. from a silicon wafer. On the electric a conductive contact layer will not be an electrical one conductive mask layer applied, e.g. a photoresist. Then part of the mask layer is removed in order then at least one electrically conductive layer on the Apply the contact layer in the resulting free space.

• organische und anorganische Isolatoren κ = 10^-18 bis 10^-7 Ω^-1/m^-1,
• Halbleiter κ = 10^-7 bis 10^-4 Ω^-1/m^-1 und
• elektrisch leitfähige Schichten, insbesondere Metallschichten κ > 10⁴ Ω^-1/m^-1, insbesondere im Bereich κ = 10⁴ bis 10⁵ Ω^-1/m^-1.

For non-conductive layers, ie for insulator layers, for semiconductor layers and for electrically conductive layers, the following specific conductivities κ can be specified:

• organic and inorganic insulators κ = 10 ^-18 to 10 ^-7 Ω ^-1 / m ^-1 ,
• Semiconductors κ = 10 ^-7 to 10 ^-4 Ω ^-1 / m ^-1 and
• electrically conductive layers, in particular metal layers κ> 10 ⁴ Ω ^-1 / m ^-1 , in particular in the range κ = 10 ⁴ to 10 ⁵ Ω ^-1 / m ^-1 .

• Bedampfen,
• Aufstäuben (Sputtern), und
• elektrochemische Abscheidung.

Various methods are known for applying the electrically conductive layers in the production of integrated circuit arrangements, among others

• vapor deposition,
• Dusting (sputtering), and
• electrochemical deposition.

When steaming and dusting arise on the whole Silicon wafer layers, on the one hand, over the silicon wafer can be unevenly thick. On the other hand Layer sections within free spaces of the mask layer different thicknesses, especially near steps. These disadvantages are annoying for many applications. steaming and dusting is both more electrically conductive for application Layers as well as for the application of electrically non-conductive Layers possible.

With electrochemical coating processes, Deposit layers of very uniform layer thickness. It will distinguish between galvanic and external currentless deposition. With the galvanic metal deposition Electrons supplied from an external power source. A z-fold positively charged metal ion with the inclusion of z Electrons reduced, where z is a natural number greater than 0 is. With the electroless deposition of metals no external power source needed. The ones required for reduction Electrons come from a reducing agent, the is contained in an electrolytic solution. The electrochemical Deposition is only possible for electrically conductive layers.

It is an object of the invention to produce an integrated Circuit arrangement with electrically conductive and electrically non-conductive layers simple process specify. Associated integrated circuit arrangements are also intended and a tunnel contact element can be specified.

The task related to the procedure is performed by the Claim 1 specified process steps solved. Further developments are specified in the subclaims.

In the method according to the invention, in addition to initially mentioned process steps in the removal of space created by parts of the mask layer by means of electrochemical deposition at least one electrically conductive layer electrochemically deposited.

Electrochemical deposition is deposited on the electrical non-conductive mask layer no materials.

This eliminates steps with which such materials would have to be removed. By inserting an electrochemical Coating processes arise within the Clear layers with uniform thickness. The layers can also be very thin, e.g. less than 2 nm Thickness of the layers is both within a free space evenly as well as in different locations of a silicon wafer of, for example, 200 or 300 mm in diameter. The electrochemical coating is a very inexpensive Coating process compared to steaming or Sputtering. This allows the lower part of the layer system manufacture with comparatively little effort. At the Producing very thin layers increases the yield in the manufacture of integrated circuit arrangements significant because the thickness of the deposited layers is technological can be set comparatively precisely.

In the method according to the invention is also in the free space after electrochemical deposition an electrical introduced non-conductive layer. So that's an electrochemical Deposition of further layers is no longer possible. Another layer or more layers will be brought into the open space with other coating techniques. The further layer or the further layers can be electrically conductive, electrically non-conductive or be semiconducting. When applying the additional layer or the other layers arise outside of the free space Layers of the same materials. These layers are removed in a removal process.

The component to be manufactured is therefore already in front of the Removal in free space. Measures to limit the lateral applied layers, as in conventional coating processes are often required. Such Measures would result in material mixing on the side edges to lead. This mixing of materials would have been unfavorable Cases bridging the electrically non-conductive Layer through electrically conductive materials and thus a electrical short circuit. By the invention However, such a bridging is in process avoided. Therefore, components can be produced with a high yield produce.

In the method according to the invention, the last deposited is Layer in a preferably anodized Oxidation process completely or partially to an electrical non-conductive layer oxidized. By this measure it is achieved that the non-conductive layer from a conductive layer can be produced. During the oxidation the thickness of the layer changes only slightly and evenly. The non-conductive layer is thus uniform thick. Alternatively, the last layer deposited an electrically non-conductive layer is applied, e.g. by dusting or steaming. The alternative is for the applied non-conductive layer is uniform Foundation by depositing the previous layers generated. This also does not lead to a more uniform conductive layer. The non-conductive layer is in many applications that are critical in manufacturing Layer, e.g. the thinnest layer. By using the The inventive method can be the non-conductive layer can be applied with smaller tolerances. This increases the Yield in the manufacture of the integrated circuit arrangement Likewise.

Is galvanically deposited, that means with external current, so forms or form the electrically conductive contact layer the electrically conductive layers deposited thereover Anode. When using certain materials for the electrical conductive contact layer, e.g. for copper or highly doped Semiconductors, so-called diffusion barriers and / or adhesive layers are used, hereinafter as an intermediate layer designated. The intermediate layer is e.g. from TaN (Tantalum nitride). The intermediate layer can also act as an anode for the galvanic deposition can be used. Reaches the intermediate layer to the edge of the processed silicon wafer (Wafer), so external current can be drawn over the edges feed the silicon wafer in a simple manner. For electroplating direct current or alternating current can be used.

In a further development, the mask layer overlaps the electrically conductive layer on all sides. In continuing education are at least two electrically conductive layers deposited from different materials one after the other. The overlap on all sides ensures that only that first material to the electrically conductive contact layer arrives. The first layer is then of uniform thickness deposited. When the second layer is deposited no more material of this layer to the electrically conductive Contact layer. The second electrically conductive layer becomes more even over the previously applied layer Thickness deposited. Also have the edge areas of the layers compared to the rest of the layer the same thickness. A Curvature in the edge areas due to a different Layer thickness does not occur.

As already mentioned, the thickness of the mask layer is as follows dimensioned that the additional layer below the opening of the free space. With the help of a removal process in a further training in a later process step Areas outside the open space are removed, that were created when the additional layer was applied. These areas thus hinder the further production of the integrated circuit arrangement no longer. To remove becomes, for example, a mechanical-chemical polishing process (MCP) used. Part of the mask layer can also be removed erode. The rest of the mask layer remains the substrate layer and delimits the layer system within of space on all sides.

The next training is before the polishing process applied a sealing layer that does not yet filled space of the free space. During the polishing process the sealing layer is up to the level of the last applied layer removed. By sealing it achieved that no material in later process steps in the space between the other layers and the Mask layer arrives. Such material would make them electrical properties of the layer system changed become.

In an alternative development, the mask layer completely removed during the removal process, e.g. through a so-called lift-off procedure. This also means that Apply the additional layer outside the free space created layers removed and interfere with the others Procedural steps not.

In a further development of the alternative, the mask layer exists from an organic material. The mask layer is removed using a suitable solvent. All organic are suitable as material for the mask layer Materials used in semiconductor technology can be. The trend is towards organic materials with small dielectric values. Examples of such Materials are polyimides, optionally with fluorine are offset. In addition, so-called spin-on glasses used, i.e. Glasses made using the so-called spin process are applied to the substrate layer. Further Representatives are alkyl silanes, such as ultra-low-k materials e.g. Teflon, porous dielectrics, e.g. Ärogel, or too SiLK, a hydrocarbon compound that does not contain silicon contains.

In one embodiment, after the mask layer has been removed applied a capsule layer. The capsule layer to the level of the last layer applied removed, preferably in a mechanically chemical Polishing process. The capsule layer serves to encapsulate the Layer system, so that in the further process steps no substances destroy the layer system.

In another development, parts of the mask layer removed by anisotropic etching, for example, that the free space preferably faces the substrate layer on all sides broadened there. The emerging structure will also referred to as the reentrant structure. The slope of the walls of the Free space, i.e. for example, the overhang is more than 5 percent with respect to the normal of the substrate layer. used for example, inclination angles of 5 percent, 10 Percent or 20 percent. Due to the inclination, the mask layer works when applying the other layers as so-called Shadow mask. When dusting the other layers excessive flattening in the edge areas of the to be applied Avoid layer through the shadow mask. However, it can can also be worked without inclining the side walls.

With a next training course, the free space e.g. one trapezoidal cross-section. The side walls of the free space form along a cross section through the mask layer for example, straight lines. This facilitates the manufacture of the Free space considerably. However, open spaces are also used, which only in the area of the other layers to the substrate layer widen and then approximately the same diameter to have.

In another development, the mask layer has one flat surface and contains a variety of cutouts, in which similar components are arranged. The contact layers several components are interconnected, for example in the manner of a matrix in rows and Columns. This measure can be used during electroplating to the interconnected contact layers on simple Kind of feed a stream. This simplifies the Electroplating process even with a large number of components, e.g. several hundred thousand components on one integrated Circuitry. Several integrated circuit arrangements are on a silicon wafer with a diameter made of 200 mm, 300 mm or larger. With integrated Circuits can be the combination of electrochemical Use deposition and other coating techniques and is the previously used manufacturing method an integrated circuit arrangement in many ways think.

In a further development, the mask layer is thinner than 100 nm, preferably thinner than 50 nm. At least one in the Cavity layer is thinner than 5 nm. In particular at such layer thicknesses, the use of inventive method or its further developments Manufacture of much more homogeneous and uniform Layers than achieved with other methods. The above Layer thicknesses are used, for example, in the production of Tunnel contact elements required, i.e. for contact elements, the so-called tunnel effect of electrons through insulators exploit.

For this reason, at least one further training course is used electrically non-conductive introduced into the free space Layer with a thickness that is dimensioned that electrons the layer only because of the tunnel effect can cross.

In one embodiment, an electrically conductive Layer by electrochemical deposition in the free space brought in. Then this layer is preferred by anodic oxidation to an electrically non-conductive Layer oxidized. This technology can be used in particular for tunnel elements to achieve a high yield use in production. The sputtering of very thin ones Layering is problematic. The anodic oxidation has advantages over other oxidation processes with regard to the oxidation time and the uniformity of the Oxidation.

• für die Maskenschicht und/oder die Versiegelungsschicht ein Quarzglas oder ein organisches elektrisch nicht leitfähiges Material,
• für die zuletzt abgeschiedene Schicht z.B. Aluminium, und/oder
• für weitere im Freiraum abgeschiedene oder in den Freiraum aufgebrachte Schichten hartmagnetische Materialien und/oder Schichten aus weichmagnetischem Material.

The following materials will be used for the next training:

• for the mask layer and / or the sealing layer, quartz glass or an organic, electrically non-conductive material,
• for the last deposited layer, for example aluminum, and / or
• for further layers of hard magnetic materials and / or layers of soft magnetic material deposited in the free space or applied in the free space.

• Ferromagnete wie z.B. FeMn, NiMn, IrMn und PtMn,
• sogenannte Pseudospinvalves wie z.B. CrPdMn, oder
• künstliche Antiferromagnete wie z.B. Co/Cu/Co, Fe/Cr/Fe, CoFe/Ru/CoFe.

By using hard magnetic and soft magnetic layers, magnetic storage elements can be produced that take advantage of the tunnel effect. Such memories are known under the name "Magnetic Random Access Memories" (MRAM). Hard magnetic materials used are:

• Ferromagnets such as FeMn, NiMn, IrMn and PtMn,
• so-called pseudospinvalves such as CrPdMn, or
• artificial antiferromagnets such as Co / Cu / Co, Fe / Cr / Fe, CoFe / Ru / CoFe.

Common to these materials is that a magnetic field with a field strength of e.g. more than 100 Oersted needed is used to align the magnetization within the Change materials.

For example, a layer is used as the soft magnetic layer made of FeNi or CoPt. Combinations of the hard magnetic and / or soft magnetic layers be used.

The invention also relates to a circuit arrangement in the at least one layer of a layer system by electrochemical Deposition has been made. The mask layer is older than that by electrochemical deposition manufactured layer. The mask layer therefore has a double function. It serves as protection for encapsulating the layer system and forms a lateral boundary with the electrochemical Deposition. So the above technicals apply Effects also for the circuit arrangement.

In addition, the invention is a circuit arrangement affected, in which a capsule layer is a layer system includes at least one by electrochemical Deposition contains deposited layer. The capsule layer is younger than the deposited layer. The above technical effects also apply to the circuit arrangement, especially those related to the mask layer and their removal indicated effects.

The layer system contains in addition to that by electrochemical Deposition layer or in addition to the through electrochemical deposition of deposited layers a further development of the circuit arrangement with capsule layer at least one electrically non-conductive layer over which further layers are arranged.

In addition, in a further development of the circuit arrangement with capsule layer at least one layer of the layer system a larger footprint than one between this layer and the contact layer. The broadening of Layer areas towards the contact layer is on the inclined Sidewalls of an already removed mask layer. The technical effects mentioned above apply also for the circuit arrangement.

In further developments of the circuit arrangements Circuitry features that are also found in circuitry arise with the inventive method or with one of his advanced training are. For example, a sealing layer is used the side walls of the mask layer are inclined, the above materials are used and / or layer thicknesses mentioned above are used. The above The technical effects mentioned apply accordingly to the Training.

The invention further relates to a tunnel contact element, the at least two electrically conductive contact layers contains. There is an electrical one between the contact layers non-conductive barrier layer, the thickness of which is dimensioned in this way is that they are electrons only because of the tunnel effect can be crossed. The barrier layer and / or one Contact layer was made by electrochemical deposition manufactured. Through this measure, the relevant Layer with high accuracy and uniform thickness getting produced. The yield of the production of the tunnel elements is very high.

At a next training course, the barrier layer made by anodic oxidation. One of the electrically conductive contact layers as electrodes for galvanic deposition is used.

In a further development, the tunnel contact element has features that also occur with a circuit arrangement that according to the inventive method or one of its further developments has been manufactured. The above Features and technical effects also apply to the Tunnel junction element.

Figur 1

die Herstellung einer SiO₂-Struktur mit einer Überhang-Struktur (Reentrant), d.h. mit einer Verjüngung der Struktur noch oben hin,

Figur 2

die Abscheidung eines unteren Metallkontaktes eines Tunnelelementes sowie einer oxidierbaren Schicht, z.B. einer Aluminiumschicht,

Figur 3

die anodische Oxidation der Aluminiumschicht zur Herstellung einer Tunnelbarriere,

Figur 4

das Aufbringen eines oberen Metallkontaktes des Tunnelelementes,

Figur 5

das Auftragen einer Versiegelungsschicht z.B. aus SiO₂,

Figur 6

die Versiegelungsschicht nach einem Einebnungsprozess,

Figur 7

eine Struktur gemäß einem Ausführungsbeispiel mit organischen Materialien,

Figur 8

die Struktur nach dem Ablösen einer organischen Maskenschicht,

Figur 9

das Aufbringen einer Kapselschicht, und

Figur 10

die Struktur mit eingeebneter Kapselschicht.

Exemplary embodiments of the invention are explained below with reference to the accompanying drawings. In it show:

Figure 1

the production of an SiO ₂ structure with an overhang structure (reentrant), ie with a tapering of the structure towards the top,

Figure 2

the deposition of a lower metal contact of a tunnel element and an oxidizable layer, for example an aluminum layer,

Figure 3

the anodic oxidation of the aluminum layer to produce a tunnel barrier,

Figure 4

the application of an upper metal contact of the tunnel element,

Figure 5

the application of a sealing layer, for example made of SiO ₂ ,

Figure 6

the sealing layer after a leveling process,

Figure 7

a structure according to an embodiment with organic materials,

Figure 8

the structure after the removal of an organic mask layer,

Figure 9

the application of a capsule layer, and

Figure 10

the structure with leveled capsule layer.

Figure 1 shows the manufacture of a structure 10 with e.g. trapezoidal cross-section on a substrate layer 12 e.g. made of silicon dioxide. An interconnect contact is in the substrate layer 12 e.g. made of copper in a previous process step been embedded. This trajectory was, for example embedded with the so-called damascene technique. Located between substrate layer 12 and interconnect contact 14 an approximately 5nm (nanometer) thick barrier layer e.g. out Tantalum nitride. On the substrate layer 12 and the interconnect contact 14 a mask layer 16 e.g. made of silicon dioxide applied. The thickness D1 of the mask layer 16 is greater than the height of a tunnel contact element to be manufactured.

Then the mask layer 16 is removed using a dry etching process, e.g. a reactive ion etching process structured to e.g. the structure 10 with a trapezoidal shape Generate cross section. Such a structure is also called Denoted reentrant structure. A occurs during the etching process Free space 18, the side walls 20 and 22 with respect to the Normals n of the substrate layer 12 or of the interconnect contact 14 by an angle α> 3 °, e.g. about 15 °. Along the cross section shown in Figure 1, the Opening of the free space 18 a width B1 of, for example 180 nm. The free space 18 widens for contact with the interconnect 14 out and has a width B2 at the interconnect contact 14 is larger than the width B1, e.g. 200 nm. In the edge areas of the interconnect contact 14 remains the mask layer 16 stand and overlaps the interconnect contact 14 by an overlap distance S of for example 20 nm. The etching is ends when the surface of the interconnect contact 14 reaches becomes. The opening of the free space 18 and its base are, for example, square, rectangular or oval.

FIG. 2 shows the deposition of a lower contact stack 50 of the tunnel element to be manufactured. The separation takes place electrochemically using external current, i.e. galvanically. This creates a positive potential on the barrier layer 24 created up to the edge areas of the silicon wafer is sufficient, on which the structure 10 is located. The mask layer 16 has a high resistance and thus acts as electrical insulator. The interconnect contact 14 conducts very well and therefore acts as an anode during the deposition. On the A metal layer 52 is initially mounted on the interconnect contact 14 from copper in uniform thickness.

Then in a second deposition process e.g. a permaloy layer 54 on the copper layer 52 galvanically deposited. On the permaloy layer 54 is in a next Deposition process, for example a cobalt-iron layer 56 galvanically separated. Also the cobalt-iron layer 56 has an even thickness. The thicknesses of the copper layer 52, the permaleus layer 54 and the cobalt-iron layer 56 in this order, for example, 3 nm, 4 nm and 1 nm.

In a next step, the cobalt-iron layer 56 galvanically with an aluminum layer 58 a uniform thickness of e.g. 1.5 nm deposited.

FIG. 3 shows the anodic oxidation of the aluminum layer 58 into an aluminum oxide layer 60. The one arriving at the anode Oxygen oxidizes aluminum layer 58 evenly Alumina layer 60. Has at the end of the oxidation process the aluminum oxide layer 60 has a thickness of e.g. 2 nm. The Aluminum oxide layer 60 forms the tunnel barrier of the one to be manufactured Tunnel junction element.

In another embodiment, the aluminum layer 58 not completely oxidized, but only partially. There remain e.g. get one to three atomic layers of the aluminum layer 58.

FIG. 4 shows the application of an upper metal stack 70 of the tunnel element to be manufactured. In a first process step e.g. in a sputtering process, is applied to the aluminum oxide layer 60 a e.g. about 2 nm thick cobalt-iron layer 72 applied. In addition, at the edge of the cobalt-iron layer 72 a space Z1 between this layer and the mask layer 16 is formed. It also turns on the mask layer 16 a cobalt-iron layer 74 is applied.

In a next process step, the cobalt-iron layer 72 e.g. an iron-manganese layer 76 is applied. The area occupied by the iron-manganese layer 76 also smaller than that of the cobalt-iron layer 72 occupied area. Between iron-manganese layer 76 and the A layer Z2 is created in the mask layer 16. Moreover an iron-manganese layer 78 is deposited on the application the cobalt-iron layer 74.

In the exemplary embodiment, a diffusion barrier is then also created made of tantalum nitride, e.g. a To prevent diffusion of copper to be applied later. This barrier layer is not shown in FIG. 4.

FIG. 5 shows the application of a sealing layer 90 e.g. made of silicon dioxide on the structure 10. The thickness of the Sealing layer 90 is chosen so that in a subsequent one Polishing process polishing on the iron-manganese layer 76 or on the barrier layer applied thereon can be stopped. A cavity 92 lies above the Level at which the polishing process is stopped and is therefore no longer disturbing. The sealing layer 90 penetrates up to the aluminum oxide layer 60 in the remaining ones Free space and fill the remaining spaces and gaps with silicon dioxide. This will make the cobalt-iron layer 72 and the iron-manganese layer 76 completely capsuled. The sealing layer also settles above the iron-manganese layer 78.

FIG. 6 shows the leveled sealing layer 90. Leveled with the help of a mechanical-chemical polishing process. The polishing process is carried out on the surface of the iron-manganese layer 76 or on the surface of the applied Barrier layer ended. During the polishing process the cobalt-iron layer applied to the mask layer 16 74 and the overlying iron-manganese layer 78 away. The structure 10 only contains after the polishing process still parts of the sealing layer 90, the side of the Cobalt-iron layer 72 and the iron-manganese layer 76 lie. After the polishing process, the manufacture of the upper interconnect contact. By on hand The manufacturing process explained in FIGS. 1 to 6 arises a tunnel contact element 100, the layers of which are uniform Have thickness. In particular, the aluminum oxide layer 60 not from materials of the overlying cobalt-iron layer 72 or the iron-manganese layer 76 is electrically short-circuited.

The barrier layer 24 can be used in further process steps from the surface of the structure 10 again cut. This leaves around the tunnel contact element 100 around side walls made of the material of the mask layer 16 stand.

In another exemplary embodiment, the substrate layer 12 is produced, for example, from an organic and electrically non-conductive material. In this case, the organic substrate layer is closed off by an additional hard mask layer 110, which consists, for example, of SiON, SiO ₂ or Si ₃ N ₄ . The boundary between the mask layer 110 and the organic substrate layer is shown in FIGS. 1 to 6 by dashed lines 112. Otherwise, the process steps and materials explained with reference to FIGS. 1 to 6 remain the same.

• eine Kupferschicht 52b,
• eine Permaloyschicht 54b,
• eine Kobalt-Eisen-Schicht 56b,
• einen die Schichten 52b, 54b und 56b enthaltenden Kontaktstapel 50b,
• eine Aluminiumoxidschicht 60b,
• eine darauf aufgebrachte Kobalt-Eisen-Schicht 72b,
• eine Eisen-Mangan-Schicht 76b,
• einen die Schichten 72b und 76b enthaltenden Metallstapel 70b,
• eine auf der Maskenschicht 122 aufgebrachte Kobalt-Eisen-Schicht 74b, und
• eine darüberliegende Eisen-Mangan-Schicht 78b.

FIG. 7 shows a structure 10b according to an exemplary embodiment in which a substrate layer 120, for example made of an organic material, is used instead of the substrate layer 12. For example, a hard mask layer 110b is located above the substrate layer 120. A barrier layer 24b between substrate layer 120 and interconnect contact 14b is also used in the exemplary embodiment shown in FIG. 7 in order to avoid the diffusion of the copper of the interconnect contact 14b into the substrate layer 120. A mask layer 122 made of an organic material was applied to the barrier layer 24b and the interconnect contact 14b. Otherwise, the same method steps were carried out for the production of the structure 10b, which were explained above with reference to FIGS. 1 to 6 for the production of the structure 10. Layers of the same material, with the same dimensions and the same function therefore have the same reference number in FIG. 7, but with the lower-case letter b. This applies to the following layers:

• a copper layer 52b,
• a permaloy layer 54b,
• a cobalt-iron layer 56b,
• a contact stack 50b containing layers 52b, 54b and 56b,
• an aluminum oxide layer 60b,
• a cobalt-iron layer 72b applied thereon,
• an iron-manganese layer 76b,
• a metal stack 70b containing layers 72b and 76b,
• a cobalt-iron layer 74b deposited on the mask layer 122, and
• an overlying iron-manganese layer 78b.

Sidewalls 20b and 22b correspond to sidewalls 20 and 22, i.e. sidewalls 20b and 22b are in structure 10b e.g. with respect to the interconnect contact 14b on the same Position and with the same inclination as that Sidewalls 20 and 22 in structure 10 with respect to interconnect contact 14. A free space 18b corresponds to the free space 18th

After the process steps for producing the in FIG Structure 10b is shown in a subsequent process step the mask layer 122 detached. Spaces 124 and 126 between the cobalt-iron layer 72b and the mask layer 122 and between the iron-manganese layer 76b and the mask layer 122 facilitate the penetration of a solvent and thus the detachment and dissolution of the mask layer 122. Together with the mask layer 122, too the layers 74b and 78b lying on the mask layer 122 replaced.

FIG. 8 shows the structure 10b after the detachment process. This Process is also called a lift-off process. Through the Combination of two coating processes, namely the electrochemical Deposition and sputtering, the application of the anodic oxidation to produce the tunnel barrier 60b as well as the application of the lift-off process become electrical Short circuits across the aluminum oxide layer 60b avoided. After the mask layer 122 has been removed, the barrier layer lies 24b free again above the hard mask layer 24b. The side surfaces of the tunnel contact element 100b are also exposed when detached.

FIG. 9 shows a capsule layer applied to the structure 10b 150 e.g. from an organic material. The capsule layer 150 is applied in a thickness greater than is the height of the tunnel contact element 100b. Above the tunnel element 100b an elevation 152 forms. The capsule layer 150 is leveled in a subsequent process step, for example by a mechanical-chemical Polishing process.

FIG. 10 shows the structure 10b at the end of the polishing process. The polishing process was on the top surface of the iron-manganese layer 76b stopped. This is the manufacture of the Tunnel contact element 100b essentially ended. In further process steps are e.g. an upper interconnect contact and other components applied (not shown).

As a stop layer for the polishing process to level the Capsule layer 150 can also be removed before the Insert mask layer 122 sputtered diffusion barrier.

In another embodiment, the substrate layer 120 an inorganic material is used, e.g. Silica. In this case there is no hard mask layer 110b needed. The mask layer 122 exists in the exemplary embodiment from an organic material. The capsule layer is made of an organic material.

In a next embodiment, the capsule layer 150 made of an inorganic material, e.g. made of silicon dioxide. An organic layer is again used for the mask layer 122 Material used. The capsule layer is made of one inorganic material.

LIST OF REFERENCE NUMBERS

10, 10b

structure

12

substrate layer

14, 14b

Leitbahnkontakt

16

mask layer

D1

thickness

18, 18b

free space

20, 20b, 22, 22b

Side wall

n

normal

α

angle

B1, B2

width

S

overlap distance

24, 24b

barrier layer

50, 50b

lower contact stack

52, 52b

copper layer

54, 54b

Permaloyschicht

56, 56b

Cobalt-iron layer

58

aluminum layer

60, 60b

aluminum oxide layer

D2

thickness

70, 70b

metal stack

72, 72b, 74, 74b

Cobalt-iron layer

76, 76b, 78, 78b

Iron manganese layer

90

sealing layer

92

cavity

100, 100b

Tunnel junction element

110, 110b

mask layer

112, 112b

border

120

organic substrate layer

122

organic mask layer

124, 126

gap

150

capsule layer

152

survey

Z1, Z2

gap

Claims (21)

Method for producing an integrated circuit arrangement, in which an electrically non-conductive mask layer (16; 122) is applied to an electrically conductive contact layer (14; 14b) carried by a substrate layer (12; 120), the mask layer (16; 122) is removed from a partial area of the electrically conductive contact layer (14; 14b), and in which at least one electrically conductive layer (52 to 56; 52b to 56b) is deposited in the resulting free space (18; 18b) by means of electrochemical deposition, the last deposited layer being completely or partially converted into an electrically non-conductive layer (60; 60b) in an oxidation process, or an electrically non-conductive layer is applied to the last deposited layer, wherein at least one further layer (72, 76; 72b, 76b) is applied to the electrically non-conductive layer (60; 60b), the further layer (72, 76; 72b, 76b) lying in the free space (18; 18b), and wherein at least one layer (74, 78; 74b, 78b) formed outside of the free space (18; 18b) when the further layer (72, 76; 72b, 76b) is applied is removed in a removal process. Method according to claim 1,
characterized, that the mask layer (16) overlaps the electrically conductive contact layer (14, 24) on all sides and that successively electrically conductive layers (52 to 56) made of different materials are deposited. The method of claim 1 or 2,
characterized in that during the removal process the mask layer remains at the level of the deposited layers and the applied layers. Method according to claim 3,
characterized, that a sealing layer (90) applied prior to the ablation process, which occupies the not-filled space of the free space (18), and that the sealing layer (90) is removed to the level of the uppermost layer (76) applied during the removal process. The method of claim 1 or 2,
characterized in that the mask layer (122) is also removed during the removal process. Method according to claim 5,
characterized, that the mask layer (122) consists of an organic material, and that the mask layer (122) is removed with the aid of a preferably organic solvent. A method according to claim 5 or 6,
characterized, that after the mask layer (122) has been removed, a capsule layer (150) is applied, and that the capsule layer (150) is removed to the level of the last applied layer (76b), preferably with a mechanical-chemical polishing process. Method according to one of the preceding claims,
characterized in that part of the mask layer (16) is preferably removed by anisotropic etching in such a way that the free space (18) widens preferably on all sides towards the substrate layer (12). A method according to claim 8,
characterized in that the free space (18) has a trapezoidal cross section. Method according to one of the preceding claims,
characterized, that a plurality of free spaces (18) with similar components (100) are arranged in the mask layer (18), and that the contact layers (14) of a plurality of components (1009) are connected to one another. Method according to one of the preceding claims,
characterized, that the mask layer (16) is thinner than 100 nm, preferably thinner than 50 nm, and / or that at least one of the layers (60) introduced into the free space (18) is thinner than 5 nm. Method according to one of the preceding claims,
characterized, that at least one layer (60) introduced into the free space (18) consists of an electrically non-conductive material, and that this layer has a uniform thickness, which is preferably dimensioned such that electrons can only cross the layer due to the tunnel effect. Method according to claim 12,
characterized, that the layer (60) made of an electrically conductive material is introduced by electrochemical deposition, that the layer is preferably oxidized to the electrically non-conductive layer (60) by anodic oxidation, and / or that the layer is preferably partially or completely oxidized. Method according to one of the preceding claims,
characterized, that the substrate layer (12) contains a quartz glass or an inorganic electrically non-conductive material, and / or that the mask layer (16) and / or the sealing layer (90) contains a quartz glass or an inorganic electrically non-conductive material, and / or that the last deposited layer (60) contains a metal which forms a stable oxide, preferably aluminum, and / or that at least one layer (54, 56) made of a hard magnetic material and / or at least one layer (72, 76) made of a soft magnetic material is arranged in the free space (18). Circuit arrangement (10), with a substrate layer (12) which carries an electrically conductive contact layer (14), with an electrically non-conductive mask layer (16) overlapping on all sides of the contact layer (14), which includes a layer system (50, 60, 70) which contains at least one layer (52 to 56, 60) deposited by electrochemical deposition, the mask layer (16) being older than the deposited layer (52, 54, 60), characterized, that the mask layer (16) has a thickness (D1) which corresponds at least to the height of the layer system (50, 60, 70), and that the layer system (50, 60, 70) contains at least one electrically non-conductive layer (60) which lies between individual layers (56, 72) of the layer system (50, 60, 70). Circuit arrangement (10b), with a substrate layer (120) which carries an electrically conductive contact layer (14b), with a capsule layer (150) which is a layer system (50b, 60b, 70b) composed of several layers, of which at least one layer (52b to 56b, 60b) has been deposited by electrochemical deposition, the capsule layer (150) being younger than the deposited layer (52b to 56b, 60b), and wherein the side edges of the layers are free of materials from other layers of the layer system. Circuit arrangement (10b) according to Claim 16,
characterized in that at least one layer of the layer system has a larger base area than a layer lying between this layer and the contact layer (14b). Circuit arrangement (10) according to one of Claims 15 to 17,
characterized in that it has features that also arise in circuit arrangements that have been produced by a method according to any one of claims 1 to 14. Tunnel contact element (100, 100b), with at least two electrically conductive contact layers (14), and with an electrically non-conductive barrier layer (60) lying between the contact layers, the thickness (D2) of which is dimensioned such that electrons can only cross it due to the tunnel effect, characterized in that a contact layer (14) and / or the barrier layer (60) have been deposited by electrochemical deposition. Tunnel contact element (100, 100b), with at least two electrically conductive contact layers (14), and with an electrically non-conductive barrier layer (60) lying between the contact layers, the thickness (D2) of which is dimensioned such that electrons can only cross it due to the tunnel effect, characterized in that the barrier layer (60) has been produced by anodic oxidation. Tunnel contact element according to claim 19 or 20, characterized in that it has features which also occur in a circuit arrangement which has been produced by a method according to one of claims 1 to 14.

Images