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EP1192653A1 - Method for lateral etching with holes for making semiconductor devices - Google Patents

Method for lateral etching with holes for making semiconductor devices

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Publication number
EP1192653A1
EP1192653A1 EP00946027A EP00946027A EP1192653A1 EP 1192653 A1 EP1192653 A1 EP 1192653A1 EP 00946027 A EP00946027 A EP 00946027A EP 00946027 A EP00946027 A EP 00946027A EP 1192653 A1 EP1192653 A1 EP 1192653A1
Authority
EP
European Patent Office
Prior art keywords
silicon
layer
germanium
grid
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00946027A
Other languages
German (de)
French (fr)
Inventor
Thomas Skotnicki
Malgorzata Jurczak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Publication of EP1192653A1 publication Critical patent/EP1192653A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/687—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having cavities, e.g. porous gate dielectrics having gasses therein

Definitions

  • the present invention relates to a method of lateral etching by holes for manufacturing semiconductor elements. It finds an interesting application in high performance CMOS semiconductor devices for rapid signal processing and / or low voltage / low power applications, and more particularly in MOS field effect transistors (MOSFET).
  • MOSFET MOS field effect transistors
  • MOSFETs of silicon on insulator (SOI) architecture One of the limiting factors of conventional solid architecture MOSFETs is the substrate effect which affects the performance of the transistor. This drawback is avoided in MOSFETs of silicon on insulator (SOI) architecture by separating the thin silicon film from the substrate by a buried layer of silicon oxide.
  • SOI silicon on insulator
  • semiconductor devices based on so-called "SON" architecture silicon on nothing
  • SOI silicon on insulator
  • predetermined minimum length of the channel region is understood to mean the shortest channel length usable in a device of given technology.
  • the insulating cavity can be made of any suitable solid or gaseous dielectric material but is preferably a cavity filled with air.
  • the manufacturing process of the semiconductor device comprises: - the formation on a top surface of a silicon substrate 1 of a layer of a selectively eliminable material which preferably ensures a continuity of mesh with the silicon substrate 1;
  • the formation of the source and drain regions 5 and 6 is preferably done by an epitaxial growth of silicon then an ion implantation of dopants.
  • the implantation is advantageously followed by annealing to make the dopants implanted in the source and drain regions 5 and 6 electrically active.
  • the annealing is of short duration under high temperatures.
  • the creation of the cavity 2 after formation of the grid 7 and before formation of the source and drain regions 5 and 6 has drawbacks in the case where it is desired to leave this cavity 2 filled with air. Indeed, the activation (annealing) of the source and drain regions 5 and 6 results in the exposure of the cavity 2 to high temperatures. Exposing air-filled cavities to high annealing temperatures can lead to deterioration of the cavities.
  • the object of the present invention is to remedy the drawbacks of the aforementioned method by forming a cavity filled with air after activation of the source and drain regions 5 and 6.
  • the present invention therefore relates to a method of manufacturing a semiconductor device with an SON structure (Silicon on
  • the invention therefore proposes a method for manufacturing a semiconductor element with an SON structure comprising the following steps:
  • the source and drain regions are first produced while the selectively eliminable layers of germanium or alloy of germanium and silicon are present. It is only after the source and drain regions have formed that the selectively eliminable material is etched through the hole to form the tunnel (s), ie a cavity or cavities filled with air.
  • the etching of the hole consists in making at least one vertical hole passing through the grid, the thin layer of grid dielectric and the stack under the grid up to the layer lower of germanium or germanium and silicon alloy of the first set. It will be readily apparent to those skilled in the art that to the extent that the dimensions of the grid allow, several holes can be made through the grid.
  • At least two vertical holes are etched each passing respectively through the source region and the drain region up to the layer of germanium or of germanium and silicon alloy of the first set.
  • the source and drain regions can be formed by implantation of dopants which diffuse as far as part of the grid.
  • spacers can be formed on two lateral and opposite sides of the grid.
  • the production of such spacers is well known to those skilled in the art.
  • the source and drain regions can be formed in a conventional manner by creating recesses in the stack and into the substrate along two opposite sides of the grid, filling the recesses by epitaxial growth of silicon then implantation of dopants.
  • the source and drain regions are preferably produced by implanting dopants in the stack and as far as the substrate after the grid has been formed (flanked by spacers) and without creating the recesses.
  • the implantation of dopants according to the invention is carried out in such a way that, by lateral diffusion, the doped zones (the source regions and drain) are underlying the spacers and part of the grid.
  • the hole or holes which will be used for the lateral etching of the layer or layers of germanium or of germanium and silicon alloy can be produced by any conventional etching process such as, for example, anisotropic plasma etching.
  • the selective lateral etching of the germanium or SiGe alloy layers can be carried out via the hole (s) using any conventional method such as plasma etching or by selective chemical attack using an oxidizing solution like this. is well known.
  • the selective lateral etching of the layer (s) of germanium or of germanium and silicon alloy via a hole is controlled so as to form a tunnel (s) ) extending as far as the spacers, for example by adjusting parameters of the etching process, in particular the time and temperature of selective lateral etching.
  • FIGS. 2 and 3 are schematic sectional views illustrating the main steps for implementing the method of manufacturing a device according to the invention, before etching the holes;
  • FIGS. 4a, 4b and 4c are schematic sectional views of the main steps of an embodiment of the method of manufacturing a device according to the invention, with at least one hole through the grid;
  • FIG. 5 is a simplified sectional view of a device produced according to the method of the invention illustrated by Figures 4a-4c, but with two holes etched in the grid;
  • FIGS. 6a, 6b and 6c are schematic sectional views of the main steps of another embodiment of the method of manufacturing a device, with holes through the source and drain regions, according to l 'invention.
  • the invention is not limited thereto, a description will now be given of the process for manufacturing a MOSFET transistor with an SON structure comprising two tunnels filled with air.
  • FIG. 2 shows a silicon substrate 12, the upper part of which is surrounded by an isolation box 13 of cylindrical shape with rectangular section.
  • a first assembly is formed, composed of a lower layer of an alloy of silicon and germanium SiGe 14 and an upper layer of silicon 15.
  • a second set also composed of a lower layer of silicon-germanium alloy 16 and an upper layer of silicon 17.
  • the silicon layers 15, 17 and of silicon-germanium alloy 14, 16 of the two sets are formed by selective epitaxy so as to ensure a transfer of the mesh continuity from the silicon substrate 12 to the consecutive layers of silicon 15, 17 and of the silicon-germanium alloy 14, 16.
  • the stack thus formed completely covers the upper surface of the silicon substrate 12.
  • the thin layer of silicon dioxide 18 does not cover the isolation box 13.
  • the two secondary lateral sides are in a direction perpendicular to the two primary lateral sides P and P ', that is to say perpendicular to the plane of the section.
  • a grid 19 of polycrystalline silicon is then formed on a central part of the thin layer of grid dielectric 18 along the primary lateral sides P and P ', and over the entire length of the thin layer of grid dielectric 18 along both sides secondary sides up to two sides of the isolation box 13.
  • the grid 19 is flanked spacers 20, 21, for example made of silicon nitride Si 3 N 4 , on the two primary lateral sides P and P '.
  • the source and drain regions 22, 23 are obtained by implanting dopants along the spacers 20, 21, in the layer of silicon dioxide 18, in the layers of silicon 15, 17 and of the silicon-germanium alloy. 14, 16 of the two assemblies and, optionally, in an upper part of the silicon substrate 12.
  • the two source and drain regions diffuse laterally towards one another under the spacers without ever connecting.
  • the region 12a under the gate not reached by the diffusion of the dopants is an active area.
  • 12a consists of the stack of layers 14, 15, 16 and 17, all of them undoped.
  • the implantation of dopants contains two stages:
  • annealing or activating the source and drain regions, following the first, in which the device is annealed so as to allow a crystalline rearrangement of the implanted regions and to make the dopants (ions) electrically active .
  • the annealing is of short duration under a high temperature of the order of 850 ° C. at most.
  • the device is covered, on its upper part, with a layer 24 of a passivation material such as silicon dioxide.
  • a vertical hole 25 is formed through the layer of silicon dioxide 24, the layer of polycrystalline silicon forming the grid 19, the layer of silicon dioxide 18 and through the active area, c that is to say the silicon layers 15, 17 and of the silicon-germanium alloy 14, 16 of the two sets up to an upper part of the silicon substrate 12.
  • the hole 25 can be formed by anisotropic plasma etching .
  • a selective lateral etching of the tunnels 26 and 27 is carried out in the respective layers of the silicon-germanium alloy 16 and 14 so that this etching extends laterally as far as the spacers.
  • passivation is carried out internal of hole 25 and tunnels 26 and 27 by thermal oxidation.
  • a thin layer of silicon dioxide is formed on the walls of the hole 25 and of the tunnels 26 and 27.
  • the part of the undoped silicon layer 15 present in the active area constitutes the channel 29 of the transistor.
  • the channel 29 is a layer in which the hole 25 is located.
  • the thickness of the silicon layer 17 is such that the growth of the thin layer of gate dielectric 18 and the internal passivation of the hole 25 and of the tunnels 26 and 27 completely consume this silicon layer 17 at the tunnel 26.
  • the thicknesses of the layers of the silicon-germanium alloy 14, 16 and the silicon dioxide 28 are such that the growth of the thin layer of gate dielectric 18 and the internal passivation of the hole 25 and of the tunnels 26 and 27 completely consume this silicon layer 17 at the tunnel 26.
  • internal passivation material are such that the hole 25 and the tunnels 26, 27 are not blocked. However, they can be plugged with silicon dioxide 28 if necessary.
  • FIG. 4c shows a transistor according to the invention in which two holes 25 and 31 have been made in the gate 19.
  • the hole 31 is obtained in the same way as the hole 25 with creation of tunnels and internal passivation.
  • the external passivation layer (silicon dioxide 24), the isolation box 13 as well as the spacers 20, 21 are not shown for reasons of simplification.
  • FIGS. 4a and 4b have been obtained in a section plane in the direction AA- as illustrated in FIG. 4c.
  • FIG. 4c also shows current lines 30 starting from the source region 22 and going towards the drain region 23 passing through the channel 29.
  • FIG. 4c also shows the two primary lateral sides P and P 'and the two secondary lateral sides S and S '.
  • Figure 5 is a simplified sectional view of a device obtained by the method illustrated in Figures 4a-4c in which the passivation layers (24, 28) are missing. The plane of the section is in a direction S-S 'passing through the holes 25 and 31 (FIG. 4c).
  • FIGS. 6a, 6b and 6c show another embodiment in which, starting from the element of FIG. 3, that is to say once the external passivation (silicon dioxide 24) has been carried out, at least etching a hole 32 in the source region 22 and at least one hole 33 in the drain region 23 through the external passivation layer 24, the thin layer of gate dielectric 18 and the layers of silicon 15, 17 and of alloy silicon-germanium sets at least up to the layer of silicon-germanium alloy 14. The grid remains intact. Selective lateral etching is then carried out, through the holes 32 and 33, to eliminate the layers of silicon-germanium alloy 14, 16 and form tunnels 34 and 35.
  • the external passivation silicon dioxide 24
  • the etching of the layers of silicon-germanium alloy 16 and 14 can be performed by isotropic plasma or by wet etching using an oxidizing solution.
  • an internal passivation of the walls of the tunnels 34, 35 is carried out (FIG. 6) with silicon dioxide 36 by thermal oxidation.
  • the tunnels 34 and 35 can also be completely filled with silicon dioxide 36 or other dielectric material.
  • Figure 6c shows a top view of such a device in which four holes are made. We also represented contacts
  • the method thus described makes it possible to produce SON structures in which the tunnels are etched after the source and drain regions have been formed.
  • the tunnels are therefore not subjected to high temperatures due to the activation of the source and drain regions.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention concerns a method for making a semiconductor device with SON structure. It consists in forming on a silicon substrate (12) a stack of layers comprising first and second successive assemblies, each consisting relative to the substrate, a lower silicon-germanium (SiGe) layer (14, 16) and an upper silicon layer (15, 17); in standard manner, forming a gate dielectric layer (18), a gate (19), spacers (20, 21), source and drain regions (22, 23) by ion implantation, and an outer passivation layer (24); then producing a vertical hole (25) in the gate down to the lower SiGe layer (14) so as to etch part of the SiGe layers (14, 16) and form tunnels (26, 27); then producing an inner passivation of the walls of the hole (25) and of the tunnels so that the tunnels can remain void or be filled.

Description

Procédé de gravure latérale par trous pour fabriquer des dispositifs semi-conducteurs. Method of lateral etching by holes for manufacturing semiconductor devices.

La présente invention concerne un procédé de gravure latérale par trous pour fabriquer des éléments semi-conducteurs. Elle trouve une application intéressante dans les dispositifs semi-conducteurs CMOS à haute performance pour le traitement rapide de signaux et/ou des applications basse tension/basse puissance, et plus particulièrement dans les transistors MOS à effet de champ (MOSFET).The present invention relates to a method of lateral etching by holes for manufacturing semiconductor elements. It finds an interesting application in high performance CMOS semiconductor devices for rapid signal processing and / or low voltage / low power applications, and more particularly in MOS field effect transistors (MOSFET).

Un des facteurs limitatifs des MOSFETs d'architecture massive classiques est l'effet de substrat qui nuit aux performances du transistor. Cet inconvénient est évité dans les MOSFETs d'architecture silicium sur isolant (SOI) en séparant le mince film de silicium du substrat par une couche enterrée d'oxyde de silicium.One of the limiting factors of conventional solid architecture MOSFETs is the substrate effect which affects the performance of the transistor. This drawback is avoided in MOSFETs of silicon on insulator (SOI) architecture by separating the thin silicon film from the substrate by a buried layer of silicon oxide.

L'élimination de l'effet de substrat dans les MOSFETs d'architecture SOI à film mince totalement appauvri résulte en un accroissement du courant de drain. Cependant, les MOSFETs d'architecture SOI ultramince souffrent d'une résistance source/drain (S/D) élevée du fait de jonctions peu profondes limitées par l'épaisseur de la couche de silicium et d'une mauvaise conductivité thermique. En outre, le coût de fabrication des substrats d'architecture SOI est élevé, ce qui a limité leur introduction sur le marché.The elimination of the substrate effect in MOSFETs of SOI architecture with a totally depleted thin film results in an increase in the drain current. However, ultrathin SOI architecture MOSFETs suffer from high source / drain resistance (S / D) due to shallow junctions limited by the thickness of the silicon layer and poor thermal conductivity. In addition, the cost of manufacturing SOI architectural substrates is high, which has limited their introduction to the market.

Pour remédier aux inconvénients de ces dispositifs d'architecture SOI ou massive, on a proposé des dispositifs semiconducteurs à base d'architecture dite "SON" (silicon on nothing) combinant les avantages des architectures massives et silicium sur isolant (SOI). Ces dispositifs semi-conducteurs, tels qu'un transistor MOS à effet de champ, permettent des épaisseurs du film de silicium ainsi que celles de l'oxyde enterré extrêmement minces, de l'ordre de quelques nanomètres.To overcome the drawbacks of these SOI or massive architecture devices, semiconductor devices based on so-called "SON" architecture (silicon on nothing) have been proposed combining the advantages of massive architectures and silicon on insulator (SOI). These semiconductor devices, such as an effect MOS transistor field, allow extremely thin thicknesses of the silicon film as well as those of the buried oxide, of the order of a few nanometers.

Un tel dispositif d'architecture dite SON dans lequel la couche diélectrique enterrée est limitée à la zone sous-jacente à la région de grille du dispositif est présenté à la figure 1.Such a so-called SON architecture device in which the buried dielectric layer is limited to the zone underlying the gate region of the device is presented in FIG. 1.

En référence à la figure 1, ce dispositif semi-conducteur comprend un substrat de silicium 1 ayant une surface supérieure revêtue d'une mince couche de diélectrique de grille 4 et dans lequel sont formées des régions de source et de drain 5 et 6 définissant entre elles une région de canal la de longueur minimale prédéterminée, une grille 7 sur la surface supérieure du corps au-dessus de la région de canal la. Ce dispositif comprend en outre dans la région de canal la entre les régions de source et de drain 5 et 6 une cavité isolante 2 continue ou discontinue délimitant avec les régions de source et de drain 5 et 6 une mince couche de silicium 3 de 1 à 50 nm d'épaisseur et située au-dessus de la cavité isolante 2, cette cavité isolante ayant une longueur représentant au moins 70% de la longueur minimale prédéterminée de la région de canal la. La grille 7 est flanquée d'espaceurs 8et 9. Des contacts 10, 11 sont prévus sur les régions de source et de drain 5, 6. Dans la suite, on utilisera, de façon interchangeable, aussi bien le terme cavité que tunnel.Referring to Figure 1, this semiconductor device comprises a silicon substrate 1 having an upper surface coated with a thin layer of gate dielectric 4 and in which are formed source and drain regions 5 and 6 defining between they a channel region la of predetermined minimum length, a grid 7 on the upper surface of the body above the channel region la. This device further comprises in the channel region la between the source and drain regions 5 and 6 a continuous or discontinuous insulating cavity 2 defining with the source and drain regions 5 and 6 a thin layer of silicon 3 from 1 to 50 nm thick and situated above the insulating cavity 2, this insulating cavity having a length representing at least 70% of the predetermined minimum length of the channel region la. The grid 7 is flanked by spacers 8 and 9. Contacts 10, 11 are provided on the source and drain regions 5, 6. In the following, we will use, interchangeably, both the term cavity and tunnel.

Dans le dispositif décrit ci-dessus, on entend par longueur minimale prédéterminée de la région de canal, la longueur de canal la plus courte utilisable dans un dispositif de technologie donnée. La cavité isolante peut être constituée de tout matériau diélectrique solide ou gazeux approprié mais est de préférence une cavité remplie d'air.In the device described above, the term predetermined minimum length of the channel region is understood to mean the shortest channel length usable in a device of given technology. The insulating cavity can be made of any suitable solid or gaseous dielectric material but is preferably a cavity filled with air.

Le procédé de fabrication du dispositif semi-conducteur qui vient d'être décrit comprend : - la formation sur une surface supérieure d'un substrat de silicium 1 d'une couche d'un matériau sélectivement éliminable qui de préférence assure une continuité de maille avec le substrat de silicium 1 ;The manufacturing process of the semiconductor device which has just been described comprises: - the formation on a top surface of a silicon substrate 1 of a layer of a selectively eliminable material which preferably ensures a continuity of mesh with the silicon substrate 1;

- la formation sur la couche de matériau sélectivement éliminable d'une mince couche de silicium 3 ayant une épaisseur de 1 à 50 nm et assurant également de préférence une continuité de maille avec le matériau sélectivement éliminable et par suite avec le substrat de silicium;the formation on the layer of material selectively eliminable of a thin layer of silicon 3 having a thickness of 1 to 50 nm and also preferably ensuring mesh continuity with the material selectively eliminable and consequently with the silicon substrate;

- la formation sur la mince couche de silicium 3 d'une mince couche de diélectrique de grille 4; - la formation sur la mince couche de diélectrique de grille 4 d'une grille 7;- The formation on the thin layer of silicon 3 of a thin layer of gate dielectric 4; - The formation on the thin layer of grid dielectric 4 of a grid 7;

- la gravure, le long de deux côtés opposés de la grille 7, de la mince couche de diélectrique de grille 4, de la mince couche de silicium 3, de la couche de matériau sélectivement éliminable et d'une partie supérieure du substrat 1 pour former des évidements;the etching, along two opposite sides of the grid 7, of the thin layer of grid dielectric 4, of the thin layer of silicon 3, of the layer of selectively eliminable material and of an upper part of the substrate 1 for forming recesses;

- la gravure latérale sélective, partielle ou totale, de la couche de matériau sélectivement éliminable pour former une cavité 2 continue ou des cavités discontinues, remplies d'air, dont la longueur totale représente au moins 70% d'une longueur minimale prédéterminée de la région de canal;the selective lateral, partial or total etching of the layer of material selectively eliminable to form a continuous cavity 2 or discontinuous cavities, filled with air, the total length of which represents at least 70% of a predetermined minimum length of the canal region;

- facultativement, le remplissage de la cavité 2 ou des cavités avec un matériau diélectrique solide; et- optionally, filling the cavity 2 or the cavities with a solid dielectric material; and

- le remplissage des évidements avec du silicium et leur dopage pour former les régions de source et de drain 5 et 6. La formation des régions de source et de drain 5 et 6 se fait de préférence par une croissance épitaxiale de silicium puis une implantation ionique de dopants. L'implantation est avantageusement suivie d'un recuit pour rendre électriquement actifs les dopants implantés dans les régions de source et de drain 5 et 6. Le recuit est de courte durée sous des températures élevées.- the filling of the recesses with silicon and their doping to form the source and drain regions 5 and 6. The formation of the source and drain regions 5 and 6 is preferably done by an epitaxial growth of silicon then an ion implantation of dopants. The implantation is advantageously followed by annealing to make the dopants implanted in the source and drain regions 5 and 6 electrically active. The annealing is of short duration under high temperatures.

Cependant, dans le procédé de fabrication décrit ci-dessus, la création de la cavité 2 après formation de la grille 7 et avant formation des régions de source et de drain 5 et 6 présente des inconvénients dans le cas où l'on désire laisser cette cavité 2 remplie d'air. En effet, l'activation (le recuit) des régions de source et de drain 5 et 6 entraîne l'exposition de la cavité 2 à des températures élevées. L'exposition des cavités remplies d'air à des températures de recuit élevées peut conduire à une détérioration des cavités.However, in the manufacturing process described above, the creation of the cavity 2 after formation of the grid 7 and before formation of the source and drain regions 5 and 6 has drawbacks in the case where it is desired to leave this cavity 2 filled with air. Indeed, the activation (annealing) of the source and drain regions 5 and 6 results in the exposure of the cavity 2 to high temperatures. Exposing air-filled cavities to high annealing temperatures can lead to deterioration of the cavities.

La présente invention a pour objet de remédier aux inconvénients du procédé précité en formant une cavité remplie d'air après l'activation des régions de source et de drain 5 et 6.The object of the present invention is to remedy the drawbacks of the aforementioned method by forming a cavity filled with air after activation of the source and drain regions 5 and 6.

La présente invention a donc pour objet un procédé de fabrication d'un dispositif semi-conducteur à structure SON (Silicon onThe present invention therefore relates to a method of manufacturing a semiconductor device with an SON structure (Silicon on

Nothing) dans lequel la cavité remplie d'air n'a pas été exposée à des températures élevées au cours de l'étape d'activation des régions de source et de drain.Nothing) in which the air-filled cavity was not exposed to high temperatures during the step of activating the source and drain regions.

L'invention propose donc un procédé de fabrication d'un élément semi-conducteur à structure SON comprenant les étapes suivantes :The invention therefore proposes a method for manufacturing a semiconductor element with an SON structure comprising the following steps:

- la formation sur une surface principale d'un substrat de silicium d'un empilement de couches comprenant au moins un ensemble de deux couches constitué d'une couche inférieure de germanium ou d'alliage de germanium et silicium et d'une couche supérieure de silicium, et ledit empilement, lorsqu'il comprend plus d'un ensemble de deux couches, comprenant un premier ensemble immédiatement adjacent au substrat et un dernier ensemble le plus éloigné du substrat;the formation on a main surface of a silicon substrate of a stack of layers comprising at least one set of two layers consisting of a lower layer of germanium or of germanium and silicon alloy and of an upper layer of silicon, and said stack, when it comprises more than one set of two layers, comprising a first set immediately adjacent to the substrate and a last set farthest from the substrate;

- la formation sur la couche supérieure de silicium de l'ensemble ou du dernier ensemble de l'empilement d'une mince couche de diélectrique de grille et d'une grille;- The formation on the upper silicon layer of the assembly or the last assembly of the stack of a thin layer of gate dielectric and a gate;

- la formation de régions de source et de drain le long de deux côtés opposés de la grille dans la mince couche de diélectrique de grille et dans l'empilement;- the formation of source and drain regions along two opposite sides of the gate in the thin layer of gate dielectric and in the stack;

- la gravure dans l'empilement d'au moins un trou au moins jusqu'à la couche inférieure de germanium ou d'alliage de germanium et silicium de l'ensemble ou du premier ensemble de l'empilement; - la gravure latérale sélective, par l'intermédiaire du trou d'au moins une partie de la (ou des) couche(s) de germamum ou d'alliage de germanium et silicium de l'empilement pour former un (ou des) tunnel(s) en dessous de la grille; et facultativement- Etching in the stack of at least one hole at least to the lower layer of germanium or germanium and silicon alloy of the assembly or the first assembly of the stack; - selective lateral etching, through the hole of at least part of the layer (s) of germamum or germanium and silicon alloy of the stack to form a tunnel (s) (s) below the grid; and optionally

- la passivation interne ou le remplissage du (ou des) tunnel(s) avec un matériau diélectrique.- internal passivation or filling of the tunnel (s) with dielectric material.

En d'autres termes, on réalise d'abord les régions de source et de drain alors que les couches sélectivement éliminables en germanium ou alliage de germanium et silicium sont présentes. C'est seulement après la formation des régions de source et de drain que l'on grave, à travers le trou, le matériau sélectivement éliminable pour former le ou les tunnels, c'est- à-dire une cavité ou des cavités remplies d'air.In other words, the source and drain regions are first produced while the selectively eliminable layers of germanium or alloy of germanium and silicon are present. It is only after the source and drain regions have formed that the selectively eliminable material is etched through the hole to form the tunnel (s), ie a cavity or cavities filled with air.

Selon un mode de mise en oeuvre de l'invention, la gravure du trou consiste en la réalisation d'au moins un trou vertical traversant la grille, la mince couche de diélectrique de grille et l'empilement sous la grille jusqu'à la couche inférieure de germanium ou d'alliage de germanium et silicium du premier ensemble. Il apparaîtra aisément à l'homme du métier que dans la mesure où les dimensions de la grille le permettent, on peut réaliser plusieurs trous à travers la grille.According to one embodiment of the invention, the etching of the hole consists in making at least one vertical hole passing through the grid, the thin layer of grid dielectric and the stack under the grid up to the layer lower of germanium or germanium and silicon alloy of the first set. It will be readily apparent to those skilled in the art that to the extent that the dimensions of the grid allow, several holes can be made through the grid.

Selon une variante avantageuse de l'invention, on grave au moins deux trous verticaux traversant chacun respectivement la région de source et la région de drain jusqu'à la couche de germanium ou d'alliage de germanium et silicium du premier ensemble. Comme précédemment, il apparaîtra aisément à l'homme du métier que dans la mesure où les dimensions des régions de source et de drain le permettent, on peut réaliser plusieurs trous dans chaque région. Cette variante permet la réalisation de dispositif nécessitant une faible dimensionnement de la grille alors que la gravure de trou dans la grille conviendrait plus à des dispositifs tels que les capteurs dans lesquels la grille peut être de grande dimension. D'une façon générale, on peut former les régions de source et de drain par implantation de dopants qui diffusent jusque sous une partie de la grille.According to an advantageous variant of the invention, at least two vertical holes are etched each passing respectively through the source region and the drain region up to the layer of germanium or of germanium and silicon alloy of the first set. As before, it will be readily apparent to those skilled in the art that as far as the dimensions of the source and drain regions allow, several holes can be made in each region. This variant allows the realization of a device requiring a small dimensioning of the grid while the etching of the hole in the grid would be more suitable for devices such as sensors in which the grid can be large. In general, the source and drain regions can be formed by implantation of dopants which diffuse as far as part of the grid.

Classiquement, après la formation de la grille, on peut former des espaceurs sur deux côtés latéraux et opposés de la grille. La réalisation de tels espaceurs est bien connue de l'homme du métier.Conventionally, after the grid has been formed, spacers can be formed on two lateral and opposite sides of the grid. The production of such spacers is well known to those skilled in the art.

La formation des régions de source et de drain peut se faire de façon classique par création d'évidements dans l'empilement et jusque dans le substrat le long de deux côtés opposés de la grille, comblement des évidements par croissance épitaxiale de silicium puis implantation de dopants. Toutefois, selon l'invention, on réalise de préférence les régions de source et de drain par implantation de dopants dans l'empilement et jusque dans le substrat après la formation de la grille (flanquée d'espaceurs) et sans création des évidements.The source and drain regions can be formed in a conventional manner by creating recesses in the stack and into the substrate along two opposite sides of the grid, filling the recesses by epitaxial growth of silicon then implantation of dopants. However, according to the invention, the source and drain regions are preferably produced by implanting dopants in the stack and as far as the substrate after the grid has been formed (flanked by spacers) and without creating the recesses.

L'implantation de dopants selon l'invention est réalisée de telle façon que, par diffusion latérale, les zones dopées (les régions de source et de drain) sont sous-jacentes aux espaceurs et à une partie de la grille.The implantation of dopants according to the invention is carried out in such a way that, by lateral diffusion, the doped zones (the source regions and drain) are underlying the spacers and part of the grid.

Le ou les trous qui serviront à la gravure latérale de la ou des couches de germanium ou d'alliage de germanium et de silicium peuvent être réalisés par tout procédé classique de gravure tel que, par exemple, une gravure par plasma anisotrope.The hole or holes which will be used for the lateral etching of the layer or layers of germanium or of germanium and silicon alloy can be produced by any conventional etching process such as, for example, anisotropic plasma etching.

La gravure latérale sélective des couches de germanium ou d'alliage SiGe peut être réalisée par l'intermédiaire du ou des trous en utilisant tout procédé classique tel qu'une gravure par plasma ou par attaque chimique sélective au moyen d'une solution oxydante comme cela est bien connu.The selective lateral etching of the germanium or SiGe alloy layers can be carried out via the hole (s) using any conventional method such as plasma etching or by selective chemical attack using an oxidizing solution like this. is well known.

De préférence, la gravure latérale sélective de la (ou des) couche(s) de germanium ou d'alliage de germanium et silicium par l'intermédiaire d'un trou, est contrôlée de façon à former un (ou des) tunnel(s) s'étendant jusque sous les espaceurs, par exemple en réglant des paramètres du procédé de gravure notamment le temps et la température de gravure latérale sélective.Preferably, the selective lateral etching of the layer (s) of germanium or of germanium and silicon alloy via a hole is controlled so as to form a tunnel (s) ) extending as far as the spacers, for example by adjusting parameters of the etching process, in particular the time and temperature of selective lateral etching.

Par ailleurs, avant l'étape de la gravure du trou, on recouvre de préférence l'ensemble du dispositif avec une couche d'un matériau de passivation. D'autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée d'un mode de mise en oeuvre nullement limitatif, et des dessins annexés, sur lesquels :Furthermore, before the etching step of the hole, the entire device is preferably covered with a layer of passivation material. Other advantages and characteristics of the invention will appear on examining the detailed description of a mode of implementation which is in no way limitative, and the appended drawings, in which:

- les figures 2 et 3 sont des vues schématiques en coupe illustrant les étapes principales de mise en oeuvre du procédé de fabrication d'un dispositif selon l'invention, avant la gravure des trous;- Figures 2 and 3 are schematic sectional views illustrating the main steps for implementing the method of manufacturing a device according to the invention, before etching the holes;

- les figures 4a, 4b et 4c sont des vues schématiques en coupe des étapes principales d'un mode de mise en oeuvre du procédé de fabrication d'un dispositif selon l'invention, avec au moins un trou à travers la grille;- Figures 4a, 4b and 4c are schematic sectional views of the main steps of an embodiment of the method of manufacturing a device according to the invention, with at least one hole through the grid;

- La figure 5 est une vue en coupe simplifiée d'un dispositif réalisé selon le procédé de l'invention illustré par les figures 4a-4c, mais avec deux trous gravés dans la grille; et- Figure 5 is a simplified sectional view of a device produced according to the method of the invention illustrated by Figures 4a-4c, but with two holes etched in the grid; and

- les figures 6a, 6b et 6c sont des vues schématiques en coupe des étapes principales d'un autre mode de mise en oeuvre du procédé de fabrication d'un dispositif, avec des trous à travers les régions de source et de drain, selon l'invention. Bien que l'invention n'y soit pas limitée, on va maintenant décrire le procédé de fabrication d'un transistor MOSFET à structure SON comportant deux tunnels remplis d'air.- Figures 6a, 6b and 6c are schematic sectional views of the main steps of another embodiment of the method of manufacturing a device, with holes through the source and drain regions, according to l 'invention. Although the invention is not limited thereto, a description will now be given of the process for manufacturing a MOSFET transistor with an SON structure comprising two tunnels filled with air.

La figure 2 montre un substrat de silicium 12 dont la partie supérieure est entourée par un caisson d'isolement 13 de forme cylindrique à section rectangulaire. Sur la surface supérieure du substrat de silicium 12 délimitée par le caisson d'isolement 13, on forme un premier ensemble composé d'une couche inférieure d'un alliage de silicium et de germanium SiGe 14 et d'une couche supérieure de silicium 15. On forme ensuite sur le premier ensemble, un second ensemble composé également d'une couche inférieure en alliage silicium- germanium 16 et d'une couche supérieure de silicium 17.FIG. 2 shows a silicon substrate 12, the upper part of which is surrounded by an isolation box 13 of cylindrical shape with rectangular section. On the upper surface of the silicon substrate 12 delimited by the isolation box 13, a first assembly is formed, composed of a lower layer of an alloy of silicon and germanium SiGe 14 and an upper layer of silicon 15. Then formed on the first set, a second set also composed of a lower layer of silicon-germanium alloy 16 and an upper layer of silicon 17.

Les couches de silicium 15, 17 et en alliage silicium-germanium 14, 16 des deux ensembles sont formées par épitaxie sélective de façon à assurer un transfert de la continuité de mailles du substrat de silicium 12 vers les couches consécutives de silicium 15, 17 et de l'alliage silicium- germanium 14, 16. L'empilement ainsi formé recouvre complètement la surface supérieure du substrat de silicium 12.The silicon layers 15, 17 and of silicon-germanium alloy 14, 16 of the two sets are formed by selective epitaxy so as to ensure a transfer of the mesh continuity from the silicon substrate 12 to the consecutive layers of silicon 15, 17 and of the silicon-germanium alloy 14, 16. The stack thus formed completely covers the upper surface of the silicon substrate 12.

Comme on le voit sur la figure 3, d'une manière classique pour la réalisation d'un transistor MOSFET, on fait croître une couche mince de diélectrique de grille 18, qui est généralement du dioxyde de silicium, sur la couche supérieure de silicium 17 du second ensemble. Sur deux côtés latéraux primaires P et P' de l'empilement constitué par les couches 14, 15, 16 et 17, la couche mince du dioxyde de silicium 18 ne recouvre pas le caisson d'isolement 13. Par contre, la couche mince de dioxyde de siliciumAs can be seen in FIG. 3, in a conventional manner for the production of a MOSFET transistor, a thin layer of gate dielectric 18, which is generally silicon dioxide, is grown on the upper layer of silicon 17 of the second set. On two primary lateral sides P and P 'of the stack formed by layers 14, 15, 16 and 17, the thin layer of silicon dioxide 18 does not cover the isolation box 13. On the other hand, the thin layer of silicon dioxide

18 s'étend jusque sur le caisson d'isolement 13 suivant les deux autres côtés latéraux secondaires de l'empilement. Sur la figure 2, les deux côtés latéraux secondaires sont suivant une direction perpendiculaire aux deux côtés latéraux primaires P et P', c'est-à-dire perpendiculaire au plan de la coupe.18 extends as far as the isolation box 13 along the other two secondary lateral sides of the stack. In FIG. 2, the two secondary lateral sides are in a direction perpendicular to the two primary lateral sides P and P ', that is to say perpendicular to the plane of the section.

On forme ensuite une grille 19 en silicium polycristallin sur une partie centrale de la couche mince de diélectrique de grille 18 suivant les côtés latéraux primaires P et P', et sur toute la longueur de la couche mince de diélectrique de grille 18 suivant les deux côtés latéraux secondaires jusque sur deux côtés du caisson d'isolement 13. La grille 19 est flanquée d'espaceurs 20, 21, par exemple constitués de nitrure de silicium Si3N4, sur les deux côtés latéraux primaires P et P'.A grid 19 of polycrystalline silicon is then formed on a central part of the thin layer of grid dielectric 18 along the primary lateral sides P and P ', and over the entire length of the thin layer of grid dielectric 18 along both sides secondary sides up to two sides of the isolation box 13. The grid 19 is flanked spacers 20, 21, for example made of silicon nitride Si 3 N 4 , on the two primary lateral sides P and P '.

Les régions de source et de drain 22, 23, sont obtenues par implantation de dopants le long des espaceurs 20, 21, dans la couche de dioxyde de silicium 18, dans les couches de silicium 15, 17 et de l'alliage silicium-germanium 14, 16 des deux ensembles et, éventuellement, dans une partie supérieure du substrat de silicium 12. Les deux régions de source et de drain diffusent latéralement l'une vers l'autre sous les espaceurs sans jamais se connecter. La région 12a sous la grille non atteinte par la diffusion des dopants est une zone active. La zone activeThe source and drain regions 22, 23 are obtained by implanting dopants along the spacers 20, 21, in the layer of silicon dioxide 18, in the layers of silicon 15, 17 and of the silicon-germanium alloy. 14, 16 of the two assemblies and, optionally, in an upper part of the silicon substrate 12. The two source and drain regions diffuse laterally towards one another under the spacers without ever connecting. The region 12a under the gate not reached by the diffusion of the dopants is an active area. The active area

12a est constituée de l'empilement des couches 14, 15, 16 et 17, toutes non dopées.12a consists of the stack of layers 14, 15, 16 and 17, all of them undoped.

L'implantation de dopants renferme deux étapes :The implantation of dopants contains two stages:

- une première étape d'implantation proprement dite dans laquelle on bombarde les régions cibles avec des ions dopants, eta first implantation step proper in which the target regions are bombarded with doping ions, and

- une seconde étape dite de recuit ou d'activation des régions de source et de drain, faisant suite à la première, dans laquelle le dispositif est recuit de façon à permettre un réarrangement cristallin des régions implantées et rendre électriquement actifs les dopants (ions). Le recuit est de courte durée sous une température élevée de l'ordre de 850°C au plus.- a second step called annealing or activating the source and drain regions, following the first, in which the device is annealed so as to allow a crystalline rearrangement of the implanted regions and to make the dopants (ions) electrically active . The annealing is of short duration under a high temperature of the order of 850 ° C. at most.

Puis, d'une manière bien connu de l'homme du métier, on recouvre le dispositif, sur sa partie supérieure, par une couche 24 d'un matériau de passivation tel que le dioxyde de silicium.Then, in a manner well known to those skilled in the art, the device is covered, on its upper part, with a layer 24 of a passivation material such as silicon dioxide.

On forme alors, conformément à la figure 4a, un trou vertical 25 à travers la couche de dioxyde de silicium 24, la couche de silicium en polycristallin formant la grille 19, la couche de dioxyde de silicium 18 et à travers la zone active, c'est-à-dire les couches de silicium 15, 17 et de l'alliage silicium-germanium 14, 16 des deux ensembles jusqu'à une partie supérieure du substrat de silicium 12. On peut former le trou 25 par gravure par plasma anisotrope.Then, in accordance with FIG. 4a, a vertical hole 25 is formed through the layer of silicon dioxide 24, the layer of polycrystalline silicon forming the grid 19, the layer of silicon dioxide 18 and through the active area, c that is to say the silicon layers 15, 17 and of the silicon-germanium alloy 14, 16 of the two sets up to an upper part of the silicon substrate 12. The hole 25 can be formed by anisotropic plasma etching .

On réalise ensuite, à travers le trou 25, une gravure sélective latérale des tunnels 26 et 27 dans les couches respectives de l'alliage de silicium-germanium 16 et 14 de sorte que cette gravure s'étende latéralement jusque sous les espaceurs. Comme le montre la figure 4b, on effectue une passivation interne du trou 25 et des tunnels 26 et 27 par oxydation thermique. En d'autres termes, on forme une mince couche de dioxyde de silicium sur les parois du trou 25 et des tunnels 26 et 27. La partie de la couche de silicium 15 non dopée présente dans la zone active constitue le canal 29 du transistor. Le canal 29 est une couche dans laquelle se trouve le trou 25. De préférence, l'épaisseur de la couche de silicium 17 est telle que la croissance de la mince couche de diélectrique de grille 18 et la passivation interne du trou 25 et des tunnels 26 et 27 consomment complètement cette couche de silicium 17 au niveau du tunnel 26. Les épaisseurs des couches de l'alliage silicium-germanium 14, 16 et du dioxyde de silicium 28Then, through the hole 25, a selective lateral etching of the tunnels 26 and 27 is carried out in the respective layers of the silicon-germanium alloy 16 and 14 so that this etching extends laterally as far as the spacers. As shown in Figure 4b, passivation is carried out internal of hole 25 and tunnels 26 and 27 by thermal oxidation. In other words, a thin layer of silicon dioxide is formed on the walls of the hole 25 and of the tunnels 26 and 27. The part of the undoped silicon layer 15 present in the active area constitutes the channel 29 of the transistor. The channel 29 is a layer in which the hole 25 is located. Preferably, the thickness of the silicon layer 17 is such that the growth of the thin layer of gate dielectric 18 and the internal passivation of the hole 25 and of the tunnels 26 and 27 completely consume this silicon layer 17 at the tunnel 26. The thicknesses of the layers of the silicon-germanium alloy 14, 16 and the silicon dioxide 28

(matériau de passivation interne) sont telles que le trou 25 et les tunnels 26, 27 ne sont pas bouchés. Cependant, on peut les boucher par le dioxyde de silicium 28 si nécessaire.(internal passivation material) are such that the hole 25 and the tunnels 26, 27 are not blocked. However, they can be plugged with silicon dioxide 28 if necessary.

La figure 4c montre un transistor selon l'invention dans lequel on a réalisé deux trous 25 et 31 dans la grille 19. Le trou 31 est obtenu de la même façon que le trou 25 avec création de tunnels et passivation interne. La couche de passivation externe (dioxyde de silicium 24), le caisson d'isolement 13 ainsi que les espaceurs 20, 21 ne sont pas représentés pour des raisons de simplification. Les figures 4a et 4b ont été obtenu dans un plan de coupe suivant la direction A- A' comme illustrée sur la figure 4c.FIG. 4c shows a transistor according to the invention in which two holes 25 and 31 have been made in the gate 19. The hole 31 is obtained in the same way as the hole 25 with creation of tunnels and internal passivation. The external passivation layer (silicon dioxide 24), the isolation box 13 as well as the spacers 20, 21 are not shown for reasons of simplification. FIGS. 4a and 4b have been obtained in a section plane in the direction AA- as illustrated in FIG. 4c.

On voit également sur la figure 4c des lignes de courant 30 partant de la région de source 22 et se dirigeant vers la région de drain 23 en passant par le canal 29. La figure 4c montre également les deux côtés latéraux primaires P et P' et les deux côtés latéraux secondaires S et S'. La figure 5 est une vue en coupe simplifiée d'un dispositif obtenu par le procédé illustré par les figures 4a-4c dans laquelle manque les couches de passivation (24, 28). Le plan de la coupe est suivant une direction S-S' passant par les trous 25 et 31 (figure 4c).FIG. 4c also shows current lines 30 starting from the source region 22 and going towards the drain region 23 passing through the channel 29. FIG. 4c also shows the two primary lateral sides P and P 'and the two secondary lateral sides S and S '. Figure 5 is a simplified sectional view of a device obtained by the method illustrated in Figures 4a-4c in which the passivation layers (24, 28) are missing. The plane of the section is in a direction S-S 'passing through the holes 25 and 31 (FIG. 4c).

Les figures 6a, 6b et 6c montrent un autre mode de réalisation dans lequel, partant de l'élément de la figure 3, c'est-à-dire une fois la passivation externe (dioxyde de silicium 24) réalisée, on grave au moins un trou 32 dans la région de source 22 et au moins un trou 33 dans la région de drain 23 en traversant la couche de passivation externe 24, la couche mince de diélectrique de grille 18 et les couches de silicium 15, 17 et d'alliage silicium-germanium des ensembles au moins jusqu'à la couche de l'alliage de silicium-germanium 14. La grille reste intacte. On réalise ensuite une gravure sélective latérale, à travers les trous 32 et 33, pour éliminer les couches en alliage silicium-germanium 14, 16 et former des tunnels 34 et 35. La gravure des couches en alliage de silicium- germanium 16 et 14 peuvent être effectuée par plasma isotrope ou par gravure humide au moyen d'une solution oxydante. Comme dans le cas du trou 25 dans la grille 19, on effectue (figure 6) une passivation interne des parois des tunnels 34, 35 avec du dioxyde de silicium 36 par oxydation thermique. Les tunnels 34 et 35 peuvent également être complètement remplis de dioxyde de silicium 36 ou d'un autre matériau diélectrique.FIGS. 6a, 6b and 6c show another embodiment in which, starting from the element of FIG. 3, that is to say once the external passivation (silicon dioxide 24) has been carried out, at least etching a hole 32 in the source region 22 and at least one hole 33 in the drain region 23 through the external passivation layer 24, the thin layer of gate dielectric 18 and the layers of silicon 15, 17 and of alloy silicon-germanium sets at least up to the layer of silicon-germanium alloy 14. The grid remains intact. Selective lateral etching is then carried out, through the holes 32 and 33, to eliminate the layers of silicon-germanium alloy 14, 16 and form tunnels 34 and 35. The etching of the layers of silicon-germanium alloy 16 and 14 can be performed by isotropic plasma or by wet etching using an oxidizing solution. As in the case of the hole 25 in the grid 19, an internal passivation of the walls of the tunnels 34, 35 is carried out (FIG. 6) with silicon dioxide 36 by thermal oxidation. The tunnels 34 and 35 can also be completely filled with silicon dioxide 36 or other dielectric material.

La figure 6c montre une vue de dessus d'un tel dispositif dans lequel quatre trous sont effectués. On a également représenté des contactsFigure 6c shows a top view of such a device in which four holes are made. We also represented contacts

37, 38 d'accès aux régions de source et de drain 22, 23. La couche de passivation externe (dioxyde de silicium 24), le caisson d'isolement 13 ainsi que les espaceurs 20, 21 ne sont pas représentés pour des raisons de simplification.37, 38 for access to the source and drain regions 22, 23. The external passivation layer (silicon dioxide 24), the isolation box 13 as well as the spacers 20, 21 are not shown for reasons of simplification.

Le procédé ainsi décrit permet de réaliser des structures SON dans lesquelles les tunnels sont gravés après la formation des régions de source et de drain. Les tunnels ne sont donc pas soumis à des températures élevées dues à l'activation des régions de source et de drain. The method thus described makes it possible to produce SON structures in which the tunnels are etched after the source and drain regions have been formed. The tunnels are therefore not subjected to high temperatures due to the activation of the source and drain regions.

Claims

REVENDICATIONS 1. Procédé de fabrication d'un dispositif semi-conducteur, caractérisé par le fait qu'il comprend :1. Method for manufacturing a semiconductor device, characterized in that it comprises: - la formation sur une surface principale d'un substrat de silicium (12) d'un empilement (14, 15, 16, 17) de couches comprenant au moins un ensemble de deux couches constitué d'une couche inférieure de germamum ou d'alliage de germanium et silicium (14, 16) et d'une couche supérieure de silicium (15, 17), et ledit empilement, lorsqu'il comprend plus d'un ensemble de deux couches, comprenant un premier ensemble (14, 15) immédiatement adjacent au substrat et un dernier ensemble (16, 17) le plus éloigné du substrat;- The formation on a main surface of a silicon substrate (12) of a stack (14, 15, 16, 17) of layers comprising at least one set of two layers consisting of a lower layer of germamum or alloy of germanium and silicon (14, 16) and an upper layer of silicon (15, 17), and said stack, when it comprises more than one set of two layers, comprising a first set (14, 15) immediately adjacent to the substrate and a last assembly (16, 17) furthest from the substrate; - la formation sur la couche supérieure de silicium de l'ensemble ou du dernier ensemble (17) de l'empilement d'une mince couche de diélectrique de grille (18) et d'une grille (19);- The formation on the upper silicon layer of the assembly or of the last assembly (17) of the stack of a thin layer of gate dielectric (18) and of a gate (19); - la formation de régions de source et de drain (22, 23) le long de deux côtés opposés (P, P') de la grille dans la mince couche de diélectrique de grille (18) et dans l'empilement (14, 15, 16, 17);- the formation of source and drain regions (22, 23) along two opposite sides (P, P ') of the grid in the thin layer of gate dielectric (18) and in the stack (14, 15 , 16, 17); - la gravure dans l'empilement d'au moins un trou (25) au moins jusqu'à la couche inférieure de germanium ou d'alliage de germanium et silicium (14) de l'ensemble ou du premier ensemble de l'empilement; - la gravure latérale sélective, par l'intermédiaire du trou d'au moins une partie de la couche ou des couches de germanium ou d'alliage de germanium et silicium (14, 16) de l'empilement pour former un tunnel ou des tunnels (26, 27) en dessous de la grille (19); et facultativement- The etching in the stack of at least one hole (25) at least up to the lower layer of germanium or germanium and silicon alloy (14) of the assembly or of the first assembly of the stack; - selective lateral etching, through the hole of at least part of the layer or layers of germanium or germanium and silicon alloy (14, 16) of the stack to form a tunnel or tunnels (26, 27) below the grid (19); and optionally - la passivation interne ou le remplissage du tunnel ou des tunnels avec un matériau diélectrique (28).- internal passivation or filling of the tunnel or tunnels with a dielectric material (28). 2. Procédé de fabrication selon la revendication 1, caractérisé par le fait que la gravure du trou (25) consiste en la réalisation d'au moins un trou vertical traversant la grille (19), la mince couche de diélectrique de grille (18) et l'empilement (14, 15, 16, 17) sous la grille jusqu'à la couche inférieure de germanium ou d'alliage de germanium et silicium2. Manufacturing method according to claim 1, characterized in that the etching of the hole (25) consists in making at least one vertical hole passing through the grid (19), the thin layer of grid dielectric (18) and the stack (14, 15, 16, 17) under the grid up to the lower layer of germanium or germanium and silicon alloy (14) du premier ensemble (14, 15).(14) of the first set (14, 15). 3. Procédé de fabrication selon la revendication 1, caractérisé par le fait qu'on grave au moins deux trous (32, 33) verticaux traversant chacun respectivement la région de source et la région de drain (22, 23) jusqu'à la couche de germanium ou d'alliage de germanium et silicium (14) du premier ensemble (14, 15).3. Manufacturing process according to claim 1, characterized in that at least two vertical holes (32, 33) are etched through each respectively the source region and the drain region (22, 23) up to the germanium or germanium and silicon alloy layer (14) of the first set (14, 15). 4. Procédé de fabrication selon l'une quelconque des revendications précédentes, caractérisé par le fait qu'on forme les régions de source et de drain (22, 23) par implantation de dopants qui diffusent jusque sous une partie de la grille (19).4. Manufacturing method according to any one of the preceding claims, characterized in that the source and drain regions (22, 23) are formed by implantation of dopants which diffuse as far as part of the grid (19) . 5. Procédé de fabrication selon l'une quelconque des revendications précédentes, caractérisé par le fait qu'après la formation de la grille, on forme des espaceurs (20, 21) sur deux côtés latéraux et opposés (P, P') de la grille.5. Manufacturing method according to any one of the preceding claims, characterized in that after the formation of the grid, spacers (20, 21) are formed on two lateral and opposite sides (P, P ') of the wire rack. 6. Procédé de fabrication selon la revendication 5, caractérisé par le fait que la gravure latérale sélective de la couche ou des couches de germanium ou d'alliage de germanium et silicium (14, 16) par l'intermédiaire d'un trou, est contrôlée de façon à former un tunnel ou des tunnels (26, 27) s 'étendant jusque sous les espaceurs (20, 21).6. Manufacturing method according to claim 5, characterized in that the selective lateral etching of the layer or layers of germanium or germanium and silicon alloy (14, 16) via a hole, is controlled so as to form a tunnel or tunnels (26, 27) extending as far as the spacers (20, 21). 7. Procédé de fabrication selon l'une quelconque des revendications précédentes, caractérisé par le fait qu'avant l'étape de la gravure du trou (25, 32, 33), on recouvre l'ensemble du dispositif avec une couche (24) d'un matériau de passivation. 7. Manufacturing method according to any one of the preceding claims, characterized in that before the step of etching the hole (25, 32, 33), the entire device is covered with a layer (24) passivation material.
EP00946027A 1999-06-28 2000-06-27 Method for lateral etching with holes for making semiconductor devices Withdrawn EP1192653A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9908248 1999-06-28
FR9908248A FR2795554B1 (en) 1999-06-28 1999-06-28 HOLES LATERAL ENGRAVING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
PCT/FR2000/001796 WO2001001477A1 (en) 1999-06-28 2000-06-27 Method for lateral etching with holes for making semiconductor devices

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FR2795554A1 (en) 2000-12-29
WO2001001477A1 (en) 2001-01-04

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