Classifications

• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00733—Cryptography or similar special procedures in a franking system
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00193—Constructional details of apparatus in a franking system
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00193—Constructional details of apparatus in a franking system
  • G07B2017/00233—Housing, e.g. lock or hardened casing
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00193—Constructional details of apparatus in a franking system
  • G07B2017/00258—Electronic hardware aspects, e.g. type of circuits used
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00314—Communication within apparatus, personal computer [PC] system, or server, e.g. between printhead and central unit in a franking machine
  • G07B2017/00346—Power handling, e.g. power-down routine
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
  • G07B2017/00395—Memory organization
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
  • G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
  • G07B2017/00395—Memory organization
  • G07B2017/00403—Memory zones protected from unauthorized reading or writing
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00733—Cryptography or similar special procedures in a franking system
  • G07B2017/00846—Key management
  • G07B2017/00862—Key storage, e.g. escrowing by trusted third party
• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
  • G07B17/00—Franking apparatus
  • G07B17/00733—Cryptography or similar special procedures in a franking system
  • G07B2017/00959—Cryptographic modules, e.g. a PC encryption board
  • G07B2017/00967—PSD [Postal Security Device] as defined by the USPS [US Postal Service]

Definitions

• the invention relates generally to postage meters (franking machines), and relates particularly to systems in which postage value is stored in a postal security device (PSD) so as to be protected against undetected tampering.
• PSD postal security device
• nonsecure printers such as laser printers, ink-jet printers, and thermal transfer printers.
• Such printers are termed “nonsecure” because the printer itself is not in a secure housing and because the communications channel linking the printer to other apparatus is nonsecure.
• nonsecure printers because the printer itself is not in a secure housing and because the communications channel linking the printer to other apparatus is nonsecure.
• the proposed anti-fraud measure is to store information within the indicia which would permit detecting fraud.
• the indicium would include not only human-readable text such as a date and a postage amount, but would also include machine- readable information, for example by means of a two-dimensional bar code.
• the machine- readable information would be cryptographically signed, and would include within it some information intended to make fraud more difficult.
• the information would typically include an identification of the postage meter license (granted by the meter manufacturer or by the postal authorities, depending on the country), an indication of the number of mail pieces franked, the postage amount, a postal security device identifier about which more will be said later, the date and time, and a zip code or post code of the mail piece addressee.
• the typical apparatus for printing such "encrypted indicia" postage includes what is called a postal security device or PSD.
• PSD has a secure housing, and within the secure housing are the accounting registers as well as a cryptographic engine.
• the engine permits cryptographic authentication and signing for communication with an external device such as the computer of the meter manufacturer or of the post office.
• the engine also permits creation of postal indicia which contain specified information and which are cryptographically signed.
• the PSD may well be physically small as compared to traditional postage meters.
• the PSD may be the size of a PCMCIA card or the size of a smart card.
• the memory must be protected against inadvertent damage due to malfunction of the processor of the PSD, for example as set forth in US Pat. No. 5668973, Protection system for critical memory information owned by the same assignee as the assignee of the present application.
• the PSD must handle power failure in a graceful fashion, for example as set forth in US Pat. No. 5712542, Postage meter with improved handling of power failure, also owned by the same assignee as the assignee of the present application.
• the printer may preferably be that described in PCT publication no. 97-46389, Printing apparatus, also owned by the same assignee as the assignee of the present application. While it has been proposed that the PSD contain a real-time clock which is keeping time continuously, desirably this requirement may be avoided as described in PCT publication no. 98-08325, Printing postage with cryptographic clocking security, also owned by the same assignee as the assignee of the present application. PSDs can form part of a network with multiple printers as described in PCT publication no. 98-13790, Proof of postage digital franking, also owned by the same assignee as the assignee of the present application.
• the entire system of PSDs depends on the use of cryptographic keys.
• the keys are used for authenticating communications between the PSD and the manufacturer's system or the postal authority's system. Such communications are used to set up and maintain the PSDs, and are used to refill or "reset” the PSDs to reflect the ability to print more postage.
• the keys are also used to cryptographically "sign" information printed in the postal indicia. If the cryptographic keys were compromised, a user might be able to defraud the post office or the PSD manufacturer or both. Many approaches have been proposed for protection of such cryptographic keys from compromise.
• the usual approach is to place the cryptographic keys in a RAM (random access memory) of a type which keeps its contents only so long as the RAM receives power from a battery.
• the secure housing of the PSD is designed to include a tamper switch, so that if the secure housing is tampered with, the switch opens. The switch interrupts power to the
• RAM random access memory
• RAM random access memory
• its contents are lost.
• the information in the RAM for example, the cryptographic keys
• Another proposed approach is to employ commercial memory chips (such as the Dallas Semiconductor DS1283 and Benchmarq bq3283) offer a pin on the package which will clear the memory based on a predetermined input voltage level.
• the tamper switch is set up to apply the predetermined voltage upon detection of tampering.
• EP 820 041 it is suggested that the secure housing of an old-style mechanical or electromechanical postage meter be set up to contain an air pressure that is distinctively higher than or lower than normal atmospheric pressure. If the secure housing is violated, the pressure within the secure housing changes to match the ambient pressure. A sensor within the housing detects the pressure change and thus the violation. The sensor disables further function of the postage meter.
• the approach of cutting power to a volatile memory such as the RAM discussed above has a drawback in that during periods of power-down, the RAM depends on an internal battery to avoid loss of the information in the RAM.
• the data to be protected may include cryptographic keys used for PSD configuration, keys used for remote resetting (refilling), keys used for signing postal indicia, and keys used for the management of the other keys.
• a RAM big enough to hold all of these important items of data will also draw a non-negligible current from the internal battery. This may lead to a limited and commercially unacceptable battery life. It would thus be desirable to have a PSD design which protects the many important items of data stored within, and yet which does not draw very much battery power and so permits a commercially acceptable battery life.
• a postal security device contains a nonvolatile memory which does not depend on battery power, such as an EEPROM, and contains a nonvolatile memory which does depend on battery power, such as a static RAM.
• the PSD also contains an encryption engine.
• An encryption key is developed and is stored in the static RAM, which is sized to be only large enough to contain the encryption key.
• a large body of data, too large to fit in the static RAM, is encrypted by means of the encryption engine and with reference to the encryption key, and is stored in the EEPROM. This body of data typically includes cryptographic keys and sensitive bit-images.
• a large RAM typically a dynamic RAM
• a tamper switch cuts power to both RAMs in the event of tampering. In this way, the battery power required to maintain the PSD during power-off periods is minimal, and yet the large body of data will be inaccessible in the event of tampering.
• Fig. 1 is a schematic functional block diagram of a system according to the invention.
• Fig. 1 shows a postal security device (PSD) in accordance with the invention.
• PSD postal security device
• the PSD has a microprocessor 12 which communicates on a bus 22 with an input/output (I/O) device 18, a memory which does not require battery backup 13 which may be for example an EEPROM or flash memory, a relatively small RAM 14, a ROM 22, and a larger RAM 16.
• the I/O device 18 communicates with external apparatus by means of communications channel 19 which may be a serial asynchronous data line. External power 21 and ground 20 are also defined.
• the larger RAM 16, and most of the other active components, receive external power.
• the smaller RAM 14 is additionally able to receive power from a backup battery 15, preferably a lithium cell with a very long (e.g. ten year) life.
• a tamper switch 17 is provided which, when triggered, can cut power to both the small RAM 14 and the large RAM 16.
• a large body of data is assumed to require protection from a tampering user.
• the EEPROM is selected to be large enough to hold this body of data after it has been encrypted.
• the body of data (or selected portions thereof) is decrypted and transferred to RAM 16.
• This decryption is performed by the microprocessor 12 executing a decryption routine stored in the ROM 22, and the decryption is done with respect to a decryption key in the RAM 14.
• the decryption may be performed by an optional engine omitted for clarity in Fig. 1.
• the decrypted data in RAM 16 are used as needed for the ordinary functions of the PSD, which include communicating via the communications channel 19 with a user computer, with a manufacturer's system, or with a postal authority system, and can include generating postal indicia which are to be printed by means of a printer.
• the body of data that requires protection from a tampering user may be located "in the clear", that is, unencrypted, in the RAM 16.
• This encryption is performed by the processor 12 executing encryption software in the ROM 22, or may optionally be performed by an encryption engine omitted for clarity in Fig. 1.
• the power-down condition for the PSD 10 assumes that no power is present at line 21. In that event, the only powered device is RAM 14.
• RAM 14 was purposefully selected to be large enough to hold the encryption key but not much larger, and in any event is smaller than the large body of data that is understood to require protection from a tampering user.
• the battery life is optimized, especially as compared with the shorter battery life that would result if the large body of data were all in battery-backed-up RAM.
• Tampering may happen during a time when external power 21 is present.
• the tamper switch should cut power to the RAM 14. (Or, alternatively, the tamper switch should apply to RAM 14 the predetermined voltage that clears the RAM.)
• the tamper switch will also cut power to the RAM 16 (or clear the RAM 16), for the reason that some of the body of sensitive data may be present "in the clear" in the RAM 16, and should not fall into the hands of the tampering user.
• the tamper switch might trigger an interrupt in the processor 12 which would cause the processor 12 to clear the sensitive portions of the RAM 16.
• Tampering may also happen during a time when external power 21 is absent.
• the RAM 16 is already, by definition, empty, as it is unpowered.
• the tamper switch causes the RAM 14 to be cleared. If the tampering user extracts the contents of the memory 13, this is of little significance, because the contents are useless unless decrypted with the assistance of the key that is no longer present in the RAM 14. If the PSD 10 is powered up again after the tampering, the decryption routine will not work because the key of RAM 14 is gone.
• the processor 12 under program control, will note the fact that RAM 14 is empty and will immediately attempt to send a message via communications channel 19 to the manufacturer or to the postal authority.

Landscapes

• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Mathematical Physics (AREA)
• Storage Device Security (AREA)
• Devices For Checking Fares Or Tickets At Control Points (AREA)
• Secondary Cells (AREA)
• Power Sources (AREA)
• Record Information Processing For Printing (AREA)
• Sealing Battery Cases Or Jackets (AREA)
• Battery Mounting, Suspending (AREA)

Applications Claiming Priority (3)

Publications (3)

Family

ID=22144347

Family Applications (1)

Country Status (6)

Families Citing this family (1)

Citations (3)

Family Cites Families (7)

• 1999
  • 1999-03-18 CA CA002324100A patent/CA2324100C/en not_active Expired - Fee Related
  • 1999-03-18 DE DE69926222T patent/DE69926222T2/de not_active Expired - Lifetime
  • 1999-03-18 EP EP99912648A patent/EP1064622B1/de not_active Expired - Lifetime
  • 1999-03-18 JP JP2000537179A patent/JP2002507802A/ja active Pending
  • 1999-03-18 WO PCT/US1999/005891 patent/WO1999048055A1/en active IP Right Grant
  • 1999-03-18 AT AT99912648T patent/ATE300069T1/de not_active IP Right Cessation

Patent Citations (3)

Non-Patent Citations (2)

Also Published As

Similar Documents

Legal Events