EP1042794A1 - Process for producing a porous layer by an electrochemical etching process - Google Patents
Process for producing a porous layer by an electrochemical etching processInfo
- Publication number
- EP1042794A1 EP1042794A1 EP98966576A EP98966576A EP1042794A1 EP 1042794 A1 EP1042794 A1 EP 1042794A1 EP 98966576 A EP98966576 A EP 98966576A EP 98966576 A EP98966576 A EP 98966576A EP 1042794 A1 EP1042794 A1 EP 1042794A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- etching
- porous layer
- porous
- producing
- etching rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/826—Materials of the light-emitting regions comprising only Group IV materials
- H10H20/8264—Materials of the light-emitting regions comprising only Group IV materials comprising polycrystalline, amorphous or porous Group IV materials
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/02—Etching
- C25F3/12—Etching of semiconducting materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
Definitions
- the invention relates to a method for producing a porous layer using an electrochemical etching process according to the preamble of claim 1. Furthermore, the invention relates to an optical component according to claim 5.
- PS porous silicon
- One area of application for PS is the use in optical components. It is known as prior art, for example from DE 4319413.3-33 or Thin solid films 276 (1996), 143-146, to produce waveguides, transmission filters, reflectors or anti-reflection coatings using layer systems made of PS.
- the optical properties of the layer systems can be specifically changed by the sequence of individual layers with different optical thicknesses.
- the optical thickness of these individual layers is influenced by their porosity and thickness.
- the Porosi- Tat and thickness is controlled for a given doping by the current density or by the duration of the electrochemical etching. It is only with the aid of the duration of the etching that it is possible, given the substrate and the current density, to set the desired layer thickness.
- the area to be etched must be defined to form such a structure.
- Etching mask leads to a curvature of the PS / substrate interface during manufacture (FIG. 1).
- strips with a length of 1 cm and a width which corresponded to their distance from the next strip were examined.
- FIG. 1 there are two curvatures. A curvature within a strip and a curvature across all strips. These curvatures result in an inhomogeneity of the layers (see FIG. 5).
- the etching for porosidization of the material is carried out in a manner known per se. It was recognized here to form an etching mask of suitable geometry with behavior tailored to the desired deep etching and to use it in the method according to the invention.
- the simultaneous production of pixels within a porosidizable structure with different properties is possible in one operation if the etching rate of each pixel is not only determined by the current density applied from the outside, but also by the different Environment of the pixel is determined.
- the surroundings of the pixels can be designed by the etching mask in such a way that the pixels have different current densities and thus different etching rates. In this way the desired different properties can be achieved.
- the method according to the invention enables several, in particular many, work steps to be replaced by a single step of suitable design.
- Another advantage of this method is that a continuous change in the properties of a porous layer is also possible. This process can be used for all electrochemical etching processes.
- the method for producing a porous layer using an electrochemical etching process includes the use of an etching mask corresponding to the desired course of the deep etching rate.
- the method according to the invention is partially formed by selecting a wedge-shaped etching mask to form a continuous course of the deep etching rate.
- the method according to the invention is advantageously embodied in that an etching mask having one or more wedge-shaped step-shaped structures is selected to form a discrete course of the deep etching rate.
- the inventive method is advantageously carried out in that silicon, germanium or aluminum is selected as the starting material for the porous layer formation. These materials are comparatively well known in their behavior with regard to etching.
- etching mask according to the invention for a continuous change in the etching rate
- Fig. 4 Surface profile measurement according to the invention, measured after the porous area has been scratched off.
- Fig. 5 Principle of measurement of the profi le measurements.
- FIG. 1 shows the depth of the porous strips etched according to the invention, measured with a surface profiler after removal of the porous silicon by sodium hydroxide solution (NaOH).
- the stripe width of the structures shown here was 1000, 500 and 250 ⁇ m.
- FIG. 2 shows the measured depth of the porous strips according to the invention after the porous layer has been removed using sodium hydroxide solution. It can be seen that in the case of a stripe width of 100 ⁇ m, the interface of a single stripe is no longer curved, but is straight. You can also see the under-etching under the mask, which was only 100 ⁇ m wide.
- FIG. 3 shows the etching mask according to the invention for achieving a continuous change in the etching rate.
- This mask is positioned on the surface to be etched.
- the surface areas below the dark areas of the etching mask according to the invention are covered, the light areas of the surface are etched. In this way it is achieved that the etching rate in the strip between the two wedge structures can be continuously adjusted or changed.
- the depth profile of porous layers according to the invention produced in this way was measured along the drawn line ABCD.
- this surface profile measurement measured after the porous area according to the invention has been scratched off, is the result shown.
- the interface between porous silicon and crystalline silicon can be seen.
- the area in which the etching rate was continuously changed by means of the lateral structuring is between points B and C.
- the exemplary embodiment shows a continuous change in the etching rate with the aid of the etching mask shown in FIG. 3.
- the area in which this effect occurs is located between the two wedge structures and thus between points B and C. In this area, the two wedge-shaped areas that are not etched continuously change the etching rate, as can be seen from FIG. 4.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Electrochemistry (AREA)
- Weting (AREA)
- Semiconductor Lasers (AREA)
- Surface Treatment Of Optical Elements (AREA)
Abstract
Description
B e s c h r e i b u n g Description
Verfahren zur Herstellung einer porösen Schicht mit Hilfe eines elektrochemischen ÄtzprozessesProcess for producing a porous layer using an electrochemical etching process
Die Erfindung betrifft ein Verfahren zur Herstellung einer porösen Schicht mit Hilfe eines elektrochemischen Ätzprozesses gemäß dem Oberbegriff des Anspruchs 1. Desweiteren betrifft die Erfindung ein optisches Bauelement gemäß Anspruch 5.The invention relates to a method for producing a porous layer using an electrochemical etching process according to the preamble of claim 1. Furthermore, the invention relates to an optical component according to claim 5.
Dieses Verfahren zur Herstellung einer porösen Schicht mit Hilfe eines elektrochemischen Ätzprozesses, sowie das Verfahren zur Beeinflussung der Ätzrate wird im folgenden ohne Einschränkung der Erfindung anhand von porösem Silicium geschildert.This method for producing a porous layer with the aid of an electrochemical etching process, as well as the method for influencing the etching rate, is described below using the porous silicon without restricting the invention.
Als Stand der Technik ist bekannt, poröses Silicium (PS) durch elektrochemisches Ätzen von Siliciumwafern herzustellen, beispielsweise zur Verwendung in der Produktion von Computerchips. Auf diese Weise gebildete Schichten haben eine schwammähnliche Struktur und weisen eine Vielzahl von interessanten Eigenschaften auf.It is known in the prior art to produce porous silicon (PS) by electrochemically etching silicon wafers, for example for use in the production of computer chips. Layers formed in this way have a sponge-like structure and have a variety of interesting properties.
Ein Anwendungsgebiet für PS ist der Einsatz in optischen Bauelementen. Es ist als Stand der Technik beispielsweise aus DE 4319413.3-33 oder Thin solid films 276 (1996), 143-146 bekannt, unter Verwendung von Schichtsystemen aus PS Wellenleiter, Transmissionsfilter, Reflektore oder Antireflexionsbeschichtungen herzustellen. Die optischen Eigenschaften der Schichtsysteme können durch die Abfolge von Einzelschichten mit verschiedener optischer Dicke gezielt verändert werden.One area of application for PS is the use in optical components. It is known as prior art, for example from DE 4319413.3-33 or Thin solid films 276 (1996), 143-146, to produce waveguides, transmission filters, reflectors or anti-reflection coatings using layer systems made of PS. The optical properties of the layer systems can be specifically changed by the sequence of individual layers with different optical thicknesses.
Die optische Dicke dieser Einzelschichten wird bei vorgegebener Dotierung durch ihre Porosität und Dicke beeinflußt. Die Porosi- tat und Dicke wird bei vorgegebener Dotierung durch die Stromdichte bzw. durch die Dauer des elektrochemischen Ätzens gesteuert. Lediglich mit Hilfe der Dauer des Ätzens ist es - be vorgegebenem Substrat und vorgegebener Stromdichte - möglich, die gewünschte Schichtdicke einzustellen.For a given doping, the optical thickness of these individual layers is influenced by their porosity and thickness. The Porosi- Tat and thickness is controlled for a given doping by the current density or by the duration of the electrochemical etching. It is only with the aid of the duration of the etching that it is possible, given the substrate and the current density, to set the desired layer thickness.
Um PS integriert mit anderen Bauelementen einsetzen zu können, muß zur Bildung einer solchen Struktur die Flache, die geatzt werden soll, definiert werden. Die bekannte Strukturierung des Substrates vor der Herstellung der porösen Schicht mit einerIn order to use PS integrated with other components, the area to be etched must be defined to form such a structure. The known structuring of the substrate before the production of the porous layer with a
Atzmaske fuhrt zu einer Krümmung des Interface PS / Substrat bei der Herstellung (Figur 1). Bei Experimenten wurden Streifen einer Lange von 1 cm und einer Breite untersucht, die jeweils ihrem Abstand von dem nächsten Streifen entsprach. Wie die Figur 1 erkennen laßt, existieren zwei Krümmungen. Eine Krümmung innerhalb eines Streifens und eine Krümmung über alle Streifen hinweg. Diese Krümmungen bewirken nachteilig eine Inhomogenität der Schichten (siehe Fig. 5) .Etching mask leads to a curvature of the PS / substrate interface during manufacture (FIG. 1). In experiments, strips with a length of 1 cm and a width which corresponded to their distance from the next strip were examined. As can be seen in FIG. 1, there are two curvatures. A curvature within a strip and a curvature across all strips. These curvatures result in an inhomogeneity of the layers (see FIG. 5).
Ist eine Einzelstruktur lOOμm oder kleiner, so ist das Interface PS / Substrat gerade (Figur 2) . Dies wird dadurch verursacht, daß der Prozeß, der zur Interfacekrummung fuhrt, diese kleinen Strukturen nicht mehr auflost. Für Anwendung von PS, die unter¬ halb dieser Großenskala liegen, entfallt das Problem einer Inho- mogemtat von Filtern und Reflektoren aufgrund der Interface- krummung . In Figur 2 ist erkennbar, daß eine Strukturierung mit Photolack zu einem starken Unteratzen der Atzmaske fuhrt. Dieses kann durch ein anderes Atzmaskenmaterial z.B. durch Siliciumnitrid (Si3N4) verhindert werden [M. Kruger et al . , Thin solid films 276 (1996) 257-260]. Mit Hilfe dieser Maskentechnik ist es möglich eine Struktur aus PS herzustellen, die sowohl über ein gerades Interface PS / Substrat verfugen als auch über senkrechte Atzflanken. Mit diesen Voraussetzungen ist eine Herstellung von Schichtsystemen aus porösem Silicium möglich, deren Eigenschaften im Voraus bestimmt werden können.If a single structure is 100 μm or smaller, the PS / substrate interface is straight (FIG. 2). This is caused by the fact that the process that leads to interface curvature no longer dissolves these small structures. Application of PS that are below ¬ half this big scale, entfallt the problem of inhomogeneous mogemtat of filters and reflectors curvature due to the interface. It can be seen in FIG. 2 that structuring with photoresist leads to severe under-etching of the etching mask. This can be prevented by another etching mask material, for example by silicon nitride (Si 3 N 4 ) [M. Kruger et al. , Thin solid films 276 (1996) 257-260]. With the help of this mask technique it is possible to produce a structure made of PS, which has a straight interface PS / substrate as well as vertical etching flanks. With these requirements, it is possible to produce layer systems made of porous silicon, the properties of which can be determined in advance.
Zur Herstellung mehrerer poröser Bereiche auf demselben Wafer kann dies bisher gleichzeitig nur dann geschehen, wenn diese auch die gleichen Eigenschaften haben sollen. Sollen hingegen die Pixel unterschiedliche Eigenschaften haben, z.B. für ein Filterarray aus porösen Schichtsystemen, so können diese nicht gleichzeitig geätzt werden. Dies fuhrt nachteilig dazu, daß schon hergestellte poröse Schichten abgedeckt werden müssen, um sie beim Atzen der neuen Pixel in ihren Eigenschaften zu erhalten. Dieser Weg ist sehr schwierig und aufwendig zu realisieren und bis etzt noch nicht möglich, da diese Abdeckung ohne Einfluß auf die porösen Schichten ruckstandsfrei entfernt werden müßte .Up to now, for the production of several porous areas on the same wafer, this can only happen at the same time if they are also to have the same properties. However, should the pixels have different properties, e.g. for a filter array made of porous layer systems, they cannot be etched at the same time. This leads disadvantageously to the fact that porous layers which have already been produced have to be covered in order to maintain their properties when the new pixels are etched. This route is very difficult and expensive to implement and is not yet possible because this cover would have to be removed without leaving any residue on the porous layers.
Es ist deshalb Aufgabe der Erfindung ein Verfahren zur Herstellung einer porösen Schicht mit Hilfe eines elektrochemischen Ätzprozesses bereitzustellen, bei dem die genannten Nachteile vermieden werden.It is therefore an object of the invention to provide a method for producing a porous layer using an electrochemical etching process, in which the disadvantages mentioned are avoided.
Die Aufgabe wird gelost durch ein Verfahren gemäß der Gesamtheit der Merkmale nach Anspruch 1. Die Aufgabe wird ferner gelost durch ein optisches Bauelement gemäß der Gesamtheit der Merkmale nach Anspruch 5. Weitere zweckmäßige oder vorteilhafte Ausfuh- rungsformen oder Varianten finden sich in den auf jeweils einen dieser Ansprüche ruckbezogenen Unteranspruchen .The object is achieved by a method according to the entirety of the features according to claim 1. The task is further solved by an optical component according to the entirety of the features according to claim 5. Further expedient or advantageous embodiments Forms or variants can be found in the subclaims that are jerk-related to each of these claims.
Im Rahmen der Erfindung wird in an sich bekannter Weise die At- zung zur Porosidierung des Materials durchgeführt. Es wurde erkannt dabei eine Atzmaske geeigneter Geometrie mit auf die gewünschte Tiefenatzung abgestimmte Verhalten zu bilden und im er- finsdungsgemäßen Verfahren einzusetzen.In the context of the invention, the etching for porosidization of the material is carried out in a manner known per se. It was recognized here to form an etching mask of suitable geometry with behavior tailored to the desired deep etching and to use it in the method according to the invention.
Es wurde im Rahmen der Erfindung zudem erkannt, daß das gleichzeitige Herstellen von Pixeln innerhalb einer porosidierbaren Struktur mit unterschiedlichen Eigenschaften in einem Arbeitsgang möglich ist, wenn die Ätzrate jedes Pixels nicht nur durch die von außen angelegte Stromdichte vorgegeben ist, sondern auch noch durch die unterschiedliche Umgebung des Pixels mitbestimmt wird. Die Umgebung der Pixel kann durch die Atzmaske so gestaltet werden, daß die Pixel unterschiedliche Stromdichten und somit unterschiedliche Atzraten haben. Auf diese Weise können die gewünschten unterschiedlichen Eigenschaften erzielt werden.It was also recognized in the context of the invention that the simultaneous production of pixels within a porosidizable structure with different properties is possible in one operation if the etching rate of each pixel is not only determined by the current density applied from the outside, but also by the different Environment of the pixel is determined. The surroundings of the pixels can be designed by the etching mask in such a way that the pixels have different current densities and thus different etching rates. In this way the desired different properties can be achieved.
Auf diese Weise ermöglicht das erfindungsgemaße Verfahren, mehrere, insbesondere viele Arbeitsschritte durch einen einzigen Schritt geeigneter Ausbildung zu ersetzen. Ein weiterer Vorteil dieses Verfahrens ist darin gelegen, daß auch eine kontinuierli- ehe Veränderung der Eigenschaften einer porösen Schicht möglich ist. Dieses Verfahren kann für alle elektrochemischen Atzverfahren verwendet werden.In this way, the method according to the invention enables several, in particular many, work steps to be replaced by a single step of suitable design. Another advantage of this method is that a continuous change in the properties of a porous layer is also possible. This process can be used for all electrochemical etching processes.
Gemäß Patentanspruch 1 beinhaltet das Verfahren zur Herstellung einer porösen Schicht mit Hilfe eines elektrochemischen Ätzprozesses den Einsatz einer den erwünschten Verlauf der Tiefenätzrate entsprechenden Atzmaske.According to claim 1, the method for producing a porous layer using an electrochemical etching process includes the use of an etching mask corresponding to the desired course of the deep etching rate.
Gemäß Patentanspruch 2 wird das erfindungsgemaße Verfahren vor- teilhaft ausgebildet, indem zur Bildung eines kontinuierlichen Verlaufs der Tiefenätzrate eine keilförmige Atzmaske gewählt wird.According to claim 2, the method according to the invention is partially formed by selecting a wedge-shaped etching mask to form a continuous course of the deep etching rate.
Gemäß Patentanspruch 3 wird das erfindungsgemaße Verfahren dadurch vorteilhaft ausgebildet, daß zur Bildung eines diskreten Verlaufs der Tiefenätzrate eine eine oder mehrere, keilförmige stufenförmige Strukturen aufweisende Atzmaske gewählt wird.According to claim 3, the method according to the invention is advantageously embodied in that an etching mask having one or more wedge-shaped step-shaped structures is selected to form a discrete course of the deep etching rate.
Gemäß Patentanspruch 4 wird das erfindungsgemaße Verfahren vorteilhaft dadurch ausgeführt, daß als Ausgangsmaterial zur porösen Schichtbildung Silicium, Germanium oder Aluminium gewählt wird. Diese Materialien sind in ihrem Verhalten hinsichtlich Atzung vergleichsweise gut bekannt.According to claim 4, the inventive method is advantageously carried out in that silicon, germanium or aluminum is selected as the starting material for the porous layer formation. These materials are comparatively well known in their behavior with regard to etching.
Optische Bauelemente mit der erfmdungsgemaßen Schicht sind gemäß Patentanspruch 5 beansprucht.Optical components with the layer according to the invention are claimed according to claim 5.
Die Erfindung ist im weiteren an Hand von Figuren und Ausfuh- rungsbeispielen naher erläutert. Es zeigt:The invention is explained in more detail below on the basis of figures and exemplary embodiments. It shows:
Fig. 1: Tiefe geatzter poröser, als Stand der Technik bekannter Streifen, gemessen mit einem Surfaceprofiler nach Ent- fernung des porösen Siliciums durch Natronlauge (NaOH) ;1: Depth of etched porous strips known as prior art, measured with a surface profiler after removal of the porous silicon with sodium hydroxide solution (NaOH);
Fig. 2: Tiefe der porösen Streifen gemäß Figur 1, gemessen nach dem Entfernen der porösen Schicht mittels Natronlauge;2: Depth of the porous strips according to FIG. 1, measured after removal of the porous layer using sodium hydroxide solution;
Fig. 3: erfindungsgemaße Atzmaske für eine kontinuierliche Änderung der Atzrate; Fig. 4: erfindungsgemaße Oberflachenprofilmessung, gemessen nach dem Abatzen des porösen Bereiches.3: etching mask according to the invention for a continuous change in the etching rate; Fig. 4: Surface profile measurement according to the invention, measured after the porous area has been scratched off.
Fig. 5: Meßprinzip der Ti efenprof i 1 messungen .Fig. 5: Principle of measurement of the profi le measurements.
AusfuhrungsbeispielExemplary embodiment
In der Figur 1 ist die Tiefe der erfindungsgemäß geatzten poro- sen Streifen, gemessen mit einem Surfaceprofiler nach Entfernung des porösen Siliciums durch Natronlauge (NaOH) dargestellt. Die Streifenbreite der hier gezeigten Strukturen betrug 1000, 500 bzw. 250 μm.FIG. 1 shows the depth of the porous strips etched according to the invention, measured with a surface profiler after removal of the porous silicon by sodium hydroxide solution (NaOH). The stripe width of the structures shown here was 1000, 500 and 250 μm.
In der Figur 2 ist die gemessene Tiefe der erfindungsgemäß porösen Streifen nach dem Entfernen der porösen Schicht mittels Natronlauge gezeigt. Es läßt sich erkennen, daß im Falle einer Streifenbreite von lOOμm das Interface eines einzelnen Streifens nicht mehr gekrümmt, sondern gerade ausgebildet ist. Zu erkennen ist auch das Unteratzen unter die Maske, welche nur 100 μm breit war .FIG. 2 shows the measured depth of the porous strips according to the invention after the porous layer has been removed using sodium hydroxide solution. It can be seen that in the case of a stripe width of 100 μm, the interface of a single stripe is no longer curved, but is straight. You can also see the under-etching under the mask, which was only 100 μm wide.
In der Figur 3 ist die erfindungsgemäße Ätzmaske zur Erzielung einer kontinuierlichen Änderung der Ätzrate dargestellt. Diese Maske wird auf die zu ätzende Oberflache positioniert. Dabei werden die Oberflächenbereich unterhalb der dunklen Bereiche der erfindungsgemäßen Ätzmaske abgedeckt, die hellen Bereiche der Oberfläche werden geätzt. Auf diese Weise wird erreicht, daß im Streifen zwischen den beiden Keilstrukturen die Ätzrate kontinu- ierlich einstellbar oder veränderbar ist. Entlang der eingezeichneten Linie ABCD, wurde das Tiefenprofil auf diese Weise hergestellter erfindungsgemäßer poröser Schichten gemessen.FIG. 3 shows the etching mask according to the invention for achieving a continuous change in the etching rate. This mask is positioned on the surface to be etched. The surface areas below the dark areas of the etching mask according to the invention are covered, the light areas of the surface are etched. In this way it is achieved that the etching rate in the strip between the two wedge structures can be continuously adjusted or changed. The depth profile of porous layers according to the invention produced in this way was measured along the drawn line ABCD.
In der Figur 4 ist diese Oberflachenprofilmessung, gemessen nach dem Abatzen des erfindungsgemaßen porösen Bereiches im Ergebnis dargestellt. Zu erkennen ist das Interface zwischen porösem Silicium und dem kristallinen Silicium. Der Bereich, in dem die Atzrate mittels der lateralen Strukturierung kontinuierlich veränderlich ausgebildet wurde, ist zwischen den Punkten B und C gegeben.In FIG. 4, this surface profile measurement, measured after the porous area according to the invention has been scratched off, is the result shown. The interface between porous silicon and crystalline silicon can be seen. The area in which the etching rate was continuously changed by means of the lateral structuring is between points B and C.
Mit dem erfindungsgemaßen Verfahren ist die Möglichkeit gegeben, sowohl diskrete als auch kontinuierliche Veränderungen der Atzrate zu erreichen. Das Ausfuhrungsbeispiel zeigt eine kontmu- ierliche Änderung der Atzrate mit Hilfe der aus in Figur 3 dargestellten Atzmaske. Der Bereich, in dieser Effekt auftritt, befindet sich zwischen den beiden Keilstrukturen und damit zwischen den Punkten B und C. In diesem Bereich verandern die beiden keilförmigen Bereiche, die nicht geatzt werden, kontinuier- lieh die Atzrate, wie aus Figur 4 ersichtlich. With the method according to the invention, it is possible to achieve both discrete and continuous changes in the etching rate. The exemplary embodiment shows a continuous change in the etching rate with the aid of the etching mask shown in FIG. 3. The area in which this effect occurs is located between the two wedge structures and thus between points B and C. In this area, the two wedge-shaped areas that are not etched continuously change the etching rate, as can be seen from FIG. 4.
Claims
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19757560A DE19757560A1 (en) | 1997-12-23 | 1997-12-23 | Process for producing a porous layer using an electrochemical etching process |
| DE19757560 | 1997-12-23 | ||
| PCT/DE1998/003775 WO1999034421A1 (en) | 1997-12-23 | 1998-12-22 | Process for producing a porous layer by an electrochemical etching process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1042794A1 true EP1042794A1 (en) | 2000-10-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP98966576A Withdrawn EP1042794A1 (en) | 1997-12-23 | 1998-12-22 | Process for producing a porous layer by an electrochemical etching process |
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| Country | Link |
|---|---|
| US (1) | US6398943B1 (en) |
| EP (1) | EP1042794A1 (en) |
| JP (1) | JP2002500275A (en) |
| CA (1) | CA2315674A1 (en) |
| DE (1) | DE19757560A1 (en) |
| WO (1) | WO1999034421A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7244513B2 (en) * | 2003-02-21 | 2007-07-17 | Nano-Proprietary, Inc. | Stain-etched silicon powder |
| US7608789B2 (en) * | 2004-08-12 | 2009-10-27 | Epcos Ag | Component arrangement provided with a carrier substrate |
| DE102005008512B4 (en) | 2005-02-24 | 2016-06-23 | Epcos Ag | Electrical module with a MEMS microphone |
| DE102005008511B4 (en) | 2005-02-24 | 2019-09-12 | Tdk Corporation | MEMS microphone |
| DE102005053767B4 (en) * | 2005-11-10 | 2014-10-30 | Epcos Ag | MEMS microphone, method of manufacture and method of installation |
| DE102005053765B4 (en) * | 2005-11-10 | 2016-04-14 | Epcos Ag | MEMS package and method of manufacture |
| KR101374932B1 (en) * | 2007-09-28 | 2014-03-17 | 재단법인서울대학교산학협력재단 | The method for laterally graded porous optical filter by diffusion limited etch process and structure using thereof |
| DE102013106353B4 (en) * | 2013-06-18 | 2018-06-28 | Tdk Corporation | Method for applying a structured coating to a component |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3971710A (en) * | 1974-11-29 | 1976-07-27 | Ibm | Anodized articles and process of preparing same |
| JPS6027179B2 (en) * | 1975-11-05 | 1985-06-27 | 日本電気株式会社 | How to form porous silicon |
| DE4310205C1 (en) * | 1993-03-29 | 1994-06-16 | Siemens Ag | Prodn. of hole structure in silicon substrate - by producing pores in substrate by etching, forming mask on substrate and selectively etching |
| DE4319413C2 (en) * | 1993-06-14 | 1999-06-10 | Forschungszentrum Juelich Gmbh | Interference filter or dielectric mirror |
| DE19518371C1 (en) * | 1995-05-22 | 1996-10-24 | Forschungszentrum Juelich Gmbh | Etching process for porous silicon structure prodn |
-
1997
- 1997-12-23 DE DE19757560A patent/DE19757560A1/en not_active Withdrawn
-
1998
- 1998-12-22 WO PCT/DE1998/003775 patent/WO1999034421A1/en not_active Application Discontinuation
- 1998-12-22 EP EP98966576A patent/EP1042794A1/en not_active Withdrawn
- 1998-12-22 US US09/581,692 patent/US6398943B1/en not_active Expired - Fee Related
- 1998-12-22 JP JP2000526960A patent/JP2002500275A/en not_active Withdrawn
- 1998-12-22 CA CA002315674A patent/CA2315674A1/en not_active Abandoned
Non-Patent Citations (1)
| Title |
|---|
| See references of WO9934421A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2315674A1 (en) | 1999-07-08 |
| WO1999034421A1 (en) | 1999-07-08 |
| DE19757560A1 (en) | 1999-07-01 |
| JP2002500275A (en) | 2002-01-08 |
| US6398943B1 (en) | 2002-06-04 |
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