EP1036418A2 - Optimized border of semiconductor components - Google Patents

Abstract

The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating (MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b...) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a,...,11) such that an extensively constant course of the line of force which evades extreme values results between both metallic coatings (1, 31, MET1; 3, MET2) when reverse voltage or blocking voltage is applied between the interspaced metallic coatings.

Description

Optimized edge termination of semiconductor components

In the case of semiconductor components with at least one blocking pn junction, this comes somewhere between the live contacts to the surface of the substrate on and in which the semiconductor component is implemented. In these areas coming to the surface, high electric field strengths lead to the case that the pn junction is blocking, that is to say a higher voltage is present at the cathode than at the anode or a controllable semiconductor element has not yet been activated via its gate connection that undesirable leakage currents flow between the anode and the cathode, which are referred to as positive or negative reverse current depending on the direction of polarity of the voltage to be blocked or blocked. To reduce the proportion of the blocking currents which is caused by high field strengths in the edge region, edge terminations are used in the prior art, so-called "junction terminations", which, for example as specially shaped field plates, optimize the course of equipotential lines and accordingly avoid high field strengths lead in the edge area of such components, cf. DE-A 195 35 322 (Siemens) in column 3, line 58 to column 4, line 35 or "Multistep Field Plates ..." from IEEE Transactions on electron. devices, vol. 39, no. 6, June 1992, pages 1514 ff, "The Contour of an Optimal Field

Plate ", IEEE Transactions on electron. Devices, Vol. 35, No. 5, May 1988, pages 684 ff. And finally" Theoretical Investigation of Planar Junction Termination ", Solid-State Electronics, Vol. 39, No. 3, pages 323 to 328, 1996. The planar edge closures described there are optimized in terms of their geometry, on the one hand as a stepped field plate and on the other hand as an optimized, continuously curved field plate with a modified elliptical geometry, but so far it has not been successful in the prior art to optimize it to be able to economically produce the geometric structure of a field plate in the edge region of a lockable semiconductor component, in particular a component that can be subjected to a high voltage above 500V. The invention sees its task in producing the above-mentioned, in particular highly locking or lockable components on an economical basis, that is to say at low cost, and yet utilizing their maximum locking capability.

This is achieved with the invention when an edge region of the inner anode metallization has an insulator profile that has a flat beginning and continuously curved outward and upward shape, which region is the "region of curvature" of the insulator profile, and one thereon directly adjacent, practically flat "base area" which, together with the curvature area, defines the cross section of the insulator profile.

The insulator profile is designed in such a way that extreme values of an electrical field that arises during operation can be avoided between the curved inner metallization, which extends the anode outwards, and the outer metallization, which is usually the cathode, next to the base area of the insulator profile. The insulator profile is produced by a method in which an initially applied thick insulator layer is additionally covered on the entire substrate with a resist layer, which is illuminated in a structured manner by a mask, which changes in the gray tone value in accordance with the desired curvature in the curvature area of the respective insulator profile. The gray tone value in the mask is transferred to the resist layer by exposure, which can then be patterned, in particular by development, in order then to transfer the structure of the developed resist layer into the strong insulator layer using an etching process such as RIE (reactive ion etching), it is advantageous if the etching rate of the insulator layer and the etching rate of the remaining resist residues which remain after the development of the exposed resist layer are approximately the same, in order to avoid a non-conformal transfer of the resist profile into the insulator. The resulting insulator profiles can either run as a wall around the anode or a plurality of insulator profiles that are staggered outwards and have different curvatures can be provided. If several staggered isolator profiles are provided

(Claim 2, Claim 3), the curvature of the surfaces of the curvature regions is not the same, but rather increases with each profile lying further outside (Claim 3).

Metallizations are applied to the respective curved surfaces mentioned, which conductively merges into the anode metallization for the insulator profile which is directly adjacent on the outside to the inside anode.

The structuring of the exposure coded in the gray tone value takes place in such a way that a desired light intensity profile in the halftone process, i.e. via a pixel grid in which the mask is coded and the pixel sizes below the resolution limit of a reducing projection exposure are converted into an almost continuous exposure curve of the resist layer, which thus makes it possible to produce continuous surfaces that curve outwards and upwards; The isolator profiles designed according to the invention thus have at least one continuous surface (without steps) over a considerable area, which is designed in such a way that theoretical calculations for an optimized course of the field lines under reverse voltage stress or forward blocking stress appear favorable.

With the invention, the thickness of the insulator layer can be varied in a predetermined manner in a controlled manner in a process over a wide range up to 10 μm; it is not absolutely necessary to give the surface curvature an ideal course if it is only ensured that the substantial field strength increases can be avoided and the reverse voltage stress at the edge of the anode towards the cathode has no significant extreme values. Even in the case of semiconductor components with reverse voltages above approximately 500 V, the theoretically maximum possible reverse voltage can be achieved with a minimal space requirement for the edge termination, that is to say the "blocking capability" of the space taken up can be fully utilized. The minimum space requirement is the

Components of importance, which are manufactured in multiples from one wafer, and the highest possible utilization of the blocking ability becomes all the more important the higher the blocking voltages. These aspects are particularly important for high-blocking IGBTs.

The insulator profiles produced according to the invention can also be used advantageously in Schottky diodes which are not based on a pn junction but instead utilize the blocking capability of a metal-semiconductor junction. At the edge of the metal-semiconductor transition, the small effective radii of curvature would lead to enormous field increases. In order to avoid this, diffused guard rings are used according to the prior art, which, however, lead to an undesired injection of minority charge carriers in the event of high forward load. By means of the isolator profiles and field plates produced according to the invention, such an injection of charge carriers does not occur and the diffusion process during manufacture can be omitted.

It is particularly advantageous to use the invention, which is limited to measures on the surface of the semiconductors, even when power semiconductors based on silicon carbide (SiC), as an example of a semiconductor with a high band gap, are to be improved (claim 12) . With these, an extremely low diffusion constant for dopants has to be accepted and therefore edge regions can practically not be produced by diffusion.

With the insulator profiles produced according to the invention, the component has those which do not run out continuously or continuously at the transition to the anode, but with a small jump in the order of magnitude of above 5 nm and below End 50 nm. This step is very low compared to the thickness of the metallization and is practically insignificant, but results from the manufacturing process using gray-tone lithography. For example, the metallization can be approximately 1 μm thick, while the “jump” of the isolator at the end of the curvature region of the isolator produced by gray-tone lithography is 20 nm.

The gray tone lithography works in such a way that the substrate is covered with an insulator layer, which is first covered with a light-sensitive layer, which is exposed in such a way that the curvature of the surface of the insulator profile is varied by gray tone, that is to say by adapting the light intensity distribution to the shape of the insulator profile, is exposed in the photoresist layer, which is then structured by development (claim 11). The photoresist layer structured in this way now still consists of resist residues which form blocks on the insulator layer which correspond to the insulator profiles. By means of an etching technique, for example a dry etching process, the resist residue still above the substrate surface is etched conformally into the insulator layer, the insulator layer being removed essentially over the entire area and being removed more strongly where the resist residues are not (claim 6).

The correct transfer is favored if the etching rates of the resist residues and the insulator layer are the same; if they are different, the shape of the resist residue must be adapted accordingly, which can be done by adjusting the intensity distribution during the exposure.

The height of the insulator profile in the base area can be chosen rather higher or rather lower (claim 4, claim 5). If the insulator profile in the base area has a height of above approximately 5 μm, the inclination at the end of the curvature area in the transition to the base area is above 10 °. The area of curvature ends here steeper than in the insulator profile, which is flat in the base area (claim 5). With a higher base area, the tooo

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is diffused in and which, when voltage is present, transfers the potential present at the corresponding location from the substrate area to the respective metallization (claim 10). The doping of these diffused strip-shaped zones essentially corresponds to the doping chosen in a p + region below the anode metallization.

The penetration depth of the diffused zones below the metallization is preferably only small, preferably below 10 μm, which does not give rise to field peaks technologically. The p ⁺ diffusion zones transfer their potential to the respective metallization that curves outwards and upwards (away from the substrate).

The lateral extent of the metallic curvature areas should be matched to the space charge depth and should correspond to about two to three times the space charge depth.

The invention (s) are explained and supplemented below using several exemplary embodiments.

FIG. 1 shows in cross section a section of an active part of a lockable semiconductor element, here a diode with anode 1 and cathode 2, 3, and an edge region of the anode, which is designed by means of a planar edge termination, here a field plate, as shown in FIGS. 3 in enlarged form of the AV area. FIG. 2a is an illustration of the structuring of a photoresist layer 20 which is initially present over the entire surface and, after structuring (by exposure) with the shape 20a shown, is transferred conformally into the insulator 10 by means of dry etching 60, here a reactive ion etching (RIE). Figure 2b corresponds to Figure 2a, a representation of staggered resist profiles 20b, 20c, 20d, which are arranged in series on the insulator 10 to the outside, starting with reactive ion etching 60, the resist residues (resist profiles), which already have the shape desired Have insulator profiles in the

Insulator layer 10 to transfer conform. FIG. 3a is a section through a finished edge finish, which was created after completion of the reactive ion etching 60 according to FIG. 2a and with a metallization 30a, the anode metallization 1 in the region of curvature

KB of the insulator profile 10a extended. The insulator profile 10a has a width which corresponds to approximately 10 to 15 times the height h _1Q . With a selected height of 10 μm, for example, there is a lateral extension of the profile of 100 μm, which is strongly dependent on the desired blocking voltage. FIG. 3 b is a result of the finished production process for the staggered insulator profiles, which were started according to FIG. 2 b, to be transferred into the insulator layer 10. For example, there are three insulator profiles 10b, 10c, 10d staggered outwards, the curvatures of which become steeper towards the outside. Again, the figure is only a schematic explanation, with the Cut lines "S" take out a large area of unchanged shape. FIG. 4 and FIG. 4a are a representation of a flatter insulator profile 11, which has a small one towards the anode 31 at the inner end

Level 11s at a height "d", which is illustrated in the enlargement of Figure 4a. This step is less than 50 nm, preferably it is in the order of magnitude between 20 nm and 30 nm in the case of a metallization 31, 31a, 31b overlying it with a

Thickness of about 1 μm. In FIG. 4, the flat insulator profile is supplemented with a metallic shield 32 which, starting from the anode metallization 31, is designed in the manner of a hood and an elliptical shape which extends laterally outwards and upwards following the curvature of the metallization. A potting compound 41 insulates the area between the anode, metallic hood 32 and cathode 3, outside the end of the insulator profile, which here has a lateral size of approximately 50 times to 200 times the height of the

Profile 11 has in the base area. Figure 5 schematically illustrates the structure of a

Gray-tone lithography produced insulator profile with curvature area KB and extensive base area SB, the latter of which has an approximately constant height "h", while the curvature area drops from the constant height in a steady course towards the anode and there, preferably through a small step 11s, to the level of the substrate 9 arrives. A metallization MET1 is applied in the area of curvature, it extends the anode metallization 1.31 and allows a controlled course of the field lines between the anode and the outer cathode MET2 without strong extreme values.

FIG. 6 is an approximately true-to-scale illustration of the

Arrangement of Figure 4 with a flat base area SB of the insulator profile.

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3 P- Φ

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P- Φ μ- Q X cQ P- P p- tr φ o P CQ Q P d p- • P CQ P CQ φ P μ-

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Φ N = N rt tr P- CQ P P rt ΪΛ> Q φ P- d Φ P 1— 'tr L7S P CQ P Z tr Hi p

Ω 0 0 Φ Φ φ P -j P Φ CQ Hl μ- P μ- i-i Φ 0- Qi P = φ CQ

Pf P P P- P d tr Φ ii CQ φ P- rt Ω CQ rt P Hi P- p o! - 'rt rt Φ rt P <! P P Ω - P. p Φ l_l- tr φ P 0 Φ rt to rt P P 0 d CQ f P 0 = ω i-i φ N Hl P 1— 'P P co co rt y- rt d α Q d CQ P rt

Q P Φ 0 P tr Φ φ P φ φ P Qi Φ y— p- Φ

Φ 3 P CQ 1-i ti Φ PP p, P ~ φ

has already been explained. Outside the outermost insulator profile 10d is the cathode metallization 3 with a channel stopper 7, as explained in FIG. 3a. The respective cutting areas S cut out those laterally wide areas in which no change in shape is provided.

The diffused zones 8, 7b, 7a below the metallizations in FIGS. 3a and 3b have only a small penetration depth of less than 10 μm, preferably 3 to 6 μm.

The semiconductor acc. Figure 3b is very inexpensive to manufacture because the insulator profiles have only a small height h _1Q in the base area SB. The height h ₁₀ will be less than 5 μm, preferably in the order of 2 μm.

In operation with reverse voltage or blocking voltage, the three staggered metallizations described are located at different potentials from the anode 1 via the first stage 1 ′ with a curved region 30c and the second stage 1 ″ with a curved region 30d, which are present from the potential-transmitting zones 7b, 7a The extent of the potential-transmitting zones 7a, 7b diffused from the crystal region of the substrate 9, which are not deeply diffused in, are selected such that they begin in each case below the outer end region of the base region of the insulator profile and outwardly approximately up to that Extend area in which the insulator profile lying further out with its curvature area KB begins to arise or rise.

The production of the geometries of FIGS. 3a and 3b will be explained using FIGS. 2a and 2b.

The substrate 9 is shown in FIG. 2a, with an insulator layer 10 formed thereon, usually made of silicon oxide. FIG. 2a shows the starting point at which a shape 20a formed after structuring (by exposure) Resist profiles or resist residues from a photoresist layer 20 which is present over the entire surface (shown in broken lines) is transferred in conformity to the insulator layer 10 underneath. A dry etching process, here a reactive ion etching by ion radiation 60, is shown as the etching process. A diffused region 8 (p ⁺ diffusion region) under the anode to be produced and a diffused channel stopper 7 with an n ⁺ diffusion region (outside the resist profile to be formed) are previously introduced into the substrate 9. An insulator 10 is applied uniformly to the substrate 9 prepared in this way and has essentially the height that a later resist profile in the base region SB of FIG. 3a is to have. An additional resist layer 20 is applied to the insulator profile, which is first illuminated in a structured manner by a mask, which mask changes in the gray tone value in accordance with the respective curvature in the curvature region KB of the insulator profile. The gray tone value in the mask (not shown) is transferred by the exposure into the resist layer 20, which is then patterned (in particular by development), and then in the etching process shown in FIG. 2a, the resist residues remaining after the exposure and development into the insulator layer 10 to be transferred, figuratively speaking the surface of the previous resist layer 20 is lowered onto the surface of the substrate, that is to say the remaining resist relief 20a is lowered into the insulator layer (figuratively speaking) as an insulator profile. The insulator 10 is removed where there are no resist blocks, is less removed where the height of the resist residue 20a is low, and where the resist residue 20a is to form the base region SB, little or nothing is removed from the insulator height. After conforming the resist residue 20a into the insulator layer 10, this creates a design of the insulator profile 10a with a curvature area KB and a base area SB, as shown in FIG. 3a, only without metallizations 1,3. This

Metallizations are then applied, possibly also the wall-like casting compound 40, in order to complete the edge closure. For conformal imaging, it is advantageous to make the etching rate of the insulator layer 10 and the etching rate of the remaining resist residues 20a essentially the same, so that no distortions occur when the base profile is formed, in particular in the region of curvature KB. If a conformal image is obtained, the angle of inclination α- of the resist residue 20a is shown directly in the angle of inclination α ^ in the slope at the upper end of the metallization 30a in FIG. 3a, or the surface OF of the region of curvature KB is in the laterally outer one End range this slope.

The structure of FIG. 3b is produced in the same way according to the production method shown schematically in FIG. 2b, which takes place analogously to the manufacture of FIG. Here, in the same number of process steps, a staggered arrangement of insulator profiles 10b, 10c, 10d has been imaged from resist residues 20b, 20c, 20d, corresponding to the resist residue 20a from FIG. 2a.

The starting point in FIG. 2b is also the flat one

Resist layer 20 is patterned illuminated and resist residues leaves that are conformally mapped in the thinner here chosen insulator 10 by a dry etching process 60, the height h _j _g microns in the size range of less than 5, in particular 2 microns for the staggered arrangement is located.

Before applying the insulator layer 10, as already explained in FIG. 3b, the potential-transmitting zones or - in the case of a circular design - rings 7a, 7b are diffused into an n ^~ substrate 9, these zones being placed in such a way that they lie below that area of the insulator 10 come to rest, in which the flat resist layer 20 is virtually completely removed by the development.

The ratio of the slopes at the top of each

Areas of curvature of the resist residues 20b, 20c, 20d can be identified with a. ^> A. > oi2 are expressed, i.e. an increasing inclination at the upper end of the curvature range for everyone lying further out Resist residue, which translates into a correspondingly increasing inclination of the upper end of the staggered curvature areas KB of FIG. 3b.

To clarify the upper end of the curvature area KB, that is to say the transition area between the curvature area and the base area, FIG. 5 shows an enlarged detail from either FIG. 3a or the outer step of the field plate 1 "of FIG. 3b. FIG. 5 is subdivided into a left-hand curvature area KB with a lateral extension b- ^ and in a base region SB with a lateral extension b _2. Below the insulator profile (comprising the curvature region and the base region) the substrate 9 is arranged. To the right of the base region the outer metallization MET2 begins with a thickness d _m , left of that

The base region at the upper end of the curvature region KB begins the inner metallization MET1 which runs inwards and which is applied to a correspondingly curved surface OF with a thickness d _m . The angle of inclination a at the upper end of the curvature area is shown. For the examples in FIG. 3a or 3b, it corresponds to the angle a. ^ Or α ^. The height h of the base area SB corresponds to the height h _1Q of FIGS. 3a, 3b.

Figure 4 with its enlarged detail in Figure 4a shows an insulator profile 11, which can be designed in accordance with the flat insulator profile of Figure 3b, but does not consist of several staggered arrangements, but has a hood 32 which extends above the insulator profile and acts as a shield with an outer curved area 32a is used. It is connected in a galvanically conductive manner to the anode 31 (above the p ⁺ diffusion region 8) and extends first upwards and then laterally outwards with a constant height ₄₁ . The area between the lower surface of the hood 32 and the insulator profile and the metallization 31, 31a, 31b is filled with a casting compound 41, which has an insulating effect. Figure 4 is not to scale, instead the structural elements are to be explained on it. One as An example of an imaginary, approximately true-to-scale design of the arrangement according to FIG. 4 is shown in FIG. 6.

A detail of the inner end of the curvature region KB of the

Insulator profile 11 are explained. This inner end, which essentially begins at the outer end of the p ⁺ diffusion zone 8, is provided with a step 11s which is formed on the order of 20 nm to 30 nm; it can also deviate from these values, but is usually less than 50 nm high, which height is marked with "d". This stage arises in the manufacturing process according to FIGS. 2a, 2b and follows from the gradation of the gray tone value of the mask during the exposure. The gray tone value cannot decrease infinitely finely to zero (permeable mask), so that from a minimum gray tone value no further grading takes place and during exposure the step 11s initially occurs in the resist residue 20a or 20b and then in the insulator 10 by dry etching 60 is transmitted. In the area of the step 11s, the course of the metallization 31 to the curvature area 31b, which runs continuously without a step, also has a slight increase 31a, which, however, is hardly noticeable at a metallization thickness of mostly 1 μm compared to the preferred step height "d" in the range of 50 nm and extreme values not caused in the field line course.

A second detail can only be seen schematically in FIG. 4, it is the radius of curvature r = r ^ ₂ ^a ^ - ^s quarter circle in the curved region 32a of the hood 32 that is preferably selected here. It begins at the distance b-, _Q from the upper end of the curved metallization 31b, which distance is significantly larger than shown in Figure 4 and is shown in Figure 6 in a specific example to scale. In this example, this distance essentially corresponds to the radius of curvature r in the quarter circle 32a of the hood 32 above the base region SB of the insulator 10.

The insulator 10 here has a flat height h- _j n according to FIG. 3b, which is below 5 μm and is preferably located at 2 μm. The radius r, represented as r ₃₂ in FIG. 4, has a dimension of 100 μm, for example, and the distance b _1Q according to FIG. 4 is also formed.

In the example in FIG. 6, the lateral is also suitable for this

Extension of the curvature region KB of the insulator profile 11 is provided with a width b ₉ which essentially corresponds to the width b _1Q . The distance between the lower surface of the hood 32 and the curved field plate 31b in the region of curvature and the base region 10 is in the example between 10 μm and 30 μm, represented by h ₄ ^, as shown in FIG. 4. This area, like the area of curvature and the area located laterally further out, is filled with a casting compound 41. It isolates and forms a mechanical stabilization.

A lockable semiconductor component is an IGBT, thyristor, GTO or diode, in particular. Schottky diode. In the edge area of an anode metallization (1.31), an insulator profile (10a, 10b, 10c, 10d, ll) with a curvature area (KB) and base area (SB) is provided (directly) on the substrate (9) of the component. which insulator profile in the curvature area (KB) has a surface (OF) which, starting flat, runs more and more curved outwards and upwards. On the surface (OF) is one of the

Surface curvature following, the inner anode metallization laterally extending metallization (METl; 30a, 30b, 30c, 30d, 31b) applied. The end of the metallization (MET1; 30a, 30b ...) is insulated from the surrounding metallization (MET2; 3) by the circumferential base area (SB) of the insulator profile (10a, 11).

A largely continuous field line course avoiding extreme values arises between the two metallizations (1, 31, METl; 3, MET2) when applying

Reverse voltage or blocking voltage between the spaced metallizations.

Claims

Expectations: 1. Lockable semiconductor component, such as IGBT, thyristor, GTO or diode, in particular Schottky diode, in which (a) in the edge region of an anode metallization (1,31) a (directly in the edge region) on the substrate (9) of the component Insulator profile (10a, 10b, 10c, 10d, 11) with curvature area (KB) and base area (SB) is provided, which isolator profile in the curvature area (KB) one Surface (OF), which starts out flat and steadily curved outwards and upwards; (b) on the surface (OF) directly following the surface curvature and laterally extending the inner anode metallization (METl; 30a, 30b, 30c, 30d, 31b) is applied; (c) around the top of the curved metallization (METl; 30a, 30b ...) by the circumferential base area (SB) of the insulator profile (10a, ..., 11) from an outer metallization (MET2; 3) surrounding them in an insulating manner so that a largely continuous, extreme value avoiding field line course between the two metallizations (1, 31, MET1; 3, MET2) - when reverse voltage or blocking voltage is applied between the spaced metallizations. 2. The component according to claim 1, wherein several Insulator profiles (10b, 10c, lOd), in particular two or three insulator profiles with respective curvature area (KB) and base area (SB) are staggered around the internal anode metallization (1), all of which are fixed on the substrate (9) , wherein the curved metallization (30b) of the innermost insulator profile is transferred into the anode metallization (1) and the surrounding outer metallization (3) of the outermost Insulator profile (lOd) is the cathode metallization (3) of the component. n lf » 3 P CQ CQ Φ . -, M - Φ P- P Q Φ tr P P Ω tr rt μ- CQ rt . . Lockable semiconductor component according to one of the preceding claims for power electronics; or method for producing an edge region of this component, in which the insulator profile (10a, 10b) with the surface (OF) running without steps in the Edge area of an anode (1; 31) is produced or can be produced by gray-tone lithography, wherein (a) the substrate (9) is covered with an insulator layer (10) between 0.5 μm and 15 μm thick; (b) the strong insulator layer is covered with a photosensitive layer (photoresist layer; 20); (c) the photoresist layer (20) is exposed via a mask which changes in the gray tone value in accordance with the curvature of the surface (OF) of at least one insulator profile (10a, 10b, 10c, 10d) and then with the formation of at least one resist residue (20a, 20b, 20c , 2 Od) is structured; (d) the structured photoresist layer (20a, 20b, 20c, 20d) and the insulator layer (10) are essentially removed with a dry etching process in order to transfer the at least one resist residue - defined by the structuring - into the insulator (10) in the correct shape and to form at least one insulator profile around the anode (1; 31) (10a, 10b, 10c, 10d). Component according to Claim 5, in which the curvature (32a, r) of the hood (32), in particular running as a quarter circle, is larger or stronger than the curvature of the laterally elongated metallization (31b). 8. The component according to one of claims 1 to 4, wherein a transition (31a) of the curved metallization (31b) to the anode metallization (31) via a small step (d) of the insulator profile at the inner end of the curvature region (KB ^ of the insulator profile (11) takes place, the small step being of the order of magnitude of 5 nm to 30 nm, so that the insulator profile for the anode metallization (31) does not run out completely without any steps. μ> HHHH 10 1 ^ 00 t H O •